quark_x10xx: add new target quark_x10xx

Intel Quark X10xx SoC debug support added
Lakemont version 1 (LMT1) is the x86 core in Quark X10xx SoC
Generic x86 32-bit code is in x86_32_common.c/h

Change-Id: If2bf77275cd0277a82558cd9895b4c66155cf368
Signed-off-by: adrian.burns@intel.com
Reviewed-on: http://openocd.zylin.com/1829
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
__archive__
Adrian Burns 2014-02-06 17:11:15 +00:00 committed by Andreas Fritiofson
parent 005d85d56c
commit 1338cf60b9
11 changed files with 3193 additions and 5 deletions

2
README
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@ -117,7 +117,7 @@ Debug targets
ARM11, ARM7, ARM9, AVR32, Cortex-A, Cortex-R, Cortex-M, ARM11, ARM7, ARM9, AVR32, Cortex-A, Cortex-R, Cortex-M,
Feroceon/Dragonite, DSP563xx, DSP5680xx, FA526, MIPS EJTAG, NDS32, Feroceon/Dragonite, DSP563xx, DSP5680xx, FA526, MIPS EJTAG, NDS32,
XScale. XScale, Intel Quark.
Flash drivers Flash drivers
------------- -------------

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@ -156,9 +156,9 @@ USB-based, parallel port-based, and other standalone boxes that run
OpenOCD internally. @xref{Debug Adapter Hardware}. OpenOCD internally. @xref{Debug Adapter Hardware}.
@b{GDB Debug:} It allows ARM7 (ARM7TDMI and ARM720t), ARM9 (ARM920T, @b{GDB Debug:} It allows ARM7 (ARM7TDMI and ARM720t), ARM9 (ARM920T,
ARM922T, ARM926EJ--S, ARM966E--S), XScale (PXA25x, IXP42x) and ARM922T, ARM926EJ--S, ARM966E--S), XScale (PXA25x, IXP42x), Cortex-M3
Cortex-M3 (Stellaris LM3, ST STM32 and Energy Micro EFM32) based cores to be (Stellaris LM3, ST STM32 and Energy Micro EFM32) and Intel Quark (x10xx)
debugged via the GDB protocol. based cores to be debugged via the GDB protocol.
@b{Flash Programming:} Flash writing is supported for external @b{Flash Programming:} Flash writing is supported for external
CFI-compatible NOR flashes (Intel and AMD/Spansion command set) and several CFI-compatible NOR flashes (Intel and AMD/Spansion command set) and several
@ -7542,6 +7542,47 @@ the peripherals.
@xref{targetevents,,Target Events}. @xref{targetevents,,Target Events}.
@end deffn @end deffn
@section Intel Architecture
Intel Quark X10xx is the first product in the Quark family of SoCs. It is an IA-32
(Pentium x86 ISA) compatible SoC. The core CPU in the X10xx is codenamed Lakemont.
Lakemont version 1 (LMT1) is used in X10xx. The CPU TAP (Lakemont TAP) is used for
software debug and the CLTAP is used for SoC level operations.
Useful docs are here: https://communities.intel.com/community/makers/documentation
@itemize
@item Intel Quark SoC X1000 OpenOCD/GDB/Eclipse App Note (web search for doc num 330015)
@item Intel Quark SoC X1000 Debug Operations User Guide (web search for doc num 329866)
@item Intel Quark SoC X1000 Datasheet (web search for doc num 329676)
@end itemize
@subsection x86 32-bit specific commands
The three main address spaces for x86 are memory, I/O and configuration space.
These commands allow a user to read and write to the 64Kbyte I/O address space.
@deffn Command {x86_32 idw} address
Display the contents of a 32-bit I/O port from address range 0x0000 - 0xffff.
@end deffn
@deffn Command {x86_32 idh} address
Display the contents of a 16-bit I/O port from address range 0x0000 - 0xffff.
@end deffn
@deffn Command {x86_32 idb} address
Display the contents of a 8-bit I/O port from address range 0x0000 - 0xffff.
@end deffn
@deffn Command {x86_32 iww} address
Write the contents of a 32-bit I/O port to address range 0x0000 - 0xffff.
@end deffn
@deffn Command {x86_32 iwh} address
Write the contents of a 16-bit I/O port to address range 0x0000 - 0xffff.
@end deffn
@deffn Command {x86_32 iwb} address
Write the contents of a 8-bit I/O port to address range 0x0000 - 0xffff.
@end deffn
@section OpenRISC Architecture @section OpenRISC Architecture
The OpenRISC CPU is a soft core. It is used in a programmable SoC which can be The OpenRISC CPU is a soft core. It is used in a programmable SoC which can be

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@ -35,6 +35,7 @@ libtarget_la_SOURCES = \
$(AVR32_SRC) \ $(AVR32_SRC) \
$(MIPS32_SRC) \ $(MIPS32_SRC) \
$(NDS32_SRC) \ $(NDS32_SRC) \
$(INTEL_IA32_SRC) \
avrt.c \ avrt.c \
dsp563xx.c \ dsp563xx.c \
dsp563xx_once.c \ dsp563xx_once.c \
@ -124,6 +125,10 @@ NDS32_SRC = \
nds32_v3m.c \ nds32_v3m.c \
nds32_aice.c nds32_aice.c
INTEL_IA32_SRC = \
quark_x10xx.c \
lakemont.c \
x86_32_common.c
noinst_HEADERS = \ noinst_HEADERS = \
algorithm.h \ algorithm.h \
@ -191,7 +196,9 @@ noinst_HEADERS = \
nds32_v3_common.h \ nds32_v3_common.h \
nds32_v3.h \ nds32_v3.h \
nds32_v3m.h \ nds32_v3m.h \
nds32_aice.h nds32_aice.h \
lakemont.h \
x86_32_common.h
ocddatadir = $(pkglibdir) ocddatadir = $(pkglibdir)
nobase_dist_ocddata_DATA = nobase_dist_ocddata_DATA =

1111
src/target/lakemont.c Normal file

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103
src/target/lakemont.h Normal file
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@ -0,0 +1,103 @@
/*
* Copyright(c) 2013 Intel Corporation.
*
* Adrian Burns (adrian.burns@intel.com)
* Thomas Faust (thomas.faust@intel.com)
* Ivan De Cesaris (ivan.de.cesaris@intel.com)
* Julien Carreno (julien.carreno@intel.com)
* Jeffrey Maxwell (jeffrey.r.maxwell@intel.com)
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
*
* Contact Information:
* Intel Corporation
*/
/*
* @file
* This is the interface to the probemode operations for Lakemont 1 (LMT1).
*/
#ifndef LAKEMONT_H
#define LAKEMONT_H
#include <jtag/jtag.h>
/* The Intel Quark SoC X1000 Core is codenamed lakemont */
#define LMT_IRLEN 8
/* lakemont tap instruction opcodes */
#define IDCODE 2
#define SUBMITPIR 3
#define PROBEMODE 4
#define WRPIR 6
#define RDWRPDR 8
#define TAPSTATUS 11
#define BYPASS 255
#define NOT_NULL 2
/* DR sizes */
#define ID_SIZE 32
#define PM_SIZE 1
#define PIR_SIZE 64
#define PDR_SIZE 32
#define TS_SIZE 32
#define BP_SIZE 1
#define MAX_SCAN_SIZE PIR_SIZE
/* needed during lakemont probemode */
#define NOT_PMREG 0xfe
#define NOT_AVAIL_REG 0xff
#define PM_DSB 0x00000000
#define PM_DSL 0xFFFFFFFF
#define PM_DSAR 0x004F9300
#define PM_DR7 0x00000400
#define DELAY_SUBMITPIR 0 /* for now 0 is working */
/* lakemont tapstatus bits */
#define TS_PRDY_BIT 0x00000001
#define TS_EN_PM_BIT 0x00000002
#define TS_PM_BIT 0x00000004
#define TS_PMCR_BIT 0x00000008
#define TS_SBP_BIT 0x00000010
struct lakemont_core_reg {
uint32_t num;
struct target *target;
struct x86_32_common *x86_32_common;
uint64_t op;
uint8_t pm_idx;
};
struct scan_blk {
uint8_t out[MAX_SCAN_SIZE]; /* scanned out to the tap */
uint8_t in[MAX_SCAN_SIZE]; /* in to our capture buf */
struct scan_field field;
};
#define I(name) (((struct lakemont_core_reg *)x86_32->cache->reg_list[name].arch_info)->pm_idx)
int lakemont_init_target(struct command_context *cmd_ctx, struct target *t);
int lakemont_init_arch_info(struct target *t, struct x86_32_common *x86_32);
int lakemont_poll(struct target *t);
int lakemont_arch_state(struct target *t);
int lakemont_halt(struct target *t);
int lakemont_resume(struct target *t, int current, uint32_t address,
int handle_breakpoints, int debug_execution);
int lakemont_step(struct target *t, int current,
uint32_t address, int handle_breakpoints);
int lakemont_reset_assert(struct target *t);
int lakemont_reset_deassert(struct target *t);
#endif /* LAKEMONT_H */

97
src/target/quark_x10xx.c Normal file
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@ -0,0 +1,97 @@
/*
* Copyright(c) 2013 Intel Corporation.
*
* Adrian Burns (adrian.burns@intel.com)
* Thomas Faust (thomas.faust@intel.com)
* Ivan De Cesaris (ivan.de.cesaris@intel.com)
* Julien Carreno (julien.carreno@intel.com)
* Jeffrey Maxwell (jeffrey.r.maxwell@intel.com)
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
*
* Contact Information:
* Intel Corporation
*/
/*
* @file
* Debugger for Intel Quark SoC X1000
* Intel Quark X10xx is the first product in the Quark family of SoCs.
* It is an IA-32 (Pentium x86 ISA) compatible SoC. The core CPU in the
* X10xx is codenamed Lakemont. Lakemont version 1 (LMT1) is used in X10xx.
* The CPU TAP (Lakemont TAP) is used for software debug and the CLTAP is
* used for SoC level operations.
* Useful docs are here: https://communities.intel.com/community/makers/documentation
* Intel Quark SoC X1000 OpenOCD/GDB/Eclipse App Note (web search for doc num 330015)
* Intel Quark SoC X1000 Debug Operations User Guide (web search for doc num 329866)
* Intel Quark SoC X1000 Datasheet (web search for doc num 329676)
*
* This file implements any Quark SoC specific features such as resetbreak (TODO)
*/
#ifdef HAVE_CONFIG_H
#include "config.h"
#endif
#include <helper/log.h>
#include "target.h"
#include "target_type.h"
#include "lakemont.h"
#include "x86_32_common.h"
int quark_x10xx_target_create(struct target *t, Jim_Interp *interp)
{
struct x86_32_common *x86_32 = calloc(1, sizeof(struct x86_32_common));
if (x86_32 == NULL) {
LOG_ERROR("%s out of memory", __func__);
return ERROR_FAIL;
}
x86_32_common_init_arch_info(t, x86_32);
lakemont_init_arch_info(t, x86_32);
return ERROR_OK;
}
int quark_x10xx_init_target(struct command_context *cmd_ctx, struct target *t)
{
return lakemont_init_target(cmd_ctx, t);
}
struct target_type quark_x10xx_target = {
.name = "quark_x10xx",
/* Quark X1000 SoC */
.target_create = quark_x10xx_target_create,
.init_target = quark_x10xx_init_target,
/* lakemont probemode specific code */
.poll = lakemont_poll,
.arch_state = lakemont_arch_state,
.halt = lakemont_halt,
.resume = lakemont_resume,
.step = lakemont_step,
.assert_reset = lakemont_reset_assert,
.deassert_reset = lakemont_reset_deassert,
/* common x86 code */
.commands = x86_32_command_handlers,
.get_gdb_reg_list = x86_32_get_gdb_reg_list,
.read_memory = x86_32_common_read_memory,
.write_memory = x86_32_common_write_memory,
.add_breakpoint = x86_32_common_add_breakpoint,
.remove_breakpoint = x86_32_common_remove_breakpoint,
.add_watchpoint = x86_32_common_add_watchpoint,
.remove_watchpoint = x86_32_common_remove_watchpoint,
.virt2phys = x86_32_common_virt2phys,
.read_phys_memory = x86_32_common_read_phys_mem,
.write_phys_memory = x86_32_common_write_phys_mem,
.mmu = x86_32_common_mmu,
};

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@ -102,6 +102,7 @@ extern struct target_type nds32_v2_target;
extern struct target_type nds32_v3_target; extern struct target_type nds32_v3_target;
extern struct target_type nds32_v3m_target; extern struct target_type nds32_v3m_target;
extern struct target_type or1k_target; extern struct target_type or1k_target;
extern struct target_type quark_x10xx_target;
static struct target_type *target_types[] = { static struct target_type *target_types[] = {
&arm7tdmi_target, &arm7tdmi_target,
@ -130,6 +131,7 @@ static struct target_type *target_types[] = {
&nds32_v3_target, &nds32_v3_target,
&nds32_v3m_target, &nds32_v3m_target,
&or1k_target, &or1k_target,
&quark_x10xx_target,
NULL, NULL,
}; };

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@ -0,0 +1,323 @@
/*
* Copyright(c) 2013 Intel Corporation.
*
* Adrian Burns (adrian.burns@intel.com)
* Thomas Faust (thomas.faust@intel.com)
* Ivan De Cesaris (ivan.de.cesaris@intel.com)
* Julien Carreno (julien.carreno@intel.com)
* Jeffrey Maxwell (jeffrey.r.maxwell@intel.com)
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
*
* Contact Information:
* Intel Corporation
*/
/*
* @file
* This is the interface to the x86 32 bit memory and breakpoint operations.
*/
#ifndef X86_32_COMMON_H
#define X86_32_COMMON_H
#include <jtag/jtag.h>
#include <helper/command.h>
extern const struct command_registration x86_32_command_handlers[];
/* for memory access */
#define BYTE 1
#define WORD 2
#define DWORD 4
#define EFLAGS_TF 0x00000100 /* Trap Flag */
#define EFLAGS_IF 0x00000200 /* Interrupt Flag */
#define EFLAGS_RF 0x00010000 /* Resume Flag */
#define EFLAGS_VM86 0x00020000 /* Virtual 8086 Mode */
#define CSAR_DPL 0x00006000
#define CSAR_D 0x00400000
#define SSAR_DPL 0x00006000
#define CR0_PE 0x00000001 /* Protected Mode Enable */
#define CR0_NW 0x20000000 /* Non Write-Through */
#define CR0_CD 0x40000000 /* Cache Disable */
#define CR0_PG 0x80000000 /* Paging Enable */
/* TODO - move back to PM specific file */
#define PM_DR6 0xFFFF0FF0
#define DR6_BRKDETECT_0 0x00000001 /* B0 through B3 */
#define DR6_BRKDETECT_1 0x00000002 /* breakpoint condition detected */
#define DR6_BRKDETECT_2 0x00000004
#define DR6_BRKDETECT_3 0x00000008
enum {
/* general purpose registers */
EAX = 0,
ECX,
EDX,
EBX,
ESP,
EBP,
ESI,
EDI,
/* instruction pointer & flags */
EIP,
EFLAGS,
/* segment registers */
CS,
SS,
DS,
ES,
FS,
GS,
/* floating point unit registers */
ST0,
ST1,
ST2,
ST3,
ST4,
ST5,
ST6,
ST7,
FCTRL,
FSTAT,
FTAG,
FISEG,
FIOFF,
FOSEG,
FOOFF,
FOP,
/* control registers */
CR0,
CR2,
CR3,
CR4,
/* debug registers */
DR0,
DR1,
DR2,
DR3,
DR6,
DR7,
/* descriptor tables */
IDTB,
IDTL,
IDTAR,
GDTB,
GDTL,
GDTAR,
TR,
LDTR,
LDTB,
LDTL,
LDTAR,
/* segment registers */
CSB,
CSL,
CSAR,
DSB,
DSL,
DSAR,
ESB,
ESL,
ESAR,
FSB,
FSL,
FSAR,
GSB,
GSL,
GSAR,
SSB,
SSL,
SSAR,
TSSB,
TSSL,
TSSAR,
/* PM control reg */
PMCR,
};
#define X86_32_COMMON_MAGIC 0x86328632
enum {
/* memory read/write */
MEMRDB32 = 0,
MEMRDB16,
MEMRDH32,
MEMRDH16,
MEMRDW32,
MEMRDW16,
MEMWRB32,
MEMWRB16,
MEMWRH32,
MEMWRH16,
MEMWRW32,
MEMWRW16,
/* IO read/write */
IORDB32,
IORDB16,
IORDH32,
IORDH16,
IORDW32,
IORDW16,
IOWRB32,
IOWRB16,
IOWRH32,
IOWRH16,
IOWRW32,
IOWRW16,
/* lakemont1 core shadow ram access opcodes */
SRAMACCESS,
SRAM2PDR,
PDR2SRAM,
WBINVD,
};
struct swbp_mem_patch {
uint8_t orig_byte;
uint32_t swbp_unique_id;
uint32_t physaddr;
struct swbp_mem_patch *next;
};
/* TODO - probemode specific - consider removing */
#define NUM_PM_REGS 18 /* regs used in save/restore */
struct x86_32_common {
uint32_t common_magic;
void *arch_info;
struct reg_cache *cache;
struct jtag_tap *curr_tap;
uint32_t stored_pc;
int flush;
/* pm_regs are for probemode save/restore state */
uint32_t pm_regs[NUM_PM_REGS];
/* working area for fastdata access */
struct working_area *fast_data_area;
int num_hw_bpoints;
struct x86_32_dbg_reg *hw_break_list;
struct swbp_mem_patch *swbbp_mem_patch_list;
/* core probemode implementation dependent functions */
uint8_t (*get_num_user_regs)(struct target *t);
bool (*is_paging_enabled)(struct target *t);
int (*disable_paging)(struct target *t);
int (*enable_paging)(struct target *t);
bool (*sw_bpts_supported)(struct target *t);
int (*transaction_status)(struct target *t);
int (*submit_instruction)(struct target *t, int num);
int (*read_hw_reg)(struct target *t, int reg, uint32_t *regval, uint8_t cache);
int (*write_hw_reg)(struct target *t, int reg,
uint32_t regval, uint8_t cache);
/* register cache to processor synchronization */
int (*read_hw_reg_to_cache)(struct target *target, int num);
int (*write_hw_reg_from_cache)(struct target *target, int num);
};
static inline struct x86_32_common *
target_to_x86_32(struct target *target)
{
return target->arch_info;
}
bool check_not_halted(const struct target *t);
/* breakpoint defines */
#define MAX_DEBUG_REGS 4
#define SW_BP_OPCODE 0xf1
#define MAX_SW_BPTS 20
struct x86_32_dbg_reg {
int used;
uint32_t bp_value;
};
#define DR7_G_ENABLE_SHIFT 1
#define DR7_ENABLE_SIZE 2 /* 2 bits per debug reg */
#define DR7_RW_SHIFT 16
#define DR7_LENGTH_SHIFT 18
#define DR7_RW_LEN_SIZE 4
#define DR7_BP_EXECUTE 0 /* 00 - only on instruction execution*/
#define DR7_BP_WRITE 1 /* 01 - only on data writes */
/*#define DR7_RW_IORW 2 UNSUPPORTED 10 - an I/O read and I/O write */
#define DR7_BP_READWRITE 3 /* on data read or data write */
#define DR7_BP_LENGTH_1 0 /* 00 - 1 byte length */
#define DR7_BP_LENGTH_2 1 /* 01 - 2 byte length */
#define DR7_BP_LENGTH_4 3 /* 11 - 4 byte length */
#define DR7_GLOBAL_ENABLE(val, regnum) \
(val |= (1 << (DR7_G_ENABLE_SHIFT + (DR7_ENABLE_SIZE * (regnum)))))
#define DR7_GLOBAL_DISABLE(val, regnum) \
(val &= ~(3 << (DR7_ENABLE_SIZE * (regnum))))
#define DR7_BP_FREE(val, regnum) \
((val & (3 << (DR7_ENABLE_SIZE * (regnum)))) == 0)
#define DR7_RESET_RWLEN_BITS(val, regnum) \
(val &= ~(0x0f << (DR7_RW_SHIFT + DR7_RW_LEN_SIZE * (regnum))))
#define DR7_SET_EXE(val, regnum) \
(val &= ~(0x0f << (DR7_RW_SHIFT + DR7_RW_LEN_SIZE * (regnum))))
#define DR7_SET_WRITE(val, regnum) \
(val |= (DR7_BP_WRITE << (DR7_RW_SHIFT + DR7_RW_LEN_SIZE * (regnum))))
#define DR7_SET_ACCESS(val, regnum) \
(val |= (DR7_BP_READWRITE << (DR7_RW_SHIFT + DR7_RW_LEN_SIZE * (regnum))))
#define DR7_SET_LENGTH(val, regnum, len) \
(val |= (len == 1) ? (DR7_BP_LENGTH_1 << (DR7_LENGTH_SHIFT + DR7_RW_LEN_SIZE * (regnum))) : \
(len == 2) ? (DR7_BP_LENGTH_2 << (DR7_LENGTH_SHIFT + DR7_RW_LEN_SIZE * (regnum))) : \
(DR7_BP_LENGTH_4 << (DR7_LENGTH_SHIFT + DR7_RW_LEN_SIZE * (regnum))))
/* public interface */
int x86_32_get_gdb_reg_list(struct target *t,
struct reg **reg_list[], int *reg_list_size,
enum target_register_class reg_class);
int x86_32_common_init_arch_info(struct target *target,
struct x86_32_common *x86_32);
int x86_32_common_mmu(struct target *t, int *enabled);
int x86_32_common_virt2phys(struct target *t, uint32_t address, uint32_t *physical);
int x86_32_common_read_phys_mem(struct target *t, uint32_t phys_address,
uint32_t size, uint32_t count, uint8_t *buffer);
int x86_32_common_write_phys_mem(struct target *t, uint32_t phys_address,
uint32_t size, uint32_t count, const uint8_t *buffer);
int x86_32_common_read_memory(struct target *t, uint32_t addr,
uint32_t size, uint32_t count, uint8_t *buf);
int x86_32_common_write_memory(struct target *t, uint32_t addr,
uint32_t size, uint32_t count, const uint8_t *buf);
int x86_32_common_read_io(struct target *t, uint32_t addr,
uint32_t size, uint8_t *buf);
int x86_32_common_write_io(struct target *t, uint32_t addr,
uint32_t size, const uint8_t *buf);
int x86_32_common_add_breakpoint(struct target *t, struct breakpoint *bp);
int x86_32_common_remove_breakpoint(struct target *t, struct breakpoint *bp);
int x86_32_common_add_watchpoint(struct target *t, struct watchpoint *wp);
int x86_32_common_remove_watchpoint(struct target *t, struct watchpoint *wp);
#endif /* X86_32_COMMON_H */

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@ -0,0 +1,9 @@
# There are many Quark boards that can host the quark_x10xx SoC
# Galileo is an example board
source [find target/quark_x10xx.cfg]
#default frequency but this can be adjusted at runtime
adapter_khz 4000
reset_config trst_only

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@ -0,0 +1,52 @@
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
set _CHIPNAME quark_x10xx
}
if { [info exists ENDIAN] } {
set _ENDIAN $ENDIAN
} else {
set _ENDIAN little
}
if { [info exists CPUTAPID] } {
set _CPUTAPID $CPUTAPID
} else {
set _CPUTAPID 0x18289013
}
jtag newtap quark_x10xx cpu -irlen 8 -irmask 0xff -expected-id $_CPUTAPID -disable
jtag newtap quark_x10xx cltap -irlen 8 -irmask 0xff -expected-id 0x0e681013 -enable
#openocd puts tap at front of chain not end of chain
proc quark_x10xx_tapenable {} {
echo "enabling core tap"
irscan quark_x10xx.cltap 0x11
drscan quark_x10xx.cltap 64 1
runtest 10
}
proc quark_x10xx_tapdisable {} {
echo "disabling core tap"
irscan quark_x10xx.cltap 0x11
drscan quark_x10xx.cltap 64 0
runtest 10
}
proc quark_x10xx_setup {} {
jtag tapenable quark_x10xx.cpu
}
jtag configure $_CHIPNAME.cpu -event tap-enable \
"quark_x10xx_tapenable"
jtag configure $_CHIPNAME.cpu -event tap-disable \
"quark_x10xx_tapdisable"
set _TARGETNAME $_CHIPNAME.cpu
target create quark_x10xx.cpu quark_x10xx -endian $_ENDIAN -chain-position quark_x10xx.cpu
jtag configure $_CHIPNAME.cpu -event setup \
"quark_x10xx_setup"