xilinx_bscan_spi: port to new migen and clean-up
* port to new migen * streamline package/part specification * add pullup (Series3, Series6) and pullnone (Series7) for unused pins as xilinx impact/vivado do it. * specify respective toolchains * build Series7 with vivado (broader support, faster) * point to prebuilt bitstreams at https://github.com/jordens/bscan_spi_bitstreams Change-Id: Ibfef3d78f855b754425f3e6131e2e49fa111e09a Signed-off-by: Robert Jordens <jordens@gmail.com> Reviewed-on: http://openocd.zylin.com/3173 Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Tested-by: jenkins Reviewed-by: Robert Jördens Reviewed-by: William D. Jones Reviewed-by: Tim "mithro" Ansell <mithro@mithis.com>gitignore-build
Robert Jordens
Paul Fertser
parent
400dbedaee
commit
12aee423db
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@ -13,20 +13,21 @@
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# GNU General Public License for more details.
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# GNU General Public License for more details.
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#
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#
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from migen.fhdl.std import *
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from migen import *
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from mibuild.generic_platform import *
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from migen.build.generic_platform import *
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from mibuild.xilinx import XilinxPlatform
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from migen.build import xilinx
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from mibuild.xilinx.vivado import XilinxVivadoToolchain
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from mibuild.xilinx.ise import XilinxISEToolchain
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"""
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"""
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This migen script produces proxy bitstreams to allow programming SPI flashes
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This migen script produces proxy bitstreams to allow programming SPI flashes
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behind FPGAs. JTAG signalling is connected directly to SPI signalling. CS_N is
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behind FPGAs.
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asserted when the JTAG IR contains the USER1 instruction and the state is
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SHIFT-DR.
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Xilinx bscan cells sample TDO on falling TCK and forward it.
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Bitstream binaries built with this script are available at:
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https://github.com/jordens/bscan_spi_bitstreams
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JTAG signalling is connected directly to SPI signalling. CS_N is
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asserted when the JTAG IR contains the USER1 instruction and the state is
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SHIFT-DR. Xilinx bscan cells sample TDO on falling TCK and forward it.
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MISO requires sampling on rising CLK and leads to one cycle of latency.
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MISO requires sampling on rising CLK and leads to one cycle of latency.
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https://github.com/m-labs/migen
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https://github.com/m-labs/migen
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@ -35,8 +36,10 @@ https://github.com/m-labs/migen
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class Spartan3(Module):
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class Spartan3(Module):
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macro = "BSCAN_SPARTAN3"
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macro = "BSCAN_SPARTAN3"
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toolchain = "ise"
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def __init__(self, platform):
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def __init__(self, platform):
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platform.toolchain.bitgen_opt += " -g compress -g UnusedPin:Pullup"
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self.clock_domains.cd_jtag = ClockDomain(reset_less=True)
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self.clock_domains.cd_jtag = ClockDomain(reset_less=True)
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spi = platform.request("spiflash")
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spi = platform.request("spiflash")
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shift = Signal()
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shift = Signal()
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@ -58,7 +61,10 @@ class Spartan3A(Spartan3):
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class Spartan6(Module):
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class Spartan6(Module):
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toolchain = "ise"
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def __init__(self, platform):
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def __init__(self, platform):
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platform.toolchain.bitgen_opt += " -g compress -g UnusedPin:Pullup"
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self.clock_domains.cd_jtag = ClockDomain(reset_less=True)
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self.clock_domains.cd_jtag = ClockDomain(reset_less=True)
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spi = platform.request("spiflash")
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spi = platform.request("spiflash")
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shift = Signal()
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shift = Signal()
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@ -72,7 +78,13 @@ class Spartan6(Module):
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class Series7(Module):
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class Series7(Module):
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toolchain = "vivado"
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def __init__(self, platform):
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def __init__(self, platform):
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platform.toolchain.bitstream_commands.extend([
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"set_property BITSTREAM.GENERAL.COMPRESS True [current_design]",
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"set_property BITSTREAM.CONFIG.UNUSEDPIN Pullnone [current_design]",
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])
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self.clock_domains.cd_jtag = ClockDomain(reset_less=True)
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self.clock_domains.cd_jtag = ClockDomain(reset_less=True)
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spi = platform.request("spiflash")
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spi = platform.request("spiflash")
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clk = Signal()
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clk = Signal()
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@ -89,184 +101,105 @@ class Series7(Module):
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i_USRCCLKTS=0, i_USRDONEO=1, i_USRDONETS=1)
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i_USRCCLKTS=0, i_USRDONEO=1, i_USRDONETS=1)
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class XilinxBscanSpi(XilinxPlatform):
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class XilinxBscanSpi(xilinx.XilinxPlatform):
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packages = {
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# (package-speedgrade, id): [cs_n, clk, mosi, miso, *pullups]
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("cp132", 1): ["M2", "N12", "N2", "N8"],
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("fg320", 1): ["U3", "U16", "T4", "N10"],
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("fg320", 2): ["V3", "U16", "T11", "V16"],
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("fg484", 1): ["Y4", "AA20", "AB14", "AB20"],
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("fgg484", 1): ["Y4", "AA20", "AB14", "AB20"],
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("fgg400", 1): ["Y2", "Y19", "W12", "W18"],
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("ftg256", 1): ["T2", "R14", "P10", "T14"],
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("ft256", 1): ["T2", "R14", "P10", "T14"],
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("fg400", 1): ["Y2", "Y19", "W12", "W18"],
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("cs484", 1): ["U7", "V17", "V13", "W17"],
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("qg144-2", 1): ["P38", "P70", "P64", "P65", "P62", "P61"],
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("cpg196-2", 1): ["P2", "N13", "P11", "N11", "N10", "P10"],
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("cpg236-1", 1): ["K19", None, "D18", "D19", "G18", "F18"],
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("csg484-2", 1): ["AB5", "W17", "AB17", "Y17", "V13", "W13"],
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("csg324-2", 1): ["V3", "R15", "T13", "R13", "T14", "V14"],
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("csg324-1", 1): ["L13", None, "K17", "K18", "L14", "M14"],
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("fbg484-1", 1): ["T19", None, "P22", "R22", "P21", "R21"],
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("fbg484-1", 2): ["L16", None, "H18", "H19", "G18", "F19"],
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("fbg676-1", 1): ["C23", None, "B24", "A25", "B22", "A22"],
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("ffg901-1", 1): ["V26", None, "R30", "T30", "R28", "T28"],
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("ffg1156-1", 1): ["V30", None, "AA33", "AA34", "Y33", "Y34"],
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("ffg1157-1", 1): ["AL33", None, "AN33", "AN34", "AK34", "AL34"],
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("ffg1158-1", 1): ["C24", None, "A23", "A24", "B26", "A26"],
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("ffg1926-1", 1): ["AK33", None, "AN34", "AN35", "AJ34", "AK34"],
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("fhg1761-1", 1): ["AL36", None, "AM36", "AN36", "AJ36", "AJ37"],
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("flg1155-1", 1): ["AL28", None, "AE28", "AF28", "AJ29", "AJ30"],
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("flg1932-1", 1): ["V32", None, "T33", "R33", "U31", "T31"],
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("flg1926-1", 1): ["AK33", None, "AN34", "AN35", "AJ34", "AK34"],
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}
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pinouts = {
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pinouts = {
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# bitstreams are named by die, package does not matter, speed grade
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# bitstreams are named by die, package does not matter, speed grade
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# should not matter.
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# should not matter.
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# cs_n, clk, mosi, miso, *pullups
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#
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"xc3s100e": ("cp132",
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# chip: (package, id, standard, class)
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["M2", "N12", "N2", "N8"],
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"xc3s100e": ("cp132", 1, "LVCMOS33", Spartan3),
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"LVCMOS33", Spartan3),
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"xc3s1200e": ("fg320", 1, "LVCMOS33", Spartan3),
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"xc3s1200e": ("fg320",
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"xc3s1400a": ("fg484", 1, "LVCMOS33", Spartan3A),
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["U3", "U16", "T4", "N10"],
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"xc3s1400an": ("fgg484", 1, "LVCMOS33", Spartan3A),
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"LVCMOS33", Spartan3),
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"xc3s1600e": ("fg320", 1, "LVCMOS33", Spartan3),
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"xc3s1400a": ("fg484",
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"xc3s200a": ("fg320", 2, "LVCMOS33", Spartan3A),
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["Y4", "AA20", "AB14", "AB20"],
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"xc3s200an": ("ftg256", 1, "LVCMOS33", Spartan3A),
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"LVCMOS33", Spartan3A),
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"xc3s250e": ("cp132", 1, "LVCMOS33", Spartan3),
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"xc3s1400an": ("fgg484",
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"xc3s400a": ("fg320", 2, "LVCMOS33", Spartan3A),
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["Y4", "AA20", "AB14", "AB20"],
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"xc3s400an": ("fgg400", 1, "LVCMOS33", Spartan3A),
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"LVCMOS33", Spartan3A),
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"xc3s500e": ("cp132", 1, "LVCMOS33", Spartan3),
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"xc3s1600e": ("fg320",
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"xc3s50a": ("ft256", 1, "LVCMOS33", Spartan3A),
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["U3", "U16", "T4", "N10"],
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"xc3s50an": ("ftg256", 1, "LVCMOS33", Spartan3A),
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"LVCMOS33", Spartan3),
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"xc3s700a": ("fg400", 1, "LVCMOS33", Spartan3A),
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"xc3s200a": ("fg320",
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"xc3s700an": ("fgg484", 1, "LVCMOS33", Spartan3A),
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["V3", "U16", "T11", "V16"],
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"xc3sd1800a": ("cs484", 1, "LVCMOS33", Spartan3A),
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"LVCMOS33", Spartan3A),
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"xc3sd3400a": ("cs484", 1, "LVCMOS33", Spartan3A),
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"xc3s200an": ("ftg256",
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["T2", "R14", "P10", "T14"],
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"LVCMOS33", Spartan3A),
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"xc3s250e": ("cp132",
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["M2", "N12", "N2", "N8"],
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"LVCMOS33", Spartan3),
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"xc3s400a": ("fg320",
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["V3", "U16", "T11", "V16"],
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"LVCMOS33", Spartan3A),
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"xc3s400an": ("fgg400",
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["Y2", "Y19", "W12", "W18"],
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"LVCMOS33", Spartan3A),
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"xc3s500e": ("cp132",
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["M2", "N12", "N2", "N8"],
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"LVCMOS33", Spartan3),
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"xc3s50a": ("ft256",
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["T2", "R14", "P10", "T14"],
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"LVCMOS33", Spartan3A),
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"xc3s50an": ("ftg256",
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["T2", "R14", "P10", "T14"],
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"LVCMOS33", Spartan3A),
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"xc3s700a": ("fg400",
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["Y2", "Y19", "W12", "W18"],
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"LVCMOS33", Spartan3A),
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"xc3s700an": ("fgg484",
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["Y4", "AA20", "AB14", "AB20"],
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"LVCMOS33", Spartan3A),
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"xc3sd1800a": ("cs484",
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["U7", "V17", "V13", "W17"],
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"LVCMOS33", Spartan3A),
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"xc3sd3400a": ("cs484",
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["U7", "V17", "V13", "W17"],
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"LVCMOS33", Spartan3A),
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"xc6slx100": ("csg484-2",
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"xc6slx100": ("csg484-2", 1, "LVCMOS33", Spartan6),
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["AB5", "W17", "AB17", "Y17", "V13", "W13"],
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"xc6slx100t": ("csg484-2", 1, "LVCMOS33", Spartan6),
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"LVCMOS33", Spartan6),
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"xc6slx150": ("csg484-2", 1, "LVCMOS33", Spartan6),
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"xc6slx100t": ("csg484-2",
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"xc6slx150t": ("csg484-2", 1, "LVCMOS33", Spartan6),
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["AB5", "W17", "AB17", "Y17", "V13", "W13"],
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"xc6slx16": ("cpg196-2", 1, "LVCMOS33", Spartan6),
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"LVCMOS33", Spartan6),
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"xc6slx25": ("csg324-2", 1, "LVCMOS33", Spartan6),
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"xc6slx150": ("csg484-2",
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"xc6slx25t": ("csg324-2", 1, "LVCMOS33", Spartan6),
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["AB5", "W17", "AB17", "Y17", "V13", "W13"],
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"xc6slx45": ("csg324-2", 1, "LVCMOS33", Spartan6),
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"LVCMOS33", Spartan6),
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"xc6slx45t": ("csg324-2", 1, "LVCMOS33", Spartan6),
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"xc6slx150t": ("csg484-2",
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"xc6slx4": ("cpg196-2", 1, "LVCMOS33", Spartan6),
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["AB5", "W17", "AB17", "Y17", "V13", "W13"],
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"xc6slx4t": ("qg144-2", 1, "LVCMOS33", Spartan6),
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"LVCMOS33", Spartan6),
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"xc6slx75": ("csg484-2", 1, "LVCMOS33", Spartan6),
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"xc6slx16": ("cpg196-2",
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"xc6slx75t": ("csg484-2", 1, "LVCMOS33", Spartan6),
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["P2", "N13", "P11", "N11", "N10", "P10"],
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"xc6slx9": ("cpg196-2", 1, "LVCMOS33", Spartan6),
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"LVCMOS33", Spartan6),
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"xc6slx9t": ("qg144-2", 1, "LVCMOS33", Spartan6),
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"xc6slx25": ("csg324-2",
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["V3", "R15", "T13", "R13", "T14", "V14"],
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"LVCMOS33", Spartan6),
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"xc6slx25t": ("csg324-2",
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["V3", "R15", "T13", "R13", "T14", "V14"],
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"LVCMOS33", Spartan6),
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"xc6slx45": ("csg324-2",
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["V3", "R15", "T13", "R13", "T14", "V14"],
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"LVCMOS33", Spartan6),
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"xc6slx45t": ("csg324-2",
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["V3", "R15", "T13", "R13", "T14", "V14"],
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"LVCMOS33", Spartan6),
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"xc6slx4": ("cpg196-2",
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["P2", "N13", "P11", "N11", "N10", "P10"],
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"LVCMOS33", Spartan6),
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"xc6slx4t": ("qg144-2",
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["P38", "P70", "P64", "P65", "P62", "P61"],
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"LVCMOS33", Spartan6),
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"xc6slx75": ("csg484-2",
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["AB5", "W17", "AB17", "Y17", "V13", "W13"],
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"LVCMOS33", Spartan6),
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"xc6slx75t": ("csg484-2",
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["AB5", "W17", "AB17", "Y17", "V13", "W13"],
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"LVCMOS33", Spartan6),
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"xc6slx9": ("cpg196-2",
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["P2", "N13", "P11", "N11", "N10", "P10"],
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"LVCMOS33", Spartan6),
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"xc6slx9t": ("qg144-2",
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["P38", "P70", "P64", "P65", "P62", "P61"],
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"LVCMOS33", Spartan6),
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"xc7a100t": ("csg324-1",
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"xc7a100t": ("csg324-1", 1, "LVCMOS25", Series7),
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["L13", None, "K17", "K18", "L14", "M14"],
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"xc7a15t": ("cpg236-1", 1, "LVCMOS25", Series7),
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"LVCMOS25", Series7),
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"xc7a200t": ("fbg484-1", 1, "LVCMOS25", Series7),
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"xc7a15t": ("cpg236-1",
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"xc7a35t": ("cpg236-1", 1, "LVCMOS25", Series7),
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["K19", None, "D18", "D19", "G18", "F18"],
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"xc7a50t": ("cpg236-1", 1, "LVCMOS25", Series7),
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"LVCMOS25", Series7),
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"xc7a75t": ("csg324-1", 1, "LVCMOS25", Series7),
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"xc7a200t": ("fbg484-1",
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"xc7k160t": ("fbg484-1", 2, "LVCMOS25", Series7),
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["T19", None, "P22", "R22", "P21", "R21"],
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"xc7k325t": ("fbg676-1", 1, "LVCMOS25", Series7),
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"LVCMOS25", Series7),
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"xc7k355t": ("ffg901-1", 1, "LVCMOS25", Series7),
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"xc7a35t": ("cpg236-1",
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"xc7k410t": ("fbg676-1", 1, "LVCMOS25", Series7),
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["K19", None, "D18", "D19", "G18", "F18"],
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"xc7k420t": ("ffg1156-1", 1, "LVCMOS25", Series7),
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"LVCMOS25", Series7),
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"xc7k480t": ("ffg1156-1", 1, "LVCMOS25", Series7),
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"xc7a50t": ("cpg236-1",
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"xc7k70t": ("fbg484-1", 2, "LVCMOS25", Series7),
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["K19", None, "D18", "D19", "G18", "F18"],
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"xc7v2000t": ("fhg1761-1", 1, "LVCMOS18", Series7),
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"LVCMOS25", Series7),
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"xc7v585t": ("ffg1157-1", 1, "LVCMOS18", Series7),
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"xc7a75t": ("csg324-1",
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"xc7vh580t": ("flg1155-1", 1, "LVCMOS18", Series7),
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["L13", None, "K17", "K18", "L14", "M14"],
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"xc7vh870t": ("flg1932-1", 1, "LVCMOS18", Series7),
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"LVCMOS25", Series7),
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"xc7vx1140t": ("flg1926-1", 1, "LVCMOS18", Series7),
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"xc7k160t": ("fbg484-1",
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"xc7vx330t": ("ffg1157-1", 1, "LVCMOS18", Series7),
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["L16", None, "H18", "H19", "G18", "F19"],
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"xc7vx415t": ("ffg1157-1", 1, "LVCMOS18", Series7),
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"LVCMOS25", Series7),
|
"xc7vx485t": ("ffg1157-1", 1, "LVCMOS18", Series7),
|
||||||
"xc7k325t": ("fbg676-1",
|
"xc7vx550t": ("ffg1158-1", 1, "LVCMOS18", Series7),
|
||||||
["C23", None, "B24", "A25", "B22", "A22"],
|
"xc7vx690t": ("ffg1157-1", 1, "LVCMOS18", Series7),
|
||||||
"LVCMOS25", Series7),
|
"xc7vx980t": ("ffg1926-1", 1, "LVCMOS18", Series7),
|
||||||
"xc7k355t": ("ffg901-1",
|
|
||||||
["V26", None, "R30", "T30", "R28", "T28"],
|
|
||||||
"LVCMOS25", Series7),
|
|
||||||
"xc7k410t": ("fbg676-1",
|
|
||||||
["C23", None, "B24", "A25", "B22", "A22"],
|
|
||||||
"LVCMOS25", Series7),
|
|
||||||
"xc7k420t": ("ffg1156-1",
|
|
||||||
["V30", None, "AA33", "AA34", "Y33", "Y34"],
|
|
||||||
"LVCMOS25", Series7),
|
|
||||||
"xc7k480t": ("ffg1156-1",
|
|
||||||
["V30", None, "AA33", "AA34", "Y33", "Y34"],
|
|
||||||
"LVCMOS25", Series7),
|
|
||||||
"xc7k70t": ("fbg484-1",
|
|
||||||
["L16", None, "H18", "H19", "G18", "F19"],
|
|
||||||
"LVCMOS25", Series7),
|
|
||||||
"xc7v2000t": ("fhg1761-1",
|
|
||||||
["AL36", None, "AM36", "AN36", "AJ36", "AJ37"],
|
|
||||||
"LVCMOS18", Series7),
|
|
||||||
"xc7v585t": ("ffg1157-1",
|
|
||||||
["AL33", None, "AN33", "AN34", "AK34", "AL34"],
|
|
||||||
"LVCMOS18", Series7),
|
|
||||||
"xc7vh580t": ("flg1155-1",
|
|
||||||
["AL28", None, "AE28", "AF28", "AJ29", "AJ30"],
|
|
||||||
"LVCMOS18", Series7),
|
|
||||||
"xc7vh870t": ("flg1932-1",
|
|
||||||
["V32", None, "T33", "R33", "U31", "T31"],
|
|
||||||
"LVCMOS18", Series7),
|
|
||||||
"xc7vx1140t": ("flg1926-1",
|
|
||||||
["AK33", None, "AN34", "AN35", "AJ34", "AK34"],
|
|
||||||
"LVCMOS18", Series7),
|
|
||||||
"xc7vx330t": ("ffg1157-1",
|
|
||||||
["AL33", None, "AN33", "AN34", "AK34", "AL34"],
|
|
||||||
"LVCMOS18", Series7),
|
|
||||||
"xc7vx415t": ("ffg1157-1",
|
|
||||||
["AL33", None, "AN33", "AN34", "AK34", "AL34"],
|
|
||||||
"LVCMOS18", Series7),
|
|
||||||
"xc7vx485t": ("ffg1157-1",
|
|
||||||
["AL33", None, "AN33", "AN34", "AK34", "AL34"],
|
|
||||||
"LVCMOS18", Series7),
|
|
||||||
"xc7vx550t": ("ffg1158-1",
|
|
||||||
["C24", None, "A23", "A24", "B26", "A26"],
|
|
||||||
"LVCMOS18", Series7),
|
|
||||||
"xc7vx690t": ("ffg1157-1",
|
|
||||||
["AL33", None, "AN33", "AN34", "AK34", "AL34"],
|
|
||||||
"LVCMOS18", Series7),
|
|
||||||
"xc7vx980t": ("ffg1926-1",
|
|
||||||
["AK33", None, "AN34", "AN35", "AJ34", "AK34"],
|
|
||||||
"LVCMOS18", Series7),
|
|
||||||
}
|
}
|
||||||
|
|
||||||
def __init__(self, device, pins, std):
|
def __init__(self, device, pins, std, toolchain="ise"):
|
||||||
cs_n, clk, mosi, miso = pins[:4]
|
cs_n, clk, mosi, miso = pins[:4]
|
||||||
io = ["spiflash", 0,
|
io = ["spiflash", 0,
|
||||||
Subsignal("cs_n", Pins(cs_n)),
|
Subsignal("cs_n", Pins(cs_n)),
|
||||||
|
|
@ -278,26 +211,21 @@ class XilinxBscanSpi(XilinxPlatform):
|
||||||
io.append(Subsignal("clk", Pins(clk)))
|
io.append(Subsignal("clk", Pins(clk)))
|
||||||
for i, p in enumerate(pins[4:]):
|
for i, p in enumerate(pins[4:]):
|
||||||
io.append(Subsignal("pullup{}".format(i), Pins(p), Misc("PULLUP")))
|
io.append(Subsignal("pullup{}".format(i), Pins(p), Misc("PULLUP")))
|
||||||
|
xilinx.XilinxPlatform.__init__(self, device, [io], toolchain=toolchain)
|
||||||
XilinxPlatform.__init__(self, device, [io])
|
|
||||||
if isinstance(self.toolchain, XilinxVivadoToolchain):
|
|
||||||
self.toolchain.bitstream_commands.append(
|
|
||||||
"set_property BITSTREAM.GENERAL.COMPRESS True [current_design]"
|
|
||||||
)
|
|
||||||
elif isinstance(self.toolchain, XilinxISEToolchain):
|
|
||||||
self.toolchain.bitgen_opt += " -g compress"
|
|
||||||
|
|
||||||
@classmethod
|
@classmethod
|
||||||
def make(cls, device, errors=False):
|
def make(cls, device, errors=False):
|
||||||
pkg, pins, std, Top = cls.pinouts[device]
|
pkg, id, std, Top = cls.pinouts[device]
|
||||||
platform = cls("{}-{}".format(device, pkg), pins, std)
|
pins = cls.packages[(pkg, id)]
|
||||||
|
platform = cls("{}-{}".format(device, pkg), pins, std, Top.toolchain)
|
||||||
top = Top(platform)
|
top = Top(platform)
|
||||||
name = "bscan_spi_{}".format(device)
|
name = "bscan_spi_{}".format(device)
|
||||||
dir = "build_{}".format(device)
|
dir = "build_{}".format(device)
|
||||||
try:
|
try:
|
||||||
platform.build(top, build_name=name, build_dir=dir)
|
platform.build(top, build_name=name, build_dir=dir)
|
||||||
except Exception as e:
|
except Exception as e:
|
||||||
print("ERROR: build failed for {}: {}".format(device, e))
|
print(("ERROR: xilinx_bscan_spi build failed "
|
||||||
|
"for {}: {}").format(device, e))
|
||||||
if errors:
|
if errors:
|
||||||
raise
|
raise
|
||||||
|
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue