diff --git a/src/target/arm_adi_v5.c b/src/target/arm_adi_v5.c
index 50d3b2677..8ab873bbc 100644
--- a/src/target/arm_adi_v5.c
+++ b/src/target/arm_adi_v5.c
@@ -965,18 +965,30 @@ static const struct {
 	{ ARM_ID, 0x000, "Cortex-M3 SCS",    "(System Control Space)", },
 	{ ARM_ID, 0x001, "Cortex-M3 ITM",    "(Instrumentation Trace Module)", },
 	{ ARM_ID, 0x002, "Cortex-M3 DWT",    "(Data Watchpoint and Trace)", },
-	{ ARM_ID, 0x003, "Cortex-M3 FBP",    "(Flash Patch and Breakpoint)", },
+	{ ARM_ID, 0x003, "Cortex-M3 FPB",    "(Flash Patch and Breakpoint)", },
 	{ ARM_ID, 0x008, "Cortex-M0 SCS",    "(System Control Space)", },
 	{ ARM_ID, 0x00a, "Cortex-M0 DWT",    "(Data Watchpoint and Trace)", },
 	{ ARM_ID, 0x00b, "Cortex-M0 BPU",    "(Breakpoint Unit)", },
 	{ ARM_ID, 0x00c, "Cortex-M4 SCS",    "(System Control Space)", },
 	{ ARM_ID, 0x00d, "CoreSight ETM11",  "(Embedded Trace)", },
+	{ ARM_ID, 0x00e, "Cortex-M7 FPB",    "(Flash Patch and Breakpoint)", },
 	{ ARM_ID, 0x490, "Cortex-A15 GIC",   "(Generic Interrupt Controller)", },
+	{ ARM_ID, 0x4a1, "Cortex-A53 ROM",   "(v8 Memory Map ROM Table)", },
+	{ ARM_ID, 0x4a2, "Cortex-A57 ROM",   "(ROM Table)", },
+	{ ARM_ID, 0x4a3, "Cortex-A53 ROM",   "(v7 Memory Map ROM Table)", },
+	{ ARM_ID, 0x4a4, "Cortex-A72 ROM",   "(ROM Table)", },
+	{ ARM_ID, 0x4af, "Cortex-A15 ROM",   "(ROM Table)", },
 	{ ARM_ID, 0x4c0, "Cortex-M0+ ROM",   "(ROM Table)", },
-	{ ARM_ID, 0x4c7, "Cortex-M7 PPB",    "(Private Peripheral Bus ROM Table)", },
+	{ ARM_ID, 0x4c3, "Cortex-M3 ROM",    "(ROM Table)", },
+	{ ARM_ID, 0x4c4, "Cortex-M4 ROM",    "(ROM Table)", },
+	{ ARM_ID, 0x4c7, "Cortex-M7 PPB ROM", "(Private Peripheral Bus ROM Table)", },
+	{ ARM_ID, 0x4c8, "Cortex-M7 ROM",    "(ROM Table)", },
+	{ ARM_ID, 0x470, "Cortex-M1 ROM",    "(ROM Table)", },
+	{ ARM_ID, 0x471, "Cortex-M0 ROM",    "(ROM Table)", },
 	{ ARM_ID, 0x906, "CoreSight CTI",    "(Cross Trigger)", },
 	{ ARM_ID, 0x907, "CoreSight ETB",    "(Trace Buffer)", },
 	{ ARM_ID, 0x908, "CoreSight CSTF",   "(Trace Funnel)", },
+	{ ARM_ID, 0x909, "CoreSight ATBR",   "(Advanced Trace Bus Replicator)", },
 	{ ARM_ID, 0x910, "CoreSight ETM9",   "(Embedded Trace)", },
 	{ ARM_ID, 0x912, "CoreSight TPIU",   "(Trace Port Interface Unit)", },
 	{ ARM_ID, 0x913, "CoreSight ITM",    "(Instrumentation Trace Macrocell)", },
@@ -1001,11 +1013,14 @@ static const struct {
 	{ ARM_ID, 0x95f, "Cortex-A15 PTM",   "(Program Trace Macrocell)", },
 	{ ARM_ID, 0x961, "CoreSight TMC",    "(Trace Memory Controller)", },
 	{ ARM_ID, 0x962, "CoreSight STM",    "(System Trace Macrocell)", },
+	{ ARM_ID, 0x975, "Cortex-M7 ETM",    "(Embedded Trace)", },
 	{ ARM_ID, 0x9a0, "CoreSight PMU",    "(Performance Monitoring Unit)", },
 	{ ARM_ID, 0x9a1, "Cortex-M4 TPIU",   "(Trace Port Interface Unit)", },
+	{ ARM_ID, 0x9a4, "CoreSight GPR",    "(Granular Power Requester)", },
 	{ ARM_ID, 0x9a5, "Cortex-A5 PMU",    "(Performance Monitor Unit)", },
 	{ ARM_ID, 0x9a7, "Cortex-A7 PMU",    "(Performance Monitor Unit)", },
 	{ ARM_ID, 0x9a8, "Cortex-A53 CTI",    "(Cross Trigger)", },
+	{ ARM_ID, 0x9a9, "Cortex-M7 TPIU",   "(Trace Port Interface Unit)", },
 	{ ARM_ID, 0x9ae, "Cortex-A17 PMU",    "(Performance Monitor Unit)", },
 	{ ARM_ID, 0x9af, "Cortex-A15 PMU",   "(Performance Monitor Unit)", },
 	{ ARM_ID, 0x9b7, "Cortex-R7 PMU",    "(Performance Monitoring Unit)", },