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Fix m*deleg logic. 

Change-Id: Ieda035280334f8e7dc78c9fbc2bdbea7c565d2de
riscv-compliance-dev
Tim Newsome 2018-03-26 16:00:34 -07:00
parent b6dca68b2e
commit 0c05aafbf8
1 changed files with 1 additions and 2 deletions
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3
src/target/riscv/riscv.c
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@ -2328,8 +2328,7 @@ int riscv_init_registers(struct target *target)
/* "In systems with only M-mode, or with both M-mode and /* "In systems with only M-mode, or with both M-mode and
* U-mode but without U-mode trap support, the medeleg and * U-mode but without U-mode trap support, the medeleg and
* mideleg registers should not exist." */ * mideleg registers should not exist." */
r->exist = (riscv_supports_extension(target, 'S') || r->exist = riscv_supports_extension(target, 'S') ||
riscv_supports_extension(target, 'U')) &&
!riscv_supports_extension(target, 'N'); !riscv_supports_extension(target, 'N');
break; break;
} }