From 0c05aafbf83cf38167aae83c6622d3ecb4b80f44 Mon Sep 17 00:00:00 2001 From: Tim Newsome Date: Mon, 26 Mar 2018 16:00:34 -0700 Subject: [PATCH] Fix m*deleg logic. Change-Id: Ieda035280334f8e7dc78c9fbc2bdbea7c565d2de --- src/target/riscv/riscv.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/src/target/riscv/riscv.c b/src/target/riscv/riscv.c index 073a355e1..89c0dc7e0 100644 --- a/src/target/riscv/riscv.c +++ b/src/target/riscv/riscv.c @@ -2328,8 +2328,7 @@ int riscv_init_registers(struct target *target) /* "In systems with only M-mode, or with both M-mode and * U-mode but without U-mode trap support, the medeleg and * mideleg registers should not exist." */ - r->exist = (riscv_supports_extension(target, 'S') || - riscv_supports_extension(target, 'U')) && + r->exist = riscv_supports_extension(target, 'S') || !riscv_supports_extension(target, 'N'); break; }