diff --git a/src/target/riscv/riscv.c b/src/target/riscv/riscv.c
index 073a355e1..89c0dc7e0 100644
--- a/src/target/riscv/riscv.c
+++ b/src/target/riscv/riscv.c
@@ -2328,8 +2328,7 @@ int riscv_init_registers(struct target *target)
 					/* "In systems with only M-mode, or with both M-mode and
 					 * U-mode but without U-mode trap support, the medeleg and
 					 * mideleg registers should not exist." */
-					r->exist = (riscv_supports_extension(target, 'S') ||
-							riscv_supports_extension(target, 'U')) &&
+					r->exist = riscv_supports_extension(target, 'S') ||
 						!riscv_supports_extension(target, 'N');
 					break;
 			}