The following patches was applied:
- openocd-flash-static-keyword-v3.patch - openocd-lpc2000-fix-erase-obo.patch - openocd-jlink-fix-sign-ptr-warn.patch - openocd-wextra-etm.patch - openocd-wextra-jtag.patch - openocd-add-new-tap-symbols-v6.patch Many thanks to Zach Welch <zw(at)superlucidity.net> git-svn-id: svn://svn.berlios.de/openocd/trunk@1462 b42882b7-edfa-0310-969c-e2dbd0fdcd60__archive__
mifi
parent
13de2d2fef
commit
0bba832713
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@ -36,19 +36,19 @@
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#include <string.h>
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#include <string.h>
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#include <unistd.h>
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#include <unistd.h>
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int aduc702x_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank);
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static int aduc702x_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank);
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int aduc702x_register_commands(struct command_context_s *cmd_ctx);
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static int aduc702x_register_commands(struct command_context_s *cmd_ctx);
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int aduc702x_erase(struct flash_bank_s *bank, int first, int last);
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static int aduc702x_erase(struct flash_bank_s *bank, int first, int last);
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int aduc702x_protect(struct flash_bank_s *bank, int set, int first, int last);
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static int aduc702x_protect(struct flash_bank_s *bank, int set, int first, int last);
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int aduc702x_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count);
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static int aduc702x_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count);
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int aduc702x_write_single(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count);
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static int aduc702x_write_single(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count);
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int aduc702x_write_block(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count);
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static int aduc702x_write_block(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count);
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int aduc702x_probe(struct flash_bank_s *bank);
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static int aduc702x_probe(struct flash_bank_s *bank);
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int aduc702x_info(struct flash_bank_s *bank, char *buf, int buf_size);
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static int aduc702x_info(struct flash_bank_s *bank, char *buf, int buf_size);
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int aduc702x_protect_check(struct flash_bank_s *bank);
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static int aduc702x_protect_check(struct flash_bank_s *bank);
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int aduc702x_build_sector_list(struct flash_bank_s *bank);
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static int aduc702x_build_sector_list(struct flash_bank_s *bank);
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int aduc702x_check_flash_completion(target_t* target, unsigned int timeout_ms);
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static int aduc702x_check_flash_completion(target_t* target, unsigned int timeout_ms);
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int aduc702x_set_write_enable(target_t *target, int enable);
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static int aduc702x_set_write_enable(target_t *target, int enable);
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#define ADUC702x_FLASH 0xfffff800
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#define ADUC702x_FLASH 0xfffff800
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#define ADUC702x_FLASH_FEESTA (0*4)
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#define ADUC702x_FLASH_FEESTA (0*4)
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@ -91,14 +91,14 @@ flash_driver_t aduc702x_flash =
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.info = aduc702x_info
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.info = aduc702x_info
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};
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};
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int aduc702x_register_commands(struct command_context_s *cmd_ctx)
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static int aduc702x_register_commands(struct command_context_s *cmd_ctx)
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{
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{
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return ERROR_OK;
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return ERROR_OK;
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}
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}
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/* flash bank aduc702x 0 0 0 0 <target#>
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/* flash bank aduc702x 0 0 0 0 <target#>
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* The ADC7019-28 devices all have the same flash layout */
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* The ADC7019-28 devices all have the same flash layout */
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int aduc702x_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank)
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static int aduc702x_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank)
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{
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{
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aduc702x_flash_bank_t *nbank;
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aduc702x_flash_bank_t *nbank;
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@ -113,7 +113,7 @@ int aduc702x_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, ch
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return ERROR_OK;
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return ERROR_OK;
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}
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}
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int aduc702x_build_sector_list(struct flash_bank_s *bank)
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static int aduc702x_build_sector_list(struct flash_bank_s *bank)
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{
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{
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//aduc7026_flash_bank_t *aduc7026_info = bank->driver_priv;
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//aduc7026_flash_bank_t *aduc7026_info = bank->driver_priv;
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@ -135,13 +135,13 @@ int aduc702x_build_sector_list(struct flash_bank_s *bank)
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return ERROR_OK;
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return ERROR_OK;
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}
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}
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int aduc702x_protect_check(struct flash_bank_s *bank)
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static int aduc702x_protect_check(struct flash_bank_s *bank)
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{
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{
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printf("aduc702x_protect_check not implemented yet.\n");
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printf("aduc702x_protect_check not implemented yet.\n");
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return ERROR_OK;
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return ERROR_OK;
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}
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}
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int aduc702x_erase(struct flash_bank_s *bank, int first, int last)
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static int aduc702x_erase(struct flash_bank_s *bank, int first, int last)
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{
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{
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//int res;
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//int res;
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int x;
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int x;
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@ -194,13 +194,13 @@ int aduc702x_erase(struct flash_bank_s *bank, int first, int last)
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return ERROR_OK;
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return ERROR_OK;
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}
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}
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int aduc702x_protect(struct flash_bank_s *bank, int set, int first, int last)
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static int aduc702x_protect(struct flash_bank_s *bank, int set, int first, int last)
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{
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{
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printf("aduc702x_protect not implemented yet.\n");
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printf("aduc702x_protect not implemented yet.\n");
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return ERROR_FLASH_OPERATION_FAILED;
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return ERROR_FLASH_OPERATION_FAILED;
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}
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}
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int aduc702x_write_block(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
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static int aduc702x_write_block(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
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{
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{
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aduc702x_flash_bank_t *aduc702x_info = bank->driver_priv;
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aduc702x_flash_bank_t *aduc702x_info = bank->driver_priv;
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target_t *target = bank->target;
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target_t *target = bank->target;
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@ -329,7 +329,7 @@ int aduc702x_write_block(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32
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/* All-JTAG, single-access method. Very slow. Used only if there is no
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/* All-JTAG, single-access method. Very slow. Used only if there is no
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* working area available. */
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* working area available. */
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int aduc702x_write_single(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
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static int aduc702x_write_single(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
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{
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{
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int x;
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int x;
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u8 b;
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u8 b;
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@ -399,12 +399,12 @@ int aduc702x_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
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return ERROR_OK;
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return ERROR_OK;
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}
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}
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int aduc702x_probe(struct flash_bank_s *bank)
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static int aduc702x_probe(struct flash_bank_s *bank)
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{
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{
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return ERROR_OK;
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return ERROR_OK;
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}
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}
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int aduc702x_info(struct flash_bank_s *bank, char *buf, int buf_size)
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static int aduc702x_info(struct flash_bank_s *bank, char *buf, int buf_size)
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{
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{
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snprintf(buf, buf_size, "aduc702x flash driver info" );
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snprintf(buf, buf_size, "aduc702x flash driver info" );
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return ERROR_OK;
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return ERROR_OK;
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@ -412,7 +412,7 @@ int aduc702x_info(struct flash_bank_s *bank, char *buf, int buf_size)
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/* sets FEEMOD bit 3
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/* sets FEEMOD bit 3
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* enable = 1 enables writes & erases, 0 disables them */
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* enable = 1 enables writes & erases, 0 disables them */
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int aduc702x_set_write_enable(target_t *target, int enable)
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static int aduc702x_set_write_enable(target_t *target, int enable)
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{
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{
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// don't bother to preserve int enable bit here
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// don't bother to preserve int enable bit here
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target_write_u16(target, ADUC702x_FLASH + ADUC702x_FLASH_FEEMOD, enable ? 8 : 0);
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target_write_u16(target, ADUC702x_FLASH + ADUC702x_FLASH_FEEMOD, enable ? 8 : 0);
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@ -425,7 +425,7 @@ int aduc702x_set_write_enable(target_t *target, int enable)
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*
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*
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* this function sleeps 1ms between checks (after the first one),
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* this function sleeps 1ms between checks (after the first one),
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* so in some cases may slow things down without a usleep after the first read */
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* so in some cases may slow things down without a usleep after the first read */
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int aduc702x_check_flash_completion(target_t* target, unsigned int timeout_ms)
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static int aduc702x_check_flash_completion(target_t* target, unsigned int timeout_ms)
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{
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{
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u8 v = 4;
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u8 v = 4;
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@ -53,22 +53,22 @@
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#include <string.h>
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#include <string.h>
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#include <unistd.h>
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#include <unistd.h>
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int at91sam7_register_commands(struct command_context_s *cmd_ctx);
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static int at91sam7_register_commands(struct command_context_s *cmd_ctx);
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int at91sam7_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank);
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static int at91sam7_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank);
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int at91sam7_erase(struct flash_bank_s *bank, int first, int last);
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static int at91sam7_erase(struct flash_bank_s *bank, int first, int last);
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int at91sam7_protect(struct flash_bank_s *bank, int set, int first, int last);
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static int at91sam7_protect(struct flash_bank_s *bank, int set, int first, int last);
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int at91sam7_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count);
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static int at91sam7_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count);
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int at91sam7_probe(struct flash_bank_s *bank);
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static int at91sam7_probe(struct flash_bank_s *bank);
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int at91sam7_auto_probe(struct flash_bank_s *bank);
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//static int at91sam7_auto_probe(struct flash_bank_s *bank);
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int at91sam7_erase_check(struct flash_bank_s *bank);
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static int at91sam7_erase_check(struct flash_bank_s *bank);
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int at91sam7_protect_check(struct flash_bank_s *bank);
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static int at91sam7_protect_check(struct flash_bank_s *bank);
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int at91sam7_info(struct flash_bank_s *bank, char *buf, int buf_size);
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static int at91sam7_info(struct flash_bank_s *bank, char *buf, int buf_size);
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u32 at91sam7_get_flash_status(target_t *target, int bank_number);
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static u32 at91sam7_get_flash_status(target_t *target, int bank_number);
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void at91sam7_set_flash_mode(flash_bank_t *bank, int mode);
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static void at91sam7_set_flash_mode(flash_bank_t *bank, int mode);
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u32 at91sam7_wait_status_busy(flash_bank_t *bank, u32 waitbits, int timeout);
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static u32 at91sam7_wait_status_busy(flash_bank_t *bank, u32 waitbits, int timeout);
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int at91sam7_flash_command(struct flash_bank_s *bank, u8 cmd, u16 pagen);
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static int at91sam7_flash_command(struct flash_bank_s *bank, u8 cmd, u16 pagen);
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int at91sam7_handle_gpnvm_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
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static int at91sam7_handle_gpnvm_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
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flash_driver_t at91sam7_flash =
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flash_driver_t at91sam7_flash =
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{
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{
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@ -85,13 +85,14 @@ flash_driver_t at91sam7_flash =
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.info = at91sam7_info
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.info = at91sam7_info
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};
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};
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u32 MC_FMR[4] = { 0xFFFFFF60, 0xFFFFFF70, 0xFFFFFF80, 0xFFFFFF90 };
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static u32 MC_FMR[4] = { 0xFFFFFF60, 0xFFFFFF70, 0xFFFFFF80, 0xFFFFFF90 };
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u32 MC_FCR[4] = { 0xFFFFFF64, 0xFFFFFF74, 0xFFFFFF84, 0xFFFFFF94 };
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static u32 MC_FCR[4] = { 0xFFFFFF64, 0xFFFFFF74, 0xFFFFFF84, 0xFFFFFF94 };
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u32 MC_FSR[4] = { 0xFFFFFF68, 0xFFFFFF78, 0xFFFFFF88, 0xFFFFFF98 };
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static u32 MC_FSR[4] = { 0xFFFFFF68, 0xFFFFFF78, 0xFFFFFF88, 0xFFFFFF98 };
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char * EPROC[8]= {"Unknown","ARM946-E","ARM7TDMI","Unknown","ARM920T","ARM926EJ-S","Unknown","Unknown"};
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static char * EPROC[8]= {"Unknown","ARM946-E","ARM7TDMI","Unknown","ARM920T","ARM926EJ-S","Unknown","Unknown"};
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long SRAMSIZ[16] = {
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#if 0
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static long SRAMSIZ[16] = {
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-1,
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-1,
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0x0400, /* 1K */
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0x0400, /* 1K */
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0x0800, /* 2K */
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0x0800, /* 2K */
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@ -109,8 +110,9 @@ long SRAMSIZ[16] = {
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0x18000, /* 96K */
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0x18000, /* 96K */
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0x80000, /* 512K */
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0x80000, /* 512K */
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};
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};
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#endif
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int at91sam7_register_commands(struct command_context_s *cmd_ctx)
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static int at91sam7_register_commands(struct command_context_s *cmd_ctx)
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{
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{
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command_t *at91sam7_cmd = register_command(cmd_ctx, NULL, "at91sam7_new", NULL, COMMAND_ANY, NULL);
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command_t *at91sam7_cmd = register_command(cmd_ctx, NULL, "at91sam7_new", NULL, COMMAND_ANY, NULL);
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@ -119,7 +121,7 @@ int at91sam7_register_commands(struct command_context_s *cmd_ctx)
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return ERROR_OK;
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return ERROR_OK;
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}
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}
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u32 at91sam7_get_flash_status(target_t *target, int bank_number)
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static u32 at91sam7_get_flash_status(target_t *target, int bank_number)
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{
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{
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u32 fsr;
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u32 fsr;
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target_read_u32(target, MC_FSR[bank_number], &fsr);
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target_read_u32(target, MC_FSR[bank_number], &fsr);
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}
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}
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/* Read clock configuration and set at91sam7_info->mck_freq */
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/* Read clock configuration and set at91sam7_info->mck_freq */
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void at91sam7_read_clock_info(flash_bank_t *bank)
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static void at91sam7_read_clock_info(flash_bank_t *bank)
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{
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{
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at91sam7_flash_bank_t *at91sam7_info = bank->driver_priv;
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at91sam7_flash_bank_t *at91sam7_info = bank->driver_priv;
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target_t *target = bank->target;
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target_t *target = bank->target;
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@ -207,7 +209,7 @@ void at91sam7_read_clock_info(flash_bank_t *bank)
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}
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}
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/* Setup the timimg registers for nvbits or normal flash */
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/* Setup the timimg registers for nvbits or normal flash */
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void at91sam7_set_flash_mode(flash_bank_t *bank, int mode)
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static void at91sam7_set_flash_mode(flash_bank_t *bank, int mode)
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{
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{
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u32 fmr, fmcn = 0, fws = 0;
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u32 fmr, fmcn = 0, fws = 0;
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at91sam7_flash_bank_t *at91sam7_info = bank->driver_priv;
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at91sam7_flash_bank_t *at91sam7_info = bank->driver_priv;
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at91sam7_info->flashmode = mode;
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at91sam7_info->flashmode = mode;
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}
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}
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u32 at91sam7_wait_status_busy(flash_bank_t *bank, u32 waitbits, int timeout)
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static u32 at91sam7_wait_status_busy(flash_bank_t *bank, u32 waitbits, int timeout)
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{
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{
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u32 status;
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u32 status;
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@ -282,7 +284,7 @@ u32 at91sam7_wait_status_busy(flash_bank_t *bank, u32 waitbits, int timeout)
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}
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}
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/* Send one command to the AT91SAM flash controller */
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/* Send one command to the AT91SAM flash controller */
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int at91sam7_flash_command(struct flash_bank_s *bank, u8 cmd, u16 pagen)
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static int at91sam7_flash_command(struct flash_bank_s *bank, u8 cmd, u16 pagen)
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{
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{
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u32 fcr;
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u32 fcr;
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at91sam7_flash_bank_t *at91sam7_info = bank->driver_priv;
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at91sam7_flash_bank_t *at91sam7_info = bank->driver_priv;
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@ -311,7 +313,7 @@ int at91sam7_flash_command(struct flash_bank_s *bank, u8 cmd, u16 pagen)
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}
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}
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/* Read device id register, main clock frequency register and fill in driver info structure */
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/* Read device id register, main clock frequency register and fill in driver info structure */
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int at91sam7_read_part_info(struct flash_bank_s *bank)
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static int at91sam7_read_part_info(struct flash_bank_s *bank)
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{
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{
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flash_bank_t *t_bank = bank;
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flash_bank_t *t_bank = bank;
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at91sam7_flash_bank_t *at91sam7_info;
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at91sam7_flash_bank_t *at91sam7_info;
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@ -626,7 +628,7 @@ int at91sam7_read_part_info(struct flash_bank_s *bank)
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return ERROR_OK;
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return ERROR_OK;
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}
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}
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int at91sam7_erase_check(struct flash_bank_s *bank)
|
static int at91sam7_erase_check(struct flash_bank_s *bank)
|
||||||
{
|
{
|
||||||
target_t *target = bank->target;
|
target_t *target = bank->target;
|
||||||
u16 retval;
|
u16 retval;
|
||||||
|
|
@ -692,7 +694,7 @@ int at91sam7_erase_check(struct flash_bank_s *bank)
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
int at91sam7_protect_check(struct flash_bank_s *bank)
|
static int at91sam7_protect_check(struct flash_bank_s *bank)
|
||||||
{
|
{
|
||||||
u8 lock_pos, gpnvm_pos;
|
u8 lock_pos, gpnvm_pos;
|
||||||
u32 status;
|
u32 status;
|
||||||
|
|
@ -752,7 +754,7 @@ int at91sam7_protect_check(struct flash_bank_s *bank)
|
||||||
# flash bank at91sam7 0x00100000 0 0 4 0 0 AT91SAM7XC256 1 16 64 256 3 0 ==== NOT RECOMENDED !!! ====
|
# flash bank at91sam7 0x00100000 0 0 4 0 0 AT91SAM7XC256 1 16 64 256 3 0 ==== NOT RECOMENDED !!! ====
|
||||||
# flash bank at91sam7 0 0 0 0 0 (old style, full auto-detection) ==== NOT RECOMENDED !!! ====
|
# flash bank at91sam7 0 0 0 0 0 (old style, full auto-detection) ==== NOT RECOMENDED !!! ====
|
||||||
****************************************************************************************************************************************************************************************/
|
****************************************************************************************************************************************************************************************/
|
||||||
int at91sam7_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank)
|
static int at91sam7_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank)
|
||||||
{
|
{
|
||||||
flash_bank_t *t_bank = bank;
|
flash_bank_t *t_bank = bank;
|
||||||
at91sam7_flash_bank_t *at91sam7_info;
|
at91sam7_flash_bank_t *at91sam7_info;
|
||||||
|
|
@ -864,7 +866,7 @@ int at91sam7_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, ch
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
int at91sam7_erase(struct flash_bank_s *bank, int first, int last)
|
static int at91sam7_erase(struct flash_bank_s *bank, int first, int last)
|
||||||
{
|
{
|
||||||
at91sam7_flash_bank_t *at91sam7_info = bank->driver_priv;
|
at91sam7_flash_bank_t *at91sam7_info = bank->driver_priv;
|
||||||
int sec;
|
int sec;
|
||||||
|
|
@ -932,7 +934,7 @@ int at91sam7_erase(struct flash_bank_s *bank, int first, int last)
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
int at91sam7_protect(struct flash_bank_s *bank, int set, int first, int last)
|
static int at91sam7_protect(struct flash_bank_s *bank, int set, int first, int last)
|
||||||
{
|
{
|
||||||
u32 cmd;
|
u32 cmd;
|
||||||
u32 sector, pagen;
|
u32 sector, pagen;
|
||||||
|
|
@ -981,7 +983,7 @@ int at91sam7_protect(struct flash_bank_s *bank, int set, int first, int last)
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
int at91sam7_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
|
static int at91sam7_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
|
||||||
{
|
{
|
||||||
int retval;
|
int retval;
|
||||||
at91sam7_flash_bank_t *at91sam7_info = bank->driver_priv;
|
at91sam7_flash_bank_t *at91sam7_info = bank->driver_priv;
|
||||||
|
|
@ -1050,7 +1052,7 @@ int at91sam7_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
int at91sam7_probe(struct flash_bank_s *bank)
|
static int at91sam7_probe(struct flash_bank_s *bank)
|
||||||
{
|
{
|
||||||
/* we can't probe on an at91sam7
|
/* we can't probe on an at91sam7
|
||||||
* if this is an at91sam7, it has the configured flash */
|
* if this is an at91sam7, it has the configured flash */
|
||||||
|
|
@ -1069,7 +1071,7 @@ int at91sam7_probe(struct flash_bank_s *bank)
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
int at91sam7_info(struct flash_bank_s *bank, char *buf, int buf_size)
|
static int at91sam7_info(struct flash_bank_s *bank, char *buf, int buf_size)
|
||||||
{
|
{
|
||||||
int printed;
|
int printed;
|
||||||
at91sam7_flash_bank_t *at91sam7_info = bank->driver_priv;
|
at91sam7_flash_bank_t *at91sam7_info = bank->driver_priv;
|
||||||
|
|
@ -1130,7 +1132,7 @@ int at91sam7_info(struct flash_bank_s *bank, char *buf, int buf_size)
|
||||||
* The maximum number of write/erase cycles for Non volatile Memory bits is 100. this includes
|
* The maximum number of write/erase cycles for Non volatile Memory bits is 100. this includes
|
||||||
* Lock Bits (LOCKx), General Purpose NVM bits (GPNVMx) and the Security Bit.
|
* Lock Bits (LOCKx), General Purpose NVM bits (GPNVMx) and the Security Bit.
|
||||||
*/
|
*/
|
||||||
int at91sam7_handle_gpnvm_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
|
static int at91sam7_handle_gpnvm_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
|
||||||
{
|
{
|
||||||
flash_bank_t *bank;
|
flash_bank_t *bank;
|
||||||
int bit;
|
int bit;
|
||||||
|
|
|
||||||
|
|
@ -51,22 +51,22 @@ There are some things to notice
|
||||||
#include <string.h>
|
#include <string.h>
|
||||||
#include <unistd.h>
|
#include <unistd.h>
|
||||||
|
|
||||||
int at91sam7_old_register_commands(struct command_context_s *cmd_ctx);
|
static int at91sam7_old_register_commands(struct command_context_s *cmd_ctx);
|
||||||
int at91sam7_old_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank);
|
static int at91sam7_old_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank);
|
||||||
int at91sam7_old_erase(struct flash_bank_s *bank, int first, int last);
|
static int at91sam7_old_erase(struct flash_bank_s *bank, int first, int last);
|
||||||
int at91sam7_old_protect(struct flash_bank_s *bank, int set, int first, int last);
|
static int at91sam7_old_protect(struct flash_bank_s *bank, int set, int first, int last);
|
||||||
int at91sam7_old_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count);
|
static int at91sam7_old_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count);
|
||||||
int at91sam7_old_probe(struct flash_bank_s *bank);
|
static int at91sam7_old_probe(struct flash_bank_s *bank);
|
||||||
int at91sam7_old_auto_probe(struct flash_bank_s *bank);
|
//static int at91sam7_old_auto_probe(struct flash_bank_s *bank);
|
||||||
int at91sam7_old_erase_check(struct flash_bank_s *bank);
|
static int at91sam7_old_erase_check(struct flash_bank_s *bank);
|
||||||
int at91sam7_old_protect_check(struct flash_bank_s *bank);
|
static int at91sam7_old_protect_check(struct flash_bank_s *bank);
|
||||||
int at91sam7_old_info(struct flash_bank_s *bank, char *buf, int buf_size);
|
static int at91sam7_old_info(struct flash_bank_s *bank, char *buf, int buf_size);
|
||||||
|
|
||||||
u32 at91sam7_old_get_flash_status(flash_bank_t *bank, u8 flashplane);
|
static u32 at91sam7_old_get_flash_status(flash_bank_t *bank, u8 flashplane);
|
||||||
void at91sam7_old_set_flash_mode(flash_bank_t *bank, u8 flashplane, int mode);
|
static void at91sam7_old_set_flash_mode(flash_bank_t *bank, u8 flashplane, int mode);
|
||||||
u32 at91sam7_old_wait_status_busy(flash_bank_t *bank, u8 flashplane, u32 waitbits, int timeout);
|
static u32 at91sam7_old_wait_status_busy(flash_bank_t *bank, u8 flashplane, u32 waitbits, int timeout);
|
||||||
int at91sam7_old_flash_command(struct flash_bank_s *bank, u8 flashplane, u8 cmd, u16 pagen);
|
static int at91sam7_old_flash_command(struct flash_bank_s *bank, u8 flashplane, u8 cmd, u16 pagen);
|
||||||
int at91sam7_old_handle_gpnvm_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
|
static int at91sam7_old_handle_gpnvm_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
|
||||||
|
|
||||||
flash_driver_t at91sam7_old_flash =
|
flash_driver_t at91sam7_old_flash =
|
||||||
{
|
{
|
||||||
|
|
@ -83,12 +83,12 @@ flash_driver_t at91sam7_old_flash =
|
||||||
.info = at91sam7_old_info
|
.info = at91sam7_old_info
|
||||||
};
|
};
|
||||||
|
|
||||||
u32 MC_FMR_old[4] = { 0xFFFFFF60, 0xFFFFFF70, 0xFFFFFF80, 0xFFFFFF90 };
|
static u32 MC_FMR_old[4] = { 0xFFFFFF60, 0xFFFFFF70, 0xFFFFFF80, 0xFFFFFF90 };
|
||||||
u32 MC_FCR_old[4] = { 0xFFFFFF64, 0xFFFFFF74, 0xFFFFFF84, 0xFFFFFF94 };
|
static u32 MC_FCR_old[4] = { 0xFFFFFF64, 0xFFFFFF74, 0xFFFFFF84, 0xFFFFFF94 };
|
||||||
u32 MC_FSR_old[4] = { 0xFFFFFF68, 0xFFFFFF78, 0xFFFFFF88, 0xFFFFFF98 };
|
static u32 MC_FSR_old[4] = { 0xFFFFFF68, 0xFFFFFF78, 0xFFFFFF88, 0xFFFFFF98 };
|
||||||
|
|
||||||
char * EPROC_old[8]= {"Unknown","ARM946-E","ARM7TDMI","Unknown","ARM920T","ARM926EJ-S","Unknown","Unknown"};
|
static char * EPROC_old[8]= {"Unknown","ARM946-E","ARM7TDMI","Unknown","ARM920T","ARM926EJ-S","Unknown","Unknown"};
|
||||||
long NVPSIZ_old[16] = {
|
static long NVPSIZ_old[16] = {
|
||||||
0,
|
0,
|
||||||
0x2000, /* 8K */
|
0x2000, /* 8K */
|
||||||
0x4000, /* 16K */
|
0x4000, /* 16K */
|
||||||
|
|
@ -107,7 +107,8 @@ long NVPSIZ_old[16] = {
|
||||||
-1
|
-1
|
||||||
};
|
};
|
||||||
|
|
||||||
long SRAMSIZ_old[16] = {
|
#if 0
|
||||||
|
static long SRAMSIZ_old[16] = {
|
||||||
-1,
|
-1,
|
||||||
0x0400, /* 1K */
|
0x0400, /* 1K */
|
||||||
0x0800, /* 2K */
|
0x0800, /* 2K */
|
||||||
|
|
@ -125,8 +126,9 @@ long SRAMSIZ_old[16] = {
|
||||||
0x18000, /* 96K */
|
0x18000, /* 96K */
|
||||||
0x80000, /* 512K */
|
0x80000, /* 512K */
|
||||||
};
|
};
|
||||||
|
#endif
|
||||||
|
|
||||||
int at91sam7_old_register_commands(struct command_context_s *cmd_ctx)
|
static int at91sam7_old_register_commands(struct command_context_s *cmd_ctx)
|
||||||
{
|
{
|
||||||
command_t *at91sam7_old_cmd = register_command(cmd_ctx, NULL, "at91sam7", NULL, COMMAND_ANY, NULL);
|
command_t *at91sam7_old_cmd = register_command(cmd_ctx, NULL, "at91sam7", NULL, COMMAND_ANY, NULL);
|
||||||
register_command(cmd_ctx, at91sam7_old_cmd, "gpnvm", at91sam7_old_handle_gpnvm_command, COMMAND_EXEC,
|
register_command(cmd_ctx, at91sam7_old_cmd, "gpnvm", at91sam7_old_handle_gpnvm_command, COMMAND_EXEC,
|
||||||
|
|
@ -135,7 +137,7 @@ int at91sam7_old_register_commands(struct command_context_s *cmd_ctx)
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
u32 at91sam7_old_get_flash_status(flash_bank_t *bank, u8 flashplane)
|
static u32 at91sam7_old_get_flash_status(flash_bank_t *bank, u8 flashplane)
|
||||||
{
|
{
|
||||||
target_t *target = bank->target;
|
target_t *target = bank->target;
|
||||||
u32 fsr;
|
u32 fsr;
|
||||||
|
|
@ -146,7 +148,7 @@ u32 at91sam7_old_get_flash_status(flash_bank_t *bank, u8 flashplane)
|
||||||
}
|
}
|
||||||
|
|
||||||
/* Read clock configuration and set at91sam7_old_info->usec_clocks*/
|
/* Read clock configuration and set at91sam7_old_info->usec_clocks*/
|
||||||
void at91sam7_old_read_clock_info(flash_bank_t *bank)
|
static void at91sam7_old_read_clock_info(flash_bank_t *bank)
|
||||||
{
|
{
|
||||||
at91sam7_old_flash_bank_t *at91sam7_old_info = bank->driver_priv;
|
at91sam7_old_flash_bank_t *at91sam7_old_info = bank->driver_priv;
|
||||||
target_t *target = bank->target;
|
target_t *target = bank->target;
|
||||||
|
|
@ -210,7 +212,7 @@ void at91sam7_old_read_clock_info(flash_bank_t *bank)
|
||||||
}
|
}
|
||||||
|
|
||||||
/* Setup the timimg registers for nvbits or normal flash */
|
/* Setup the timimg registers for nvbits or normal flash */
|
||||||
void at91sam7_old_set_flash_mode(flash_bank_t *bank, u8 flashplane, int mode)
|
static void at91sam7_old_set_flash_mode(flash_bank_t *bank, u8 flashplane, int mode)
|
||||||
{
|
{
|
||||||
u32 fmr, fmcn = 0, fws = 0;
|
u32 fmr, fmcn = 0, fws = 0;
|
||||||
at91sam7_old_flash_bank_t *at91sam7_old_info = bank->driver_priv;
|
at91sam7_old_flash_bank_t *at91sam7_old_info = bank->driver_priv;
|
||||||
|
|
@ -251,7 +253,7 @@ void at91sam7_old_set_flash_mode(flash_bank_t *bank, u8 flashplane, int mode)
|
||||||
at91sam7_old_info->flashmode[flashplane] = mode;
|
at91sam7_old_info->flashmode[flashplane] = mode;
|
||||||
}
|
}
|
||||||
|
|
||||||
u32 at91sam7_old_wait_status_busy(flash_bank_t *bank, u8 flashplane, u32 waitbits, int timeout)
|
static u32 at91sam7_old_wait_status_busy(flash_bank_t *bank, u8 flashplane, u32 waitbits, int timeout)
|
||||||
{
|
{
|
||||||
u32 status;
|
u32 status;
|
||||||
|
|
||||||
|
|
@ -279,7 +281,7 @@ u32 at91sam7_old_wait_status_busy(flash_bank_t *bank, u8 flashplane, u32 waitbit
|
||||||
|
|
||||||
|
|
||||||
/* Send one command to the AT91SAM flash controller */
|
/* Send one command to the AT91SAM flash controller */
|
||||||
int at91sam7_old_flash_command(struct flash_bank_s *bank, u8 flashplane, u8 cmd, u16 pagen)
|
static int at91sam7_old_flash_command(struct flash_bank_s *bank, u8 flashplane, u8 cmd, u16 pagen)
|
||||||
{
|
{
|
||||||
u32 fcr;
|
u32 fcr;
|
||||||
at91sam7_old_flash_bank_t *at91sam7_old_info = bank->driver_priv;
|
at91sam7_old_flash_bank_t *at91sam7_old_info = bank->driver_priv;
|
||||||
|
|
@ -307,7 +309,7 @@ int at91sam7_old_flash_command(struct flash_bank_s *bank, u8 flashplane, u8 cmd,
|
||||||
}
|
}
|
||||||
|
|
||||||
/* Read device id register, main clock frequency register and fill in driver info structure */
|
/* Read device id register, main clock frequency register and fill in driver info structure */
|
||||||
int at91sam7_old_read_part_info(struct flash_bank_s *bank)
|
static int at91sam7_old_read_part_info(struct flash_bank_s *bank)
|
||||||
{
|
{
|
||||||
at91sam7_old_flash_bank_t *at91sam7_old_info = bank->driver_priv;
|
at91sam7_old_flash_bank_t *at91sam7_old_info = bank->driver_priv;
|
||||||
target_t *target = bank->target;
|
target_t *target = bank->target;
|
||||||
|
|
@ -574,7 +576,7 @@ int at91sam7_old_erase_check(struct flash_bank_s *bank)
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
int at91sam7_old_protect_check(struct flash_bank_s *bank)
|
static int at91sam7_old_protect_check(struct flash_bank_s *bank)
|
||||||
{
|
{
|
||||||
u32 status;
|
u32 status;
|
||||||
int flashplane;
|
int flashplane;
|
||||||
|
|
@ -625,7 +627,7 @@ int at91sam7_old_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
int at91sam7_old_erase(struct flash_bank_s *bank, int first, int last)
|
static int at91sam7_old_erase(struct flash_bank_s *bank, int first, int last)
|
||||||
{
|
{
|
||||||
at91sam7_old_flash_bank_t *at91sam7_old_info = bank->driver_priv;
|
at91sam7_old_flash_bank_t *at91sam7_old_info = bank->driver_priv;
|
||||||
u8 flashplane;
|
u8 flashplane;
|
||||||
|
|
@ -716,7 +718,7 @@ int at91sam7_old_protect(struct flash_bank_s *bank, int set, int first, int last
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
int at91sam7_old_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
|
static int at91sam7_old_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
|
||||||
{
|
{
|
||||||
at91sam7_old_flash_bank_t *at91sam7_old_info = bank->driver_priv;
|
at91sam7_old_flash_bank_t *at91sam7_old_info = bank->driver_priv;
|
||||||
target_t *target = bank->target;
|
target_t *target = bank->target;
|
||||||
|
|
@ -784,7 +786,7 @@ int at91sam7_old_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 co
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
int at91sam7_old_probe(struct flash_bank_s *bank)
|
static int at91sam7_old_probe(struct flash_bank_s *bank)
|
||||||
{
|
{
|
||||||
/* we can't probe on an at91sam7_old
|
/* we can't probe on an at91sam7_old
|
||||||
* if this is an at91sam7_old, it has the configured flash
|
* if this is an at91sam7_old, it has the configured flash
|
||||||
|
|
@ -811,7 +813,7 @@ int at91sam7_old_probe(struct flash_bank_s *bank)
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
int at91sam7_old_info(struct flash_bank_s *bank, char *buf, int buf_size)
|
static int at91sam7_old_info(struct flash_bank_s *bank, char *buf, int buf_size)
|
||||||
{
|
{
|
||||||
int printed, flashplane;
|
int printed, flashplane;
|
||||||
at91sam7_old_flash_bank_t *at91sam7_old_info = bank->driver_priv;
|
at91sam7_old_flash_bank_t *at91sam7_old_info = bank->driver_priv;
|
||||||
|
|
@ -871,7 +873,7 @@ int at91sam7_old_info(struct flash_bank_s *bank, char *buf, int buf_size)
|
||||||
* The maximum number of write/erase cycles for Non Volatile Memory bits is 100. This includes
|
* The maximum number of write/erase cycles for Non Volatile Memory bits is 100. This includes
|
||||||
* Lock Bits (LOCKx), General Purpose NVM bits (GPNVMx) and the Security Bit.
|
* Lock Bits (LOCKx), General Purpose NVM bits (GPNVMx) and the Security Bit.
|
||||||
*/
|
*/
|
||||||
int at91sam7_old_handle_gpnvm_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
|
static int at91sam7_old_handle_gpnvm_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
|
||||||
{
|
{
|
||||||
flash_bank_t *bank;
|
flash_bank_t *bank;
|
||||||
int bit;
|
int bit;
|
||||||
|
|
|
||||||
110
src/flash/cfi.c
110
src/flash/cfi.c
|
|
@ -38,17 +38,17 @@
|
||||||
#include <string.h>
|
#include <string.h>
|
||||||
#include <unistd.h>
|
#include <unistd.h>
|
||||||
|
|
||||||
int cfi_register_commands(struct command_context_s *cmd_ctx);
|
static int cfi_register_commands(struct command_context_s *cmd_ctx);
|
||||||
int cfi_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank);
|
static int cfi_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank);
|
||||||
int cfi_erase(struct flash_bank_s *bank, int first, int last);
|
static int cfi_erase(struct flash_bank_s *bank, int first, int last);
|
||||||
int cfi_protect(struct flash_bank_s *bank, int set, int first, int last);
|
static int cfi_protect(struct flash_bank_s *bank, int set, int first, int last);
|
||||||
int cfi_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count);
|
static int cfi_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count);
|
||||||
int cfi_probe(struct flash_bank_s *bank);
|
static int cfi_probe(struct flash_bank_s *bank);
|
||||||
int cfi_auto_probe(struct flash_bank_s *bank);
|
static int cfi_auto_probe(struct flash_bank_s *bank);
|
||||||
int cfi_protect_check(struct flash_bank_s *bank);
|
static int cfi_protect_check(struct flash_bank_s *bank);
|
||||||
int cfi_info(struct flash_bank_s *bank, char *buf, int buf_size);
|
static int cfi_info(struct flash_bank_s *bank, char *buf, int buf_size);
|
||||||
|
|
||||||
int cfi_handle_part_id_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
|
//static int cfi_handle_part_id_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
|
||||||
|
|
||||||
#define CFI_MAX_BUS_WIDTH 4
|
#define CFI_MAX_BUS_WIDTH 4
|
||||||
#define CFI_MAX_CHIP_WIDTH 4
|
#define CFI_MAX_CHIP_WIDTH 4
|
||||||
|
|
@ -71,19 +71,19 @@ flash_driver_t cfi_flash =
|
||||||
.info = cfi_info
|
.info = cfi_info
|
||||||
};
|
};
|
||||||
|
|
||||||
cfi_unlock_addresses_t cfi_unlock_addresses[] =
|
static cfi_unlock_addresses_t cfi_unlock_addresses[] =
|
||||||
{
|
{
|
||||||
[CFI_UNLOCK_555_2AA] = { .unlock1 = 0x555, .unlock2 = 0x2aa },
|
[CFI_UNLOCK_555_2AA] = { .unlock1 = 0x555, .unlock2 = 0x2aa },
|
||||||
[CFI_UNLOCK_5555_2AAA] = { .unlock1 = 0x5555, .unlock2 = 0x2aaa },
|
[CFI_UNLOCK_5555_2AAA] = { .unlock1 = 0x5555, .unlock2 = 0x2aaa },
|
||||||
};
|
};
|
||||||
|
|
||||||
/* CFI fixups foward declarations */
|
/* CFI fixups foward declarations */
|
||||||
void cfi_fixup_0002_erase_regions(flash_bank_t *flash, void *param);
|
static void cfi_fixup_0002_erase_regions(flash_bank_t *flash, void *param);
|
||||||
void cfi_fixup_0002_unlock_addresses(flash_bank_t *flash, void *param);
|
static void cfi_fixup_0002_unlock_addresses(flash_bank_t *flash, void *param);
|
||||||
void cfi_fixup_atmel_reversed_erase_regions(flash_bank_t *flash, void *param);
|
static void cfi_fixup_atmel_reversed_erase_regions(flash_bank_t *flash, void *param);
|
||||||
|
|
||||||
/* fixup after identifying JEDEC manufactuer and ID */
|
/* fixup after identifying JEDEC manufactuer and ID */
|
||||||
cfi_fixup_t cfi_jedec_fixups[] = {
|
static cfi_fixup_t cfi_jedec_fixups[] = {
|
||||||
{CFI_MFR_SST, 0x00D4, cfi_fixup_non_cfi, NULL},
|
{CFI_MFR_SST, 0x00D4, cfi_fixup_non_cfi, NULL},
|
||||||
{CFI_MFR_SST, 0x00D5, cfi_fixup_non_cfi, NULL},
|
{CFI_MFR_SST, 0x00D5, cfi_fixup_non_cfi, NULL},
|
||||||
{CFI_MFR_SST, 0x00D6, cfi_fixup_non_cfi, NULL},
|
{CFI_MFR_SST, 0x00D6, cfi_fixup_non_cfi, NULL},
|
||||||
|
|
@ -101,7 +101,7 @@ cfi_fixup_t cfi_jedec_fixups[] = {
|
||||||
};
|
};
|
||||||
|
|
||||||
/* fixup after reading cmdset 0002 primary query table */
|
/* fixup after reading cmdset 0002 primary query table */
|
||||||
cfi_fixup_t cfi_0002_fixups[] = {
|
static cfi_fixup_t cfi_0002_fixups[] = {
|
||||||
{CFI_MFR_SST, 0x00D4, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
|
{CFI_MFR_SST, 0x00D4, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
|
||||||
{CFI_MFR_SST, 0x00D5, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
|
{CFI_MFR_SST, 0x00D5, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
|
||||||
{CFI_MFR_SST, 0x00D6, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
|
{CFI_MFR_SST, 0x00D6, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
|
||||||
|
|
@ -117,11 +117,11 @@ cfi_fixup_t cfi_0002_fixups[] = {
|
||||||
};
|
};
|
||||||
|
|
||||||
/* fixup after reading cmdset 0001 primary query table */
|
/* fixup after reading cmdset 0001 primary query table */
|
||||||
cfi_fixup_t cfi_0001_fixups[] = {
|
static cfi_fixup_t cfi_0001_fixups[] = {
|
||||||
{0, 0, NULL, NULL}
|
{0, 0, NULL, NULL}
|
||||||
};
|
};
|
||||||
|
|
||||||
void cfi_fixup(flash_bank_t *bank, cfi_fixup_t *fixups)
|
static void cfi_fixup(flash_bank_t *bank, cfi_fixup_t *fixups)
|
||||||
{
|
{
|
||||||
cfi_flash_bank_t *cfi_info = bank->driver_priv;
|
cfi_flash_bank_t *cfi_info = bank->driver_priv;
|
||||||
cfi_fixup_t *f;
|
cfi_fixup_t *f;
|
||||||
|
|
@ -154,7 +154,7 @@ __inline__ u32 flash_address(flash_bank_t *bank, int sector, u32 offset)
|
||||||
|
|
||||||
}
|
}
|
||||||
|
|
||||||
void cfi_command(flash_bank_t *bank, u8 cmd, u8 *cmd_buf)
|
static void cfi_command(flash_bank_t *bank, u8 cmd, u8 *cmd_buf)
|
||||||
{
|
{
|
||||||
int i;
|
int i;
|
||||||
|
|
||||||
|
|
@ -184,7 +184,7 @@ void cfi_command(flash_bank_t *bank, u8 cmd, u8 *cmd_buf)
|
||||||
* flash banks are expected to be made of similar chips
|
* flash banks are expected to be made of similar chips
|
||||||
* the query result should be the same for all
|
* the query result should be the same for all
|
||||||
*/
|
*/
|
||||||
u8 cfi_query_u8(flash_bank_t *bank, int sector, u32 offset)
|
static u8 cfi_query_u8(flash_bank_t *bank, int sector, u32 offset)
|
||||||
{
|
{
|
||||||
target_t *target = bank->target;
|
target_t *target = bank->target;
|
||||||
u8 data[CFI_MAX_BUS_WIDTH];
|
u8 data[CFI_MAX_BUS_WIDTH];
|
||||||
|
|
@ -201,7 +201,7 @@ u8 cfi_query_u8(flash_bank_t *bank, int sector, u32 offset)
|
||||||
* in case of a bank made of multiple chips,
|
* in case of a bank made of multiple chips,
|
||||||
* the individual values are ORed
|
* the individual values are ORed
|
||||||
*/
|
*/
|
||||||
u8 cfi_get_u8(flash_bank_t *bank, int sector, u32 offset)
|
static u8 cfi_get_u8(flash_bank_t *bank, int sector, u32 offset)
|
||||||
{
|
{
|
||||||
target_t *target = bank->target;
|
target_t *target = bank->target;
|
||||||
u8 data[CFI_MAX_BUS_WIDTH];
|
u8 data[CFI_MAX_BUS_WIDTH];
|
||||||
|
|
@ -226,7 +226,7 @@ u8 cfi_get_u8(flash_bank_t *bank, int sector, u32 offset)
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
u16 cfi_query_u16(flash_bank_t *bank, int sector, u32 offset)
|
static u16 cfi_query_u16(flash_bank_t *bank, int sector, u32 offset)
|
||||||
{
|
{
|
||||||
target_t *target = bank->target;
|
target_t *target = bank->target;
|
||||||
u8 data[CFI_MAX_BUS_WIDTH * 2];
|
u8 data[CFI_MAX_BUS_WIDTH * 2];
|
||||||
|
|
@ -239,7 +239,7 @@ u16 cfi_query_u16(flash_bank_t *bank, int sector, u32 offset)
|
||||||
return data[bank->bus_width - 1] | data[(2 * bank->bus_width) - 1] << 8;
|
return data[bank->bus_width - 1] | data[(2 * bank->bus_width) - 1] << 8;
|
||||||
}
|
}
|
||||||
|
|
||||||
u32 cfi_query_u32(flash_bank_t *bank, int sector, u32 offset)
|
static u32 cfi_query_u32(flash_bank_t *bank, int sector, u32 offset)
|
||||||
{
|
{
|
||||||
target_t *target = bank->target;
|
target_t *target = bank->target;
|
||||||
u8 data[CFI_MAX_BUS_WIDTH * 4];
|
u8 data[CFI_MAX_BUS_WIDTH * 4];
|
||||||
|
|
@ -253,7 +253,7 @@ u32 cfi_query_u32(flash_bank_t *bank, int sector, u32 offset)
|
||||||
data[(3 * bank->bus_width) - 1] << 16 | data[(4 * bank->bus_width) - 1] << 24;
|
data[(3 * bank->bus_width) - 1] << 16 | data[(4 * bank->bus_width) - 1] << 24;
|
||||||
}
|
}
|
||||||
|
|
||||||
void cfi_intel_clear_status_register(flash_bank_t *bank)
|
static void cfi_intel_clear_status_register(flash_bank_t *bank)
|
||||||
{
|
{
|
||||||
target_t *target = bank->target;
|
target_t *target = bank->target;
|
||||||
u8 command[8];
|
u8 command[8];
|
||||||
|
|
@ -343,7 +343,7 @@ int cfi_spansion_wait_status_busy(flash_bank_t *bank, int timeout)
|
||||||
return(ERROR_FLASH_BUSY);
|
return(ERROR_FLASH_BUSY);
|
||||||
}
|
}
|
||||||
|
|
||||||
int cfi_read_intel_pri_ext(flash_bank_t *bank)
|
static int cfi_read_intel_pri_ext(flash_bank_t *bank)
|
||||||
{
|
{
|
||||||
int retval;
|
int retval;
|
||||||
cfi_flash_bank_t *cfi_info = bank->driver_priv;
|
cfi_flash_bank_t *cfi_info = bank->driver_priv;
|
||||||
|
|
@ -406,7 +406,7 @@ int cfi_read_intel_pri_ext(flash_bank_t *bank)
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
int cfi_read_spansion_pri_ext(flash_bank_t *bank)
|
static int cfi_read_spansion_pri_ext(flash_bank_t *bank)
|
||||||
{
|
{
|
||||||
int retval;
|
int retval;
|
||||||
cfi_flash_bank_t *cfi_info = bank->driver_priv;
|
cfi_flash_bank_t *cfi_info = bank->driver_priv;
|
||||||
|
|
@ -471,7 +471,7 @@ int cfi_read_spansion_pri_ext(flash_bank_t *bank)
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
int cfi_read_atmel_pri_ext(flash_bank_t *bank)
|
static int cfi_read_atmel_pri_ext(flash_bank_t *bank)
|
||||||
{
|
{
|
||||||
int retval;
|
int retval;
|
||||||
cfi_atmel_pri_ext_t atmel_pri_ext;
|
cfi_atmel_pri_ext_t atmel_pri_ext;
|
||||||
|
|
@ -538,7 +538,7 @@ int cfi_read_atmel_pri_ext(flash_bank_t *bank)
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
int cfi_read_0002_pri_ext(flash_bank_t *bank)
|
static int cfi_read_0002_pri_ext(flash_bank_t *bank)
|
||||||
{
|
{
|
||||||
cfi_flash_bank_t *cfi_info = bank->driver_priv;
|
cfi_flash_bank_t *cfi_info = bank->driver_priv;
|
||||||
|
|
||||||
|
|
@ -552,7 +552,7 @@ int cfi_read_0002_pri_ext(flash_bank_t *bank)
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
int cfi_spansion_info(struct flash_bank_s *bank, char *buf, int buf_size)
|
static int cfi_spansion_info(struct flash_bank_s *bank, char *buf, int buf_size)
|
||||||
{
|
{
|
||||||
int printed;
|
int printed;
|
||||||
cfi_flash_bank_t *cfi_info = bank->driver_priv;
|
cfi_flash_bank_t *cfi_info = bank->driver_priv;
|
||||||
|
|
@ -587,7 +587,7 @@ int cfi_spansion_info(struct flash_bank_s *bank, char *buf, int buf_size)
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
int cfi_intel_info(struct flash_bank_s *bank, char *buf, int buf_size)
|
static int cfi_intel_info(struct flash_bank_s *bank, char *buf, int buf_size)
|
||||||
{
|
{
|
||||||
int printed;
|
int printed;
|
||||||
cfi_flash_bank_t *cfi_info = bank->driver_priv;
|
cfi_flash_bank_t *cfi_info = bank->driver_priv;
|
||||||
|
|
@ -616,7 +616,7 @@ int cfi_intel_info(struct flash_bank_s *bank, char *buf, int buf_size)
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
int cfi_register_commands(struct command_context_s *cmd_ctx)
|
static int cfi_register_commands(struct command_context_s *cmd_ctx)
|
||||||
{
|
{
|
||||||
/*command_t *cfi_cmd = */
|
/*command_t *cfi_cmd = */
|
||||||
register_command(cmd_ctx, NULL, "cfi", NULL, COMMAND_ANY, "flash bank cfi <base> <size> <chip_width> <bus_width> <targetNum> [jedec_probe/x16_as_x8]");
|
register_command(cmd_ctx, NULL, "cfi", NULL, COMMAND_ANY, "flash bank cfi <base> <size> <chip_width> <bus_width> <targetNum> [jedec_probe/x16_as_x8]");
|
||||||
|
|
@ -629,7 +629,7 @@ int cfi_register_commands(struct command_context_s *cmd_ctx)
|
||||||
|
|
||||||
/* flash_bank cfi <base> <size> <chip_width> <bus_width> <target#> [options]
|
/* flash_bank cfi <base> <size> <chip_width> <bus_width> <target#> [options]
|
||||||
*/
|
*/
|
||||||
int cfi_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank)
|
static int cfi_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank)
|
||||||
{
|
{
|
||||||
cfi_flash_bank_t *cfi_info;
|
cfi_flash_bank_t *cfi_info;
|
||||||
int i;
|
int i;
|
||||||
|
|
@ -677,7 +677,7 @@ int cfi_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
int cfi_intel_erase(struct flash_bank_s *bank, int first, int last)
|
static int cfi_intel_erase(struct flash_bank_s *bank, int first, int last)
|
||||||
{
|
{
|
||||||
int retval;
|
int retval;
|
||||||
cfi_flash_bank_t *cfi_info = bank->driver_priv;
|
cfi_flash_bank_t *cfi_info = bank->driver_priv;
|
||||||
|
|
@ -721,7 +721,7 @@ int cfi_intel_erase(struct flash_bank_s *bank, int first, int last)
|
||||||
|
|
||||||
}
|
}
|
||||||
|
|
||||||
int cfi_spansion_erase(struct flash_bank_s *bank, int first, int last)
|
static int cfi_spansion_erase(struct flash_bank_s *bank, int first, int last)
|
||||||
{
|
{
|
||||||
int retval;
|
int retval;
|
||||||
cfi_flash_bank_t *cfi_info = bank->driver_priv;
|
cfi_flash_bank_t *cfi_info = bank->driver_priv;
|
||||||
|
|
@ -787,7 +787,7 @@ int cfi_spansion_erase(struct flash_bank_s *bank, int first, int last)
|
||||||
return target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
|
return target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
|
||||||
}
|
}
|
||||||
|
|
||||||
int cfi_erase(struct flash_bank_s *bank, int first, int last)
|
static int cfi_erase(struct flash_bank_s *bank, int first, int last)
|
||||||
{
|
{
|
||||||
cfi_flash_bank_t *cfi_info = bank->driver_priv;
|
cfi_flash_bank_t *cfi_info = bank->driver_priv;
|
||||||
|
|
||||||
|
|
@ -822,7 +822,7 @@ int cfi_erase(struct flash_bank_s *bank, int first, int last)
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
int cfi_intel_protect(struct flash_bank_s *bank, int set, int first, int last)
|
static int cfi_intel_protect(struct flash_bank_s *bank, int set, int first, int last)
|
||||||
{
|
{
|
||||||
int retval;
|
int retval;
|
||||||
cfi_flash_bank_t *cfi_info = bank->driver_priv;
|
cfi_flash_bank_t *cfi_info = bank->driver_priv;
|
||||||
|
|
@ -939,7 +939,7 @@ int cfi_intel_protect(struct flash_bank_s *bank, int set, int first, int last)
|
||||||
return target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
|
return target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
|
||||||
}
|
}
|
||||||
|
|
||||||
int cfi_protect(struct flash_bank_s *bank, int set, int first, int last)
|
static int cfi_protect(struct flash_bank_s *bank, int set, int first, int last)
|
||||||
{
|
{
|
||||||
cfi_flash_bank_t *cfi_info = bank->driver_priv;
|
cfi_flash_bank_t *cfi_info = bank->driver_priv;
|
||||||
|
|
||||||
|
|
@ -1018,7 +1018,7 @@ static void cfi_fix_code_endian(target_t *target, u8 *dest, const u32 *src, u32
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
u32 cfi_command_val(flash_bank_t *bank, u8 cmd)
|
static u32 cfi_command_val(flash_bank_t *bank, u8 cmd)
|
||||||
{
|
{
|
||||||
target_t *target = bank->target;
|
target_t *target = bank->target;
|
||||||
|
|
||||||
|
|
@ -1041,7 +1041,7 @@ u32 cfi_command_val(flash_bank_t *bank, u8 cmd)
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
int cfi_intel_write_block(struct flash_bank_s *bank, u8 *buffer, u32 address, u32 count)
|
static int cfi_intel_write_block(struct flash_bank_s *bank, u8 *buffer, u32 address, u32 count)
|
||||||
{
|
{
|
||||||
cfi_flash_bank_t *cfi_info = bank->driver_priv;
|
cfi_flash_bank_t *cfi_info = bank->driver_priv;
|
||||||
target_t *target = bank->target;
|
target_t *target = bank->target;
|
||||||
|
|
@ -1285,7 +1285,7 @@ cleanup:
|
||||||
return retval;
|
return retval;
|
||||||
}
|
}
|
||||||
|
|
||||||
int cfi_spansion_write_block(struct flash_bank_s *bank, u8 *buffer, u32 address, u32 count)
|
static int cfi_spansion_write_block(struct flash_bank_s *bank, u8 *buffer, u32 address, u32 count)
|
||||||
{
|
{
|
||||||
cfi_flash_bank_t *cfi_info = bank->driver_priv;
|
cfi_flash_bank_t *cfi_info = bank->driver_priv;
|
||||||
cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
|
cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
|
||||||
|
|
@ -1547,7 +1547,7 @@ int cfi_spansion_write_block(struct flash_bank_s *bank, u8 *buffer, u32 address,
|
||||||
return exit_code;
|
return exit_code;
|
||||||
}
|
}
|
||||||
|
|
||||||
int cfi_intel_write_word(struct flash_bank_s *bank, u8 *word, u32 address)
|
static int cfi_intel_write_word(struct flash_bank_s *bank, u8 *word, u32 address)
|
||||||
{
|
{
|
||||||
int retval;
|
int retval;
|
||||||
cfi_flash_bank_t *cfi_info = bank->driver_priv;
|
cfi_flash_bank_t *cfi_info = bank->driver_priv;
|
||||||
|
|
@ -1581,7 +1581,7 @@ int cfi_intel_write_word(struct flash_bank_s *bank, u8 *word, u32 address)
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
int cfi_intel_write_words(struct flash_bank_s *bank, u8 *word, u32 wordcount, u32 address)
|
static int cfi_intel_write_words(struct flash_bank_s *bank, u8 *word, u32 wordcount, u32 address)
|
||||||
{
|
{
|
||||||
int retval;
|
int retval;
|
||||||
cfi_flash_bank_t *cfi_info = bank->driver_priv;
|
cfi_flash_bank_t *cfi_info = bank->driver_priv;
|
||||||
|
|
@ -1673,7 +1673,7 @@ int cfi_intel_write_words(struct flash_bank_s *bank, u8 *word, u32 wordcount, u3
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
int cfi_spansion_write_word(struct flash_bank_s *bank, u8 *word, u32 address)
|
static int cfi_spansion_write_word(struct flash_bank_s *bank, u8 *word, u32 address)
|
||||||
{
|
{
|
||||||
int retval;
|
int retval;
|
||||||
cfi_flash_bank_t *cfi_info = bank->driver_priv;
|
cfi_flash_bank_t *cfi_info = bank->driver_priv;
|
||||||
|
|
@ -1719,7 +1719,7 @@ int cfi_spansion_write_word(struct flash_bank_s *bank, u8 *word, u32 address)
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
int cfi_spansion_write_words(struct flash_bank_s *bank, u8 *word, u32 wordcount, u32 address)
|
static int cfi_spansion_write_words(struct flash_bank_s *bank, u8 *word, u32 wordcount, u32 address)
|
||||||
{
|
{
|
||||||
int retval;
|
int retval;
|
||||||
cfi_flash_bank_t *cfi_info = bank->driver_priv;
|
cfi_flash_bank_t *cfi_info = bank->driver_priv;
|
||||||
|
|
@ -1811,7 +1811,7 @@ int cfi_spansion_write_words(struct flash_bank_s *bank, u8 *word, u32 wordcount,
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
int cfi_write_word(struct flash_bank_s *bank, u8 *word, u32 address)
|
static int cfi_write_word(struct flash_bank_s *bank, u8 *word, u32 address)
|
||||||
{
|
{
|
||||||
cfi_flash_bank_t *cfi_info = bank->driver_priv;
|
cfi_flash_bank_t *cfi_info = bank->driver_priv;
|
||||||
|
|
||||||
|
|
@ -1832,7 +1832,7 @@ int cfi_write_word(struct flash_bank_s *bank, u8 *word, u32 address)
|
||||||
return ERROR_FLASH_OPERATION_FAILED;
|
return ERROR_FLASH_OPERATION_FAILED;
|
||||||
}
|
}
|
||||||
|
|
||||||
int cfi_write_words(struct flash_bank_s *bank, u8 *word, u32 wordcount, u32 address)
|
static int cfi_write_words(struct flash_bank_s *bank, u8 *word, u32 wordcount, u32 address)
|
||||||
{
|
{
|
||||||
cfi_flash_bank_t *cfi_info = bank->driver_priv;
|
cfi_flash_bank_t *cfi_info = bank->driver_priv;
|
||||||
|
|
||||||
|
|
@ -2062,7 +2062,7 @@ int cfi_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
|
||||||
return target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, current_word);
|
return target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, current_word);
|
||||||
}
|
}
|
||||||
|
|
||||||
void cfi_fixup_atmel_reversed_erase_regions(flash_bank_t *bank, void *param)
|
static void cfi_fixup_atmel_reversed_erase_regions(flash_bank_t *bank, void *param)
|
||||||
{
|
{
|
||||||
cfi_flash_bank_t *cfi_info = bank->driver_priv;
|
cfi_flash_bank_t *cfi_info = bank->driver_priv;
|
||||||
cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
|
cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
|
||||||
|
|
@ -2070,7 +2070,7 @@ void cfi_fixup_atmel_reversed_erase_regions(flash_bank_t *bank, void *param)
|
||||||
pri_ext->_reversed_geometry = 1;
|
pri_ext->_reversed_geometry = 1;
|
||||||
}
|
}
|
||||||
|
|
||||||
void cfi_fixup_0002_erase_regions(flash_bank_t *bank, void *param)
|
static void cfi_fixup_0002_erase_regions(flash_bank_t *bank, void *param)
|
||||||
{
|
{
|
||||||
int i;
|
int i;
|
||||||
cfi_flash_bank_t *cfi_info = bank->driver_priv;
|
cfi_flash_bank_t *cfi_info = bank->driver_priv;
|
||||||
|
|
@ -2092,7 +2092,7 @@ void cfi_fixup_0002_erase_regions(flash_bank_t *bank, void *param)
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
void cfi_fixup_0002_unlock_addresses(flash_bank_t *bank, void *param)
|
static void cfi_fixup_0002_unlock_addresses(flash_bank_t *bank, void *param)
|
||||||
{
|
{
|
||||||
cfi_flash_bank_t *cfi_info = bank->driver_priv;
|
cfi_flash_bank_t *cfi_info = bank->driver_priv;
|
||||||
cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
|
cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
|
||||||
|
|
@ -2102,7 +2102,7 @@ void cfi_fixup_0002_unlock_addresses(flash_bank_t *bank, void *param)
|
||||||
pri_ext->_unlock2 = unlock_addresses->unlock2;
|
pri_ext->_unlock2 = unlock_addresses->unlock2;
|
||||||
}
|
}
|
||||||
|
|
||||||
int cfi_probe(struct flash_bank_s *bank)
|
static int cfi_probe(struct flash_bank_s *bank)
|
||||||
{
|
{
|
||||||
cfi_flash_bank_t *cfi_info = bank->driver_priv;
|
cfi_flash_bank_t *cfi_info = bank->driver_priv;
|
||||||
target_t *target = bank->target;
|
target_t *target = bank->target;
|
||||||
|
|
@ -2379,7 +2379,7 @@ int cfi_probe(struct flash_bank_s *bank)
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
int cfi_auto_probe(struct flash_bank_s *bank)
|
static int cfi_auto_probe(struct flash_bank_s *bank)
|
||||||
{
|
{
|
||||||
cfi_flash_bank_t *cfi_info = bank->driver_priv;
|
cfi_flash_bank_t *cfi_info = bank->driver_priv;
|
||||||
if (cfi_info->probed)
|
if (cfi_info->probed)
|
||||||
|
|
@ -2388,7 +2388,7 @@ int cfi_auto_probe(struct flash_bank_s *bank)
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
int cfi_intel_protect_check(struct flash_bank_s *bank)
|
static int cfi_intel_protect_check(struct flash_bank_s *bank)
|
||||||
{
|
{
|
||||||
int retval;
|
int retval;
|
||||||
cfi_flash_bank_t *cfi_info = bank->driver_priv;
|
cfi_flash_bank_t *cfi_info = bank->driver_priv;
|
||||||
|
|
@ -2421,7 +2421,7 @@ int cfi_intel_protect_check(struct flash_bank_s *bank)
|
||||||
return target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
|
return target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
|
||||||
}
|
}
|
||||||
|
|
||||||
int cfi_spansion_protect_check(struct flash_bank_s *bank)
|
static int cfi_spansion_protect_check(struct flash_bank_s *bank)
|
||||||
{
|
{
|
||||||
int retval;
|
int retval;
|
||||||
cfi_flash_bank_t *cfi_info = bank->driver_priv;
|
cfi_flash_bank_t *cfi_info = bank->driver_priv;
|
||||||
|
|
@ -2462,7 +2462,7 @@ int cfi_spansion_protect_check(struct flash_bank_s *bank)
|
||||||
return target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
|
return target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
|
||||||
}
|
}
|
||||||
|
|
||||||
int cfi_protect_check(struct flash_bank_s *bank)
|
static int cfi_protect_check(struct flash_bank_s *bank)
|
||||||
{
|
{
|
||||||
cfi_flash_bank_t *cfi_info = bank->driver_priv;
|
cfi_flash_bank_t *cfi_info = bank->driver_priv;
|
||||||
|
|
||||||
|
|
@ -2492,7 +2492,7 @@ int cfi_protect_check(struct flash_bank_s *bank)
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
int cfi_info(struct flash_bank_s *bank, char *buf, int buf_size)
|
static int cfi_info(struct flash_bank_s *bank, char *buf, int buf_size)
|
||||||
{
|
{
|
||||||
int printed;
|
int printed;
|
||||||
cfi_flash_bank_t *cfi_info = bank->driver_priv;
|
cfi_flash_bank_t *cfi_info = bank->driver_priv;
|
||||||
|
|
|
||||||
|
|
@ -36,19 +36,21 @@
|
||||||
#include "../target/embeddedice.h"
|
#include "../target/embeddedice.h"
|
||||||
#include "types.h"
|
#include "types.h"
|
||||||
|
|
||||||
int ecosflash_register_commands(struct command_context_s *cmd_ctx);
|
static int ecosflash_register_commands(struct command_context_s *cmd_ctx);
|
||||||
int ecosflash_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank);
|
static int ecosflash_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank);
|
||||||
int ecosflash_erase(struct flash_bank_s *bank, int first, int last);
|
static int ecosflash_erase(struct flash_bank_s *bank, int first, int last);
|
||||||
int ecosflash_protect(struct flash_bank_s *bank, int set, int first, int last);
|
static int ecosflash_protect(struct flash_bank_s *bank, int set, int first, int last);
|
||||||
int ecosflash_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count);
|
static int ecosflash_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count);
|
||||||
int ecosflash_probe(struct flash_bank_s *bank);
|
static int ecosflash_probe(struct flash_bank_s *bank);
|
||||||
int ecosflash_protect_check(struct flash_bank_s *bank);
|
static int ecosflash_protect_check(struct flash_bank_s *bank);
|
||||||
int ecosflash_info(struct flash_bank_s *bank, char *buf, int buf_size);
|
static int ecosflash_info(struct flash_bank_s *bank, char *buf, int buf_size);
|
||||||
|
|
||||||
u32 ecosflash_get_flash_status(flash_bank_t *bank);
|
#if 0
|
||||||
void ecosflash_set_flash_mode(flash_bank_t *bank,int mode);
|
static u32 ecosflash_get_flash_status(flash_bank_t *bank);
|
||||||
u32 ecosflash_wait_status_busy(flash_bank_t *bank, u32 waitbits, int timeout);
|
static void ecosflash_set_flash_mode(flash_bank_t *bank,int mode);
|
||||||
int ecosflash_handle_gpnvm_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
|
static u32 ecosflash_wait_status_busy(flash_bank_t *bank, u32 waitbits, int timeout);
|
||||||
|
static int ecosflash_handle_gpnvm_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
|
||||||
|
#endif
|
||||||
|
|
||||||
flash_driver_t ecosflash_flash =
|
flash_driver_t ecosflash_flash =
|
||||||
{
|
{
|
||||||
|
|
@ -136,7 +138,7 @@ flash_errmsg(int err)
|
||||||
|
|
||||||
/* flash bank ecosflash <base> <size> <chip_width> <bus_width> <target#> <driverPath>
|
/* flash bank ecosflash <base> <size> <chip_width> <bus_width> <target#> <driverPath>
|
||||||
*/
|
*/
|
||||||
int ecosflash_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank)
|
static int ecosflash_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank)
|
||||||
{
|
{
|
||||||
ecosflash_flash_bank_t *info;
|
ecosflash_flash_bank_t *info;
|
||||||
|
|
||||||
|
|
@ -181,7 +183,7 @@ int ecosflash_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, c
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
int loadDriver(ecosflash_flash_bank_t *info)
|
static int loadDriver(ecosflash_flash_bank_t *info)
|
||||||
{
|
{
|
||||||
u32 buf_cnt;
|
u32 buf_cnt;
|
||||||
u32 image_size;
|
u32 image_size;
|
||||||
|
|
@ -230,7 +232,7 @@ static int const OFFSET_FLASH_SIZE=0x8;
|
||||||
static int const OFFSET_GET_WORKAREA=0x18;
|
static int const OFFSET_GET_WORKAREA=0x18;
|
||||||
static int const OFFSET_GET_WORKAREA_SIZE=0x4;
|
static int const OFFSET_GET_WORKAREA_SIZE=0x4;
|
||||||
|
|
||||||
int runCode(ecosflash_flash_bank_t *info,
|
static int runCode(ecosflash_flash_bank_t *info,
|
||||||
u32 codeStart, u32 codeStop, u32 r0, u32 r1, u32 r2,
|
u32 codeStart, u32 codeStop, u32 r0, u32 r1, u32 r2,
|
||||||
u32 *result,
|
u32 *result,
|
||||||
/* timeout in ms */
|
/* timeout in ms */
|
||||||
|
|
@ -271,7 +273,7 @@ int runCode(ecosflash_flash_bank_t *info,
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
int eCosBoard_erase(ecosflash_flash_bank_t *info, u32 address, u32 len)
|
static int eCosBoard_erase(ecosflash_flash_bank_t *info, u32 address, u32 len)
|
||||||
{
|
{
|
||||||
int retval;
|
int retval;
|
||||||
int timeout = (len / 20480 + 1) * 1000; /*asume 20 KB/s*/
|
int timeout = (len / 20480 + 1) * 1000; /*asume 20 KB/s*/
|
||||||
|
|
@ -302,7 +304,7 @@ int eCosBoard_erase(ecosflash_flash_bank_t *info, u32 address, u32 len)
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
int eCosBoard_flash(ecosflash_flash_bank_t *info, void *data, u32 address, u32 len)
|
static int eCosBoard_flash(ecosflash_flash_bank_t *info, void *data, u32 address, u32 len)
|
||||||
{
|
{
|
||||||
target_t *target=info->target;
|
target_t *target=info->target;
|
||||||
const int chunk=8192;
|
const int chunk=8192;
|
||||||
|
|
@ -361,12 +363,12 @@ int eCosBoard_flash(ecosflash_flash_bank_t *info, void *data, u32 address, u32 l
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
int ecosflash_probe(struct flash_bank_s *bank)
|
static int ecosflash_probe(struct flash_bank_s *bank)
|
||||||
{
|
{
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
int ecosflash_register_commands(struct command_context_s *cmd_ctx)
|
static int ecosflash_register_commands(struct command_context_s *cmd_ctx)
|
||||||
{
|
{
|
||||||
register_command(cmd_ctx, NULL, "ecosflash", NULL, COMMAND_ANY, NULL);
|
register_command(cmd_ctx, NULL, "ecosflash", NULL, COMMAND_ANY, NULL);
|
||||||
|
|
||||||
|
|
@ -396,7 +398,8 @@ static void command(flash_bank_t *bank, u8 cmd, u8 *cmd_buf)
|
||||||
}
|
}
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
u32 ecosflash_address(struct flash_bank_s *bank, u32 address)
|
#if 0
|
||||||
|
static u32 ecosflash_address(struct flash_bank_s *bank, u32 address)
|
||||||
{
|
{
|
||||||
u32 retval = 0;
|
u32 retval = 0;
|
||||||
switch(bank->bus_width)
|
switch(bank->bus_width)
|
||||||
|
|
@ -411,54 +414,57 @@ u32 ecosflash_address(struct flash_bank_s *bank, u32 address)
|
||||||
|
|
||||||
return retval + bank->base;
|
return retval + bank->base;
|
||||||
}
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
int ecosflash_erase(struct flash_bank_s *bank, int first, int last)
|
static int ecosflash_erase(struct flash_bank_s *bank, int first, int last)
|
||||||
{
|
{
|
||||||
struct flash_bank_s *c=bank;
|
struct flash_bank_s *c=bank;
|
||||||
ecosflash_flash_bank_t *info = bank->driver_priv;
|
ecosflash_flash_bank_t *info = bank->driver_priv;
|
||||||
return eCosBoard_erase(info, c->base+first*sectorSize, sectorSize*(last-first+1));
|
return eCosBoard_erase(info, c->base+first*sectorSize, sectorSize*(last-first+1));
|
||||||
}
|
}
|
||||||
|
|
||||||
int ecosflash_protect(struct flash_bank_s *bank, int set, int first, int last)
|
static int ecosflash_protect(struct flash_bank_s *bank, int set, int first, int last)
|
||||||
{
|
{
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
int ecosflash_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
|
static int ecosflash_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
|
||||||
{
|
{
|
||||||
ecosflash_flash_bank_t *info = bank->driver_priv;
|
ecosflash_flash_bank_t *info = bank->driver_priv;
|
||||||
struct flash_bank_s *c=bank;
|
struct flash_bank_s *c=bank;
|
||||||
return eCosBoard_flash(info, buffer, c->base+offset, count);
|
return eCosBoard_flash(info, buffer, c->base+offset, count);
|
||||||
}
|
}
|
||||||
|
|
||||||
int ecosflash_protect_check(struct flash_bank_s *bank)
|
static int ecosflash_protect_check(struct flash_bank_s *bank)
|
||||||
{
|
{
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
int ecosflash_info(struct flash_bank_s *bank, char *buf, int buf_size)
|
static int ecosflash_info(struct flash_bank_s *bank, char *buf, int buf_size)
|
||||||
{
|
{
|
||||||
ecosflash_flash_bank_t *info = bank->driver_priv;
|
ecosflash_flash_bank_t *info = bank->driver_priv;
|
||||||
snprintf(buf, buf_size, "eCos flash driver: %s", info->driverPath);
|
snprintf(buf, buf_size, "eCos flash driver: %s", info->driverPath);
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
u32 ecosflash_get_flash_status(flash_bank_t *bank)
|
#if 0
|
||||||
|
static u32 ecosflash_get_flash_status(flash_bank_t *bank)
|
||||||
{
|
{
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
void ecosflash_set_flash_mode(flash_bank_t *bank,int mode)
|
static void ecosflash_set_flash_mode(flash_bank_t *bank,int mode)
|
||||||
{
|
{
|
||||||
|
|
||||||
}
|
}
|
||||||
|
|
||||||
u32 ecosflash_wait_status_busy(flash_bank_t *bank, u32 waitbits, int timeout)
|
static u32 ecosflash_wait_status_busy(flash_bank_t *bank, u32 waitbits, int timeout)
|
||||||
{
|
{
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
int ecosflash_handle_gpnvm_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
|
static int ecosflash_handle_gpnvm_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
|
||||||
{
|
{
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
#endif
|
||||||
|
|
|
||||||
|
|
@ -48,19 +48,17 @@
|
||||||
#include <inttypes.h>
|
#include <inttypes.h>
|
||||||
|
|
||||||
/* command handlers */
|
/* command handlers */
|
||||||
int handle_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
|
static int handle_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
|
||||||
int handle_flash_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
|
static int handle_flash_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
|
||||||
int handle_flash_probe_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
|
static int handle_flash_probe_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
|
||||||
int handle_flash_erase_check_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
|
static int handle_flash_erase_check_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
|
||||||
int handle_flash_erase_address_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
|
static int handle_flash_erase_address_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
|
||||||
int handle_flash_protect_check_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
|
static int handle_flash_protect_check_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
|
||||||
int handle_flash_erase_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
|
static int handle_flash_erase_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
|
||||||
int handle_flash_write_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
|
static int handle_flash_write_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
|
||||||
int handle_flash_write_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
|
static int handle_flash_write_image_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
|
||||||
int handle_flash_write_image_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
|
static int handle_flash_fill_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
|
||||||
int handle_flash_fill_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
|
static int handle_flash_protect_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
|
||||||
int handle_flash_protect_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
|
|
||||||
flash_bank_t *get_flash_bank_by_addr(target_t *target, u32 addr);
|
|
||||||
|
|
||||||
/* flash drivers
|
/* flash drivers
|
||||||
*/
|
*/
|
||||||
|
|
@ -265,7 +263,7 @@ flash_bank_t *get_flash_bank_by_num(int num)
|
||||||
return p;
|
return p;
|
||||||
}
|
}
|
||||||
|
|
||||||
int handle_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
|
static int handle_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
|
||||||
{
|
{
|
||||||
int retval;
|
int retval;
|
||||||
int i;
|
int i;
|
||||||
|
|
@ -345,7 +343,7 @@ int handle_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
int handle_flash_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
|
static int handle_flash_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
|
||||||
{
|
{
|
||||||
flash_bank_t *p;
|
flash_bank_t *p;
|
||||||
int i = 0;
|
int i = 0;
|
||||||
|
|
@ -396,7 +394,7 @@ int handle_flash_info_command(struct command_context_s *cmd_ctx, char *cmd, char
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
int handle_flash_probe_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
|
static int handle_flash_probe_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
|
||||||
{
|
{
|
||||||
flash_bank_t *p;
|
flash_bank_t *p;
|
||||||
int retval;
|
int retval;
|
||||||
|
|
@ -432,7 +430,7 @@ int handle_flash_probe_command(struct command_context_s *cmd_ctx, char *cmd, cha
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
int handle_flash_erase_check_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
|
static int handle_flash_erase_check_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
|
||||||
{
|
{
|
||||||
flash_bank_t *p;
|
flash_bank_t *p;
|
||||||
int retval;
|
int retval;
|
||||||
|
|
@ -476,7 +474,7 @@ int handle_flash_erase_check_command(struct command_context_s *cmd_ctx, char *cm
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
int handle_flash_erase_address_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
|
static int handle_flash_erase_address_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
|
||||||
{
|
{
|
||||||
flash_bank_t *p;
|
flash_bank_t *p;
|
||||||
int retval;
|
int retval;
|
||||||
|
|
@ -524,7 +522,7 @@ int handle_flash_erase_address_command(struct command_context_s *cmd_ctx, char *
|
||||||
return retval;
|
return retval;
|
||||||
}
|
}
|
||||||
|
|
||||||
int handle_flash_protect_check_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
|
static int handle_flash_protect_check_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
|
||||||
{
|
{
|
||||||
flash_bank_t *p;
|
flash_bank_t *p;
|
||||||
int retval;
|
int retval;
|
||||||
|
|
@ -558,7 +556,7 @@ int handle_flash_protect_check_command(struct command_context_s *cmd_ctx, char *
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
int handle_flash_erase_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
|
static int handle_flash_erase_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
|
||||||
{
|
{
|
||||||
if (argc > 2)
|
if (argc > 2)
|
||||||
{
|
{
|
||||||
|
|
@ -595,7 +593,7 @@ int handle_flash_erase_command(struct command_context_s *cmd_ctx, char *cmd, cha
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
int handle_flash_protect_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
|
static int handle_flash_protect_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
|
||||||
{
|
{
|
||||||
if (argc > 3)
|
if (argc > 3)
|
||||||
{
|
{
|
||||||
|
|
@ -634,7 +632,7 @@ int handle_flash_protect_command(struct command_context_s *cmd_ctx, char *cmd, c
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
int handle_flash_write_image_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
|
static int handle_flash_write_image_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
|
||||||
{
|
{
|
||||||
target_t *target = get_current_target(cmd_ctx);
|
target_t *target = get_current_target(cmd_ctx);
|
||||||
|
|
||||||
|
|
@ -719,7 +717,7 @@ int handle_flash_write_image_command(struct command_context_s *cmd_ctx, char *cm
|
||||||
return retval;
|
return retval;
|
||||||
}
|
}
|
||||||
|
|
||||||
int handle_flash_fill_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
|
static int handle_flash_fill_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
|
||||||
{
|
{
|
||||||
int err = ERROR_OK, retval;
|
int err = ERROR_OK, retval;
|
||||||
u32 address;
|
u32 address;
|
||||||
|
|
@ -819,7 +817,7 @@ int handle_flash_fill_command(struct command_context_s *cmd_ctx, char *cmd, char
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
int handle_flash_write_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
|
static int handle_flash_write_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
|
||||||
{
|
{
|
||||||
u32 offset;
|
u32 offset;
|
||||||
u8 *buffer;
|
u8 *buffer;
|
||||||
|
|
|
||||||
|
|
@ -51,17 +51,17 @@
|
||||||
* - 2378
|
* - 2378
|
||||||
*/
|
*/
|
||||||
|
|
||||||
int lpc2000_register_commands(struct command_context_s *cmd_ctx);
|
static int lpc2000_register_commands(struct command_context_s *cmd_ctx);
|
||||||
int lpc2000_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank);
|
static int lpc2000_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank);
|
||||||
int lpc2000_erase(struct flash_bank_s *bank, int first, int last);
|
static int lpc2000_erase(struct flash_bank_s *bank, int first, int last);
|
||||||
int lpc2000_protect(struct flash_bank_s *bank, int set, int first, int last);
|
static int lpc2000_protect(struct flash_bank_s *bank, int set, int first, int last);
|
||||||
int lpc2000_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count);
|
static int lpc2000_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count);
|
||||||
int lpc2000_probe(struct flash_bank_s *bank);
|
static int lpc2000_probe(struct flash_bank_s *bank);
|
||||||
int lpc2000_erase_check(struct flash_bank_s *bank);
|
static int lpc2000_erase_check(struct flash_bank_s *bank);
|
||||||
int lpc2000_protect_check(struct flash_bank_s *bank);
|
static int lpc2000_protect_check(struct flash_bank_s *bank);
|
||||||
int lpc2000_info(struct flash_bank_s *bank, char *buf, int buf_size);
|
static int lpc2000_info(struct flash_bank_s *bank, char *buf, int buf_size);
|
||||||
|
|
||||||
int lpc2000_handle_part_id_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
|
static int lpc2000_handle_part_id_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
|
||||||
|
|
||||||
flash_driver_t lpc2000_flash =
|
flash_driver_t lpc2000_flash =
|
||||||
{
|
{
|
||||||
|
|
@ -78,7 +78,7 @@ flash_driver_t lpc2000_flash =
|
||||||
.info = lpc2000_info
|
.info = lpc2000_info
|
||||||
};
|
};
|
||||||
|
|
||||||
int lpc2000_register_commands(struct command_context_s *cmd_ctx)
|
static int lpc2000_register_commands(struct command_context_s *cmd_ctx)
|
||||||
{
|
{
|
||||||
command_t *lpc2000_cmd = register_command(cmd_ctx, NULL, "lpc2000", NULL, COMMAND_ANY, NULL);
|
command_t *lpc2000_cmd = register_command(cmd_ctx, NULL, "lpc2000", NULL, COMMAND_ANY, NULL);
|
||||||
|
|
||||||
|
|
@ -88,7 +88,7 @@ int lpc2000_register_commands(struct command_context_s *cmd_ctx)
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
int lpc2000_build_sector_list(struct flash_bank_s *bank)
|
static int lpc2000_build_sector_list(struct flash_bank_s *bank)
|
||||||
{
|
{
|
||||||
lpc2000_flash_bank_t *lpc2000_info = bank->driver_priv;
|
lpc2000_flash_bank_t *lpc2000_info = bank->driver_priv;
|
||||||
|
|
||||||
|
|
@ -239,7 +239,7 @@ int lpc2000_build_sector_list(struct flash_bank_s *bank)
|
||||||
* 0x20 to 0x2b: command result table
|
* 0x20 to 0x2b: command result table
|
||||||
* 0x2c to 0xac: stack (only 128b needed)
|
* 0x2c to 0xac: stack (only 128b needed)
|
||||||
*/
|
*/
|
||||||
int lpc2000_iap_call(flash_bank_t *bank, int code, u32 param_table[5], u32 result_table[2])
|
static int lpc2000_iap_call(flash_bank_t *bank, int code, u32 param_table[5], u32 result_table[2])
|
||||||
{
|
{
|
||||||
int retval;
|
int retval;
|
||||||
lpc2000_flash_bank_t *lpc2000_info = bank->driver_priv;
|
lpc2000_flash_bank_t *lpc2000_info = bank->driver_priv;
|
||||||
|
|
@ -322,14 +322,14 @@ int lpc2000_iap_call(flash_bank_t *bank, int code, u32 param_table[5], u32 resul
|
||||||
return status_code;
|
return status_code;
|
||||||
}
|
}
|
||||||
|
|
||||||
int lpc2000_iap_blank_check(struct flash_bank_s *bank, int first, int last)
|
static int lpc2000_iap_blank_check(struct flash_bank_s *bank, int first, int last)
|
||||||
{
|
{
|
||||||
u32 param_table[5];
|
u32 param_table[5];
|
||||||
u32 result_table[2];
|
u32 result_table[2];
|
||||||
int status_code;
|
int status_code;
|
||||||
int i;
|
int i;
|
||||||
|
|
||||||
if ((first < 0) || (last > bank->num_sectors))
|
if ((first < 0) || (last >= bank->num_sectors))
|
||||||
return ERROR_FLASH_SECTOR_INVALID;
|
return ERROR_FLASH_SECTOR_INVALID;
|
||||||
|
|
||||||
for (i = first; i <= last; i++)
|
for (i = first; i <= last; i++)
|
||||||
|
|
@ -365,7 +365,7 @@ int lpc2000_iap_blank_check(struct flash_bank_s *bank, int first, int last)
|
||||||
|
|
||||||
/* flash bank lpc2000 <base> <size> 0 0 <target#> <lpc_variant> <cclk> [calc_checksum]
|
/* flash bank lpc2000 <base> <size> 0 0 <target#> <lpc_variant> <cclk> [calc_checksum]
|
||||||
*/
|
*/
|
||||||
int lpc2000_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank)
|
static int lpc2000_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank)
|
||||||
{
|
{
|
||||||
lpc2000_flash_bank_t *lpc2000_info;
|
lpc2000_flash_bank_t *lpc2000_info;
|
||||||
|
|
||||||
|
|
@ -413,7 +413,7 @@ int lpc2000_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, cha
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
int lpc2000_erase(struct flash_bank_s *bank, int first, int last)
|
static int lpc2000_erase(struct flash_bank_s *bank, int first, int last)
|
||||||
{
|
{
|
||||||
lpc2000_flash_bank_t *lpc2000_info = bank->driver_priv;
|
lpc2000_flash_bank_t *lpc2000_info = bank->driver_priv;
|
||||||
u32 param_table[5];
|
u32 param_table[5];
|
||||||
|
|
@ -465,13 +465,13 @@ int lpc2000_erase(struct flash_bank_s *bank, int first, int last)
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
int lpc2000_protect(struct flash_bank_s *bank, int set, int first, int last)
|
static int lpc2000_protect(struct flash_bank_s *bank, int set, int first, int last)
|
||||||
{
|
{
|
||||||
/* can't protect/unprotect on the lpc2000 */
|
/* can't protect/unprotect on the lpc2000 */
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
int lpc2000_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
|
static int lpc2000_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
|
||||||
{
|
{
|
||||||
lpc2000_flash_bank_t *lpc2000_info = bank->driver_priv;
|
lpc2000_flash_bank_t *lpc2000_info = bank->driver_priv;
|
||||||
target_t *target = bank->target;
|
target_t *target = bank->target;
|
||||||
|
|
@ -635,7 +635,7 @@ int lpc2000_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
|
||||||
return retval;
|
return retval;
|
||||||
}
|
}
|
||||||
|
|
||||||
int lpc2000_probe(struct flash_bank_s *bank)
|
static int lpc2000_probe(struct flash_bank_s *bank)
|
||||||
{
|
{
|
||||||
/* we can't probe on an lpc2000
|
/* we can't probe on an lpc2000
|
||||||
* if this is an lpc2xxx, it has the configured flash
|
* if this is an lpc2xxx, it has the configured flash
|
||||||
|
|
@ -643,7 +643,7 @@ int lpc2000_probe(struct flash_bank_s *bank)
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
int lpc2000_erase_check(struct flash_bank_s *bank)
|
static int lpc2000_erase_check(struct flash_bank_s *bank)
|
||||||
{
|
{
|
||||||
if (bank->target->state != TARGET_HALTED)
|
if (bank->target->state != TARGET_HALTED)
|
||||||
{
|
{
|
||||||
|
|
@ -654,13 +654,13 @@ int lpc2000_erase_check(struct flash_bank_s *bank)
|
||||||
return lpc2000_iap_blank_check(bank, 0, bank->num_sectors - 1);
|
return lpc2000_iap_blank_check(bank, 0, bank->num_sectors - 1);
|
||||||
}
|
}
|
||||||
|
|
||||||
int lpc2000_protect_check(struct flash_bank_s *bank)
|
static int lpc2000_protect_check(struct flash_bank_s *bank)
|
||||||
{
|
{
|
||||||
/* sectors are always protected */
|
/* sectors are always protected */
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
int lpc2000_info(struct flash_bank_s *bank, char *buf, int buf_size)
|
static int lpc2000_info(struct flash_bank_s *bank, char *buf, int buf_size)
|
||||||
{
|
{
|
||||||
lpc2000_flash_bank_t *lpc2000_info = bank->driver_priv;
|
lpc2000_flash_bank_t *lpc2000_info = bank->driver_priv;
|
||||||
|
|
||||||
|
|
@ -669,7 +669,7 @@ int lpc2000_info(struct flash_bank_s *bank, char *buf, int buf_size)
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
int lpc2000_handle_part_id_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
|
static int lpc2000_handle_part_id_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
|
||||||
{
|
{
|
||||||
flash_bank_t *bank;
|
flash_bank_t *bank;
|
||||||
u32 param_table[5];
|
u32 param_table[5];
|
||||||
|
|
|
||||||
|
|
@ -94,22 +94,19 @@
|
||||||
/* F_CLK_TIME */
|
/* F_CLK_TIME */
|
||||||
#define FCT_CLK_DIV_MASK 0x0FFF
|
#define FCT_CLK_DIV_MASK 0x0FFF
|
||||||
|
|
||||||
int lpc288x_register_commands(struct command_context_s *cmd_ctx);
|
static int lpc288x_register_commands(struct command_context_s *cmd_ctx);
|
||||||
int lpc288x_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank);
|
static int lpc288x_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank);
|
||||||
int lpc288x_erase(struct flash_bank_s *bank, int first, int last);
|
static int lpc288x_erase(struct flash_bank_s *bank, int first, int last);
|
||||||
int lpc288x_protect(struct flash_bank_s *bank, int set, int first, int last);
|
static int lpc288x_protect(struct flash_bank_s *bank, int set, int first, int last);
|
||||||
int lpc288x_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count);
|
static int lpc288x_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count);
|
||||||
int lpc288x_probe(struct flash_bank_s *bank);
|
static int lpc288x_probe(struct flash_bank_s *bank);
|
||||||
int lpc288x_auto_probe(struct flash_bank_s *bank);
|
static int lpc288x_erase_check(struct flash_bank_s *bank);
|
||||||
int lpc288x_erase_check(struct flash_bank_s *bank);
|
static int lpc288x_protect_check(struct flash_bank_s *bank);
|
||||||
int lpc288x_protect_check(struct flash_bank_s *bank);
|
static int lpc288x_info(struct flash_bank_s *bank, char *buf, int buf_size);
|
||||||
int lpc288x_info(struct flash_bank_s *bank, char *buf, int buf_size);
|
static u32 lpc288x_wait_status_busy(flash_bank_t *bank, int timeout);
|
||||||
void lpc288x_set_flash_mode(flash_bank_t *bank, u8 flashplane, int mode);
|
static void lpc288x_load_timer(int erase, struct target_s *target);
|
||||||
u32 lpc288x_wait_status_busy(flash_bank_t *bank, int timeout);
|
static void lpc288x_set_flash_clk(struct flash_bank_s *bank);
|
||||||
void lpc288x_load_timer(int erase, struct target_s *target);
|
static u32 lpc288x_system_ready(struct flash_bank_s *bank);
|
||||||
void lpc288x_set_flash_clk(struct flash_bank_s *bank);
|
|
||||||
u32 lpc288x_system_ready(struct flash_bank_s *bank);
|
|
||||||
int lpc288x_handle_part_id_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
|
|
||||||
|
|
||||||
flash_driver_t lpc288x_flash =
|
flash_driver_t lpc288x_flash =
|
||||||
{
|
{
|
||||||
|
|
@ -126,12 +123,12 @@ flash_driver_t lpc288x_flash =
|
||||||
.info = lpc288x_info
|
.info = lpc288x_info
|
||||||
};
|
};
|
||||||
|
|
||||||
int lpc288x_register_commands(struct command_context_s *cmd_ctx)
|
static int lpc288x_register_commands(struct command_context_s *cmd_ctx)
|
||||||
{
|
{
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
u32 lpc288x_wait_status_busy(flash_bank_t *bank, int timeout)
|
static u32 lpc288x_wait_status_busy(flash_bank_t *bank, int timeout)
|
||||||
{
|
{
|
||||||
u32 status;
|
u32 status;
|
||||||
target_t *target = bank->target;
|
target_t *target = bank->target;
|
||||||
|
|
@ -151,7 +148,7 @@ u32 lpc288x_wait_status_busy(flash_bank_t *bank, int timeout)
|
||||||
}
|
}
|
||||||
|
|
||||||
/* Read device id register and fill in driver info structure */
|
/* Read device id register and fill in driver info structure */
|
||||||
int lpc288x_read_part_info(struct flash_bank_s *bank)
|
static int lpc288x_read_part_info(struct flash_bank_s *bank)
|
||||||
{
|
{
|
||||||
lpc288x_flash_bank_t *lpc288x_info = bank->driver_priv;
|
lpc288x_flash_bank_t *lpc288x_info = bank->driver_priv;
|
||||||
target_t *target = bank->target;
|
target_t *target = bank->target;
|
||||||
|
|
@ -201,13 +198,13 @@ int lpc288x_read_part_info(struct flash_bank_s *bank)
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
int lpc288x_protect_check(struct flash_bank_s *bank)
|
static int lpc288x_protect_check(struct flash_bank_s *bank)
|
||||||
{
|
{
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
/* flash_bank LPC288x 0 0 0 0 <target#> <cclk> */
|
/* flash_bank LPC288x 0 0 0 0 <target#> <cclk> */
|
||||||
int lpc288x_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank)
|
static int lpc288x_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank)
|
||||||
{
|
{
|
||||||
lpc288x_flash_bank_t *lpc288x_info;
|
lpc288x_flash_bank_t *lpc288x_info;
|
||||||
|
|
||||||
|
|
@ -232,7 +229,7 @@ int lpc288x_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, cha
|
||||||
* AHB = 12 MHz ?
|
* AHB = 12 MHz ?
|
||||||
* 12000000/66000 = 182
|
* 12000000/66000 = 182
|
||||||
* CLK_DIV = 60 ? */
|
* CLK_DIV = 60 ? */
|
||||||
void lpc288x_set_flash_clk(struct flash_bank_s *bank)
|
static void lpc288x_set_flash_clk(struct flash_bank_s *bank)
|
||||||
{
|
{
|
||||||
u32 clk_time;
|
u32 clk_time;
|
||||||
lpc288x_flash_bank_t *lpc288x_info = bank->driver_priv;
|
lpc288x_flash_bank_t *lpc288x_info = bank->driver_priv;
|
||||||
|
|
@ -247,7 +244,7 @@ void lpc288x_set_flash_clk(struct flash_bank_s *bank)
|
||||||
* LOAD_TIMER_WRITE FPT_TIME = ((1,000,000 / AHB tcyc (in ns)) - 2) / 512
|
* LOAD_TIMER_WRITE FPT_TIME = ((1,000,000 / AHB tcyc (in ns)) - 2) / 512
|
||||||
* = 23 (75) (AN10548 72 - is this wrong?)
|
* = 23 (75) (AN10548 72 - is this wrong?)
|
||||||
* TODO: Sort out timing calcs ;) */
|
* TODO: Sort out timing calcs ;) */
|
||||||
void lpc288x_load_timer(int erase, struct target_s *target)
|
static void lpc288x_load_timer(int erase, struct target_s *target)
|
||||||
{
|
{
|
||||||
if (erase == LOAD_TIMER_ERASE)
|
if (erase == LOAD_TIMER_ERASE)
|
||||||
{
|
{
|
||||||
|
|
@ -259,7 +256,7 @@ void lpc288x_load_timer(int erase, struct target_s *target)
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
u32 lpc288x_system_ready(struct flash_bank_s *bank)
|
static u32 lpc288x_system_ready(struct flash_bank_s *bank)
|
||||||
{
|
{
|
||||||
lpc288x_flash_bank_t *lpc288x_info = bank->driver_priv;
|
lpc288x_flash_bank_t *lpc288x_info = bank->driver_priv;
|
||||||
if (lpc288x_info->cidr == 0)
|
if (lpc288x_info->cidr == 0)
|
||||||
|
|
@ -275,7 +272,7 @@ u32 lpc288x_system_ready(struct flash_bank_s *bank)
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
int lpc288x_erase_check(struct flash_bank_s *bank)
|
static int lpc288x_erase_check(struct flash_bank_s *bank)
|
||||||
{
|
{
|
||||||
u32 status = lpc288x_system_ready(bank); /* probed? halted? */
|
u32 status = lpc288x_system_ready(bank); /* probed? halted? */
|
||||||
if (status != ERROR_OK)
|
if (status != ERROR_OK)
|
||||||
|
|
@ -287,7 +284,7 @@ int lpc288x_erase_check(struct flash_bank_s *bank)
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
int lpc288x_erase(struct flash_bank_s *bank, int first, int last)
|
static int lpc288x_erase(struct flash_bank_s *bank, int first, int last)
|
||||||
{
|
{
|
||||||
u32 status;
|
u32 status;
|
||||||
int sector;
|
int sector;
|
||||||
|
|
@ -328,7 +325,7 @@ int lpc288x_erase(struct flash_bank_s *bank, int first, int last)
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
int lpc288x_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
|
static int lpc288x_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
|
||||||
{
|
{
|
||||||
u8 page_buffer[FLASH_PAGE_SIZE];
|
u8 page_buffer[FLASH_PAGE_SIZE];
|
||||||
u32 i, status, source_offset,dest_offset;
|
u32 i, status, source_offset,dest_offset;
|
||||||
|
|
@ -443,7 +440,7 @@ int lpc288x_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
int lpc288x_probe(struct flash_bank_s *bank)
|
static int lpc288x_probe(struct flash_bank_s *bank)
|
||||||
{
|
{
|
||||||
/* we only deal with LPC2888 so flash config is fixed */
|
/* we only deal with LPC2888 so flash config is fixed */
|
||||||
lpc288x_flash_bank_t *lpc288x_info = bank->driver_priv;
|
lpc288x_flash_bank_t *lpc288x_info = bank->driver_priv;
|
||||||
|
|
@ -466,13 +463,13 @@ int lpc288x_probe(struct flash_bank_s *bank)
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
int lpc288x_info(struct flash_bank_s *bank, char *buf, int buf_size)
|
static int lpc288x_info(struct flash_bank_s *bank, char *buf, int buf_size)
|
||||||
{
|
{
|
||||||
snprintf(buf, buf_size, "lpc288x flash driver");
|
snprintf(buf, buf_size, "lpc288x flash driver");
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
int lpc288x_protect(struct flash_bank_s *bank, int set, int first, int last)
|
static int lpc288x_protect(struct flash_bank_s *bank, int set, int first, int last)
|
||||||
{
|
{
|
||||||
int lockregion, status;
|
int lockregion, status;
|
||||||
u32 value;
|
u32 value;
|
||||||
|
|
|
||||||
|
|
@ -32,20 +32,20 @@
|
||||||
#include "nand.h"
|
#include "nand.h"
|
||||||
#include "target.h"
|
#include "target.h"
|
||||||
|
|
||||||
int lpc3180_nand_device_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct nand_device_s *device);
|
static int lpc3180_nand_device_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct nand_device_s *device);
|
||||||
int lpc3180_register_commands(struct command_context_s *cmd_ctx);
|
static int lpc3180_register_commands(struct command_context_s *cmd_ctx);
|
||||||
int lpc3180_init(struct nand_device_s *device);
|
static int lpc3180_init(struct nand_device_s *device);
|
||||||
int lpc3180_reset(struct nand_device_s *device);
|
static int lpc3180_reset(struct nand_device_s *device);
|
||||||
int lpc3180_command(struct nand_device_s *device, u8 command);
|
static int lpc3180_command(struct nand_device_s *device, u8 command);
|
||||||
int lpc3180_address(struct nand_device_s *device, u8 address);
|
static int lpc3180_address(struct nand_device_s *device, u8 address);
|
||||||
int lpc3180_write_data(struct nand_device_s *device, u16 data);
|
static int lpc3180_write_data(struct nand_device_s *device, u16 data);
|
||||||
int lpc3180_read_data(struct nand_device_s *device, void *data);
|
static int lpc3180_read_data(struct nand_device_s *device, void *data);
|
||||||
int lpc3180_write_page(struct nand_device_s *device, u32 page, u8 *data, u32 data_size, u8 *oob, u32 oob_size);
|
static int lpc3180_write_page(struct nand_device_s *device, u32 page, u8 *data, u32 data_size, u8 *oob, u32 oob_size);
|
||||||
int lpc3180_read_page(struct nand_device_s *device, u32 page, u8 *data, u32 data_size, u8 *oob, u32 oob_size);
|
static int lpc3180_read_page(struct nand_device_s *device, u32 page, u8 *data, u32 data_size, u8 *oob, u32 oob_size);
|
||||||
int lpc3180_controller_ready(struct nand_device_s *device, int timeout);
|
static int lpc3180_controller_ready(struct nand_device_s *device, int timeout);
|
||||||
int lpc3180_nand_ready(struct nand_device_s *device, int timeout);
|
static int lpc3180_nand_ready(struct nand_device_s *device, int timeout);
|
||||||
|
|
||||||
int handle_lpc3180_select_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
|
static int handle_lpc3180_select_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
|
||||||
|
|
||||||
nand_flash_controller_t lpc3180_nand_controller =
|
nand_flash_controller_t lpc3180_nand_controller =
|
||||||
{
|
{
|
||||||
|
|
@ -66,7 +66,7 @@ nand_flash_controller_t lpc3180_nand_controller =
|
||||||
|
|
||||||
/* nand device lpc3180 <target#> <oscillator_frequency>
|
/* nand device lpc3180 <target#> <oscillator_frequency>
|
||||||
*/
|
*/
|
||||||
int lpc3180_nand_device_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct nand_device_s *device)
|
static int lpc3180_nand_device_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct nand_device_s *device)
|
||||||
{
|
{
|
||||||
lpc3180_nand_controller_t *lpc3180_info;
|
lpc3180_nand_controller_t *lpc3180_info;
|
||||||
|
|
||||||
|
|
@ -99,7 +99,7 @@ int lpc3180_nand_device_command(struct command_context_s *cmd_ctx, char *cmd, ch
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
int lpc3180_register_commands(struct command_context_s *cmd_ctx)
|
static int lpc3180_register_commands(struct command_context_s *cmd_ctx)
|
||||||
{
|
{
|
||||||
command_t *lpc3180_cmd = register_command(cmd_ctx, NULL, "lpc3180", NULL, COMMAND_ANY, "commands specific to the LPC3180 NAND flash controllers");
|
command_t *lpc3180_cmd = register_command(cmd_ctx, NULL, "lpc3180", NULL, COMMAND_ANY, "commands specific to the LPC3180 NAND flash controllers");
|
||||||
|
|
||||||
|
|
@ -108,7 +108,7 @@ int lpc3180_register_commands(struct command_context_s *cmd_ctx)
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
int lpc3180_pll(int fclkin, u32 pll_ctrl)
|
static int lpc3180_pll(int fclkin, u32 pll_ctrl)
|
||||||
{
|
{
|
||||||
int bypass = (pll_ctrl & 0x8000) >> 15;
|
int bypass = (pll_ctrl & 0x8000) >> 15;
|
||||||
int direct = (pll_ctrl & 0x4000) >> 14;
|
int direct = (pll_ctrl & 0x4000) >> 14;
|
||||||
|
|
@ -136,7 +136,7 @@ int lpc3180_pll(int fclkin, u32 pll_ctrl)
|
||||||
return (m / (2 * p)) * (fclkin / n);
|
return (m / (2 * p)) * (fclkin / n);
|
||||||
}
|
}
|
||||||
|
|
||||||
float lpc3180_cycle_time(lpc3180_nand_controller_t *lpc3180_info)
|
static float lpc3180_cycle_time(lpc3180_nand_controller_t *lpc3180_info)
|
||||||
{
|
{
|
||||||
target_t *target = lpc3180_info->target;
|
target_t *target = lpc3180_info->target;
|
||||||
u32 sysclk_ctrl, pwr_ctrl, hclkdiv_ctrl, hclkpll_ctrl;
|
u32 sysclk_ctrl, pwr_ctrl, hclkdiv_ctrl, hclkpll_ctrl;
|
||||||
|
|
@ -186,7 +186,7 @@ float lpc3180_cycle_time(lpc3180_nand_controller_t *lpc3180_info)
|
||||||
return cycle;
|
return cycle;
|
||||||
}
|
}
|
||||||
|
|
||||||
int lpc3180_init(struct nand_device_s *device)
|
static int lpc3180_init(struct nand_device_s *device)
|
||||||
{
|
{
|
||||||
lpc3180_nand_controller_t *lpc3180_info = device->controller_priv;
|
lpc3180_nand_controller_t *lpc3180_info = device->controller_priv;
|
||||||
target_t *target = lpc3180_info->target;
|
target_t *target = lpc3180_info->target;
|
||||||
|
|
@ -316,7 +316,7 @@ int lpc3180_init(struct nand_device_s *device)
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
int lpc3180_reset(struct nand_device_s *device)
|
static int lpc3180_reset(struct nand_device_s *device)
|
||||||
{
|
{
|
||||||
lpc3180_nand_controller_t *lpc3180_info = device->controller_priv;
|
lpc3180_nand_controller_t *lpc3180_info = device->controller_priv;
|
||||||
target_t *target = lpc3180_info->target;
|
target_t *target = lpc3180_info->target;
|
||||||
|
|
@ -358,7 +358,7 @@ int lpc3180_reset(struct nand_device_s *device)
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
int lpc3180_command(struct nand_device_s *device, u8 command)
|
static int lpc3180_command(struct nand_device_s *device, u8 command)
|
||||||
{
|
{
|
||||||
lpc3180_nand_controller_t *lpc3180_info = device->controller_priv;
|
lpc3180_nand_controller_t *lpc3180_info = device->controller_priv;
|
||||||
target_t *target = lpc3180_info->target;
|
target_t *target = lpc3180_info->target;
|
||||||
|
|
@ -388,7 +388,7 @@ int lpc3180_command(struct nand_device_s *device, u8 command)
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
int lpc3180_address(struct nand_device_s *device, u8 address)
|
static int lpc3180_address(struct nand_device_s *device, u8 address)
|
||||||
{
|
{
|
||||||
lpc3180_nand_controller_t *lpc3180_info = device->controller_priv;
|
lpc3180_nand_controller_t *lpc3180_info = device->controller_priv;
|
||||||
target_t *target = lpc3180_info->target;
|
target_t *target = lpc3180_info->target;
|
||||||
|
|
@ -418,7 +418,7 @@ int lpc3180_address(struct nand_device_s *device, u8 address)
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
int lpc3180_write_data(struct nand_device_s *device, u16 data)
|
static int lpc3180_write_data(struct nand_device_s *device, u16 data)
|
||||||
{
|
{
|
||||||
lpc3180_nand_controller_t *lpc3180_info = device->controller_priv;
|
lpc3180_nand_controller_t *lpc3180_info = device->controller_priv;
|
||||||
target_t *target = lpc3180_info->target;
|
target_t *target = lpc3180_info->target;
|
||||||
|
|
@ -448,7 +448,7 @@ int lpc3180_write_data(struct nand_device_s *device, u16 data)
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
int lpc3180_read_data(struct nand_device_s *device, void *data)
|
static int lpc3180_read_data(struct nand_device_s *device, void *data)
|
||||||
{
|
{
|
||||||
lpc3180_nand_controller_t *lpc3180_info = device->controller_priv;
|
lpc3180_nand_controller_t *lpc3180_info = device->controller_priv;
|
||||||
target_t *target = lpc3180_info->target;
|
target_t *target = lpc3180_info->target;
|
||||||
|
|
@ -510,7 +510,7 @@ int lpc3180_read_data(struct nand_device_s *device, void *data)
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
int lpc3180_write_page(struct nand_device_s *device, u32 page, u8 *data, u32 data_size, u8 *oob, u32 oob_size)
|
static int lpc3180_write_page(struct nand_device_s *device, u32 page, u8 *data, u32 data_size, u8 *oob, u32 oob_size)
|
||||||
{
|
{
|
||||||
lpc3180_nand_controller_t *lpc3180_info = device->controller_priv;
|
lpc3180_nand_controller_t *lpc3180_info = device->controller_priv;
|
||||||
target_t *target = lpc3180_info->target;
|
target_t *target = lpc3180_info->target;
|
||||||
|
|
@ -649,7 +649,7 @@ int lpc3180_write_page(struct nand_device_s *device, u32 page, u8 *data, u32 dat
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
int lpc3180_read_page(struct nand_device_s *device, u32 page, u8 *data, u32 data_size, u8 *oob, u32 oob_size)
|
static int lpc3180_read_page(struct nand_device_s *device, u32 page, u8 *data, u32 data_size, u8 *oob, u32 oob_size)
|
||||||
{
|
{
|
||||||
lpc3180_nand_controller_t *lpc3180_info = device->controller_priv;
|
lpc3180_nand_controller_t *lpc3180_info = device->controller_priv;
|
||||||
target_t *target = lpc3180_info->target;
|
target_t *target = lpc3180_info->target;
|
||||||
|
|
@ -796,7 +796,7 @@ int lpc3180_read_page(struct nand_device_s *device, u32 page, u8 *data, u32 data
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
int lpc3180_controller_ready(struct nand_device_s *device, int timeout)
|
static int lpc3180_controller_ready(struct nand_device_s *device, int timeout)
|
||||||
{
|
{
|
||||||
lpc3180_nand_controller_t *lpc3180_info = device->controller_priv;
|
lpc3180_nand_controller_t *lpc3180_info = device->controller_priv;
|
||||||
target_t *target = lpc3180_info->target;
|
target_t *target = lpc3180_info->target;
|
||||||
|
|
@ -830,7 +830,7 @@ int lpc3180_controller_ready(struct nand_device_s *device, int timeout)
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
int lpc3180_nand_ready(struct nand_device_s *device, int timeout)
|
static int lpc3180_nand_ready(struct nand_device_s *device, int timeout)
|
||||||
{
|
{
|
||||||
lpc3180_nand_controller_t *lpc3180_info = device->controller_priv;
|
lpc3180_nand_controller_t *lpc3180_info = device->controller_priv;
|
||||||
target_t *target = lpc3180_info->target;
|
target_t *target = lpc3180_info->target;
|
||||||
|
|
@ -870,7 +870,7 @@ int lpc3180_nand_ready(struct nand_device_s *device, int timeout)
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
int handle_lpc3180_select_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
|
static int handle_lpc3180_select_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
|
||||||
{
|
{
|
||||||
nand_device_t *device = NULL;
|
nand_device_t *device = NULL;
|
||||||
lpc3180_nand_controller_t *lpc3180_info = NULL;
|
lpc3180_nand_controller_t *lpc3180_info = NULL;
|
||||||
|
|
|
||||||
|
|
@ -39,24 +39,21 @@
|
||||||
#include "fileio.h"
|
#include "fileio.h"
|
||||||
#include "image.h"
|
#include "image.h"
|
||||||
|
|
||||||
int nand_register_commands(struct command_context_s *cmd_ctx);
|
static int handle_nand_list_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
|
||||||
int handle_nand_list_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
|
static int handle_nand_probe_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
|
||||||
int handle_nand_probe_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
|
static int handle_nand_check_bad_blocks_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
|
||||||
int handle_nand_check_bad_blocks_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
|
static int handle_nand_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
|
||||||
int handle_nand_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
|
static int handle_nand_copy_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
|
||||||
int handle_nand_copy_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
|
static int handle_nand_write_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
|
||||||
int handle_nand_write_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
|
static int handle_nand_dump_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
|
||||||
int handle_nand_dump_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
|
static int handle_nand_erase_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
|
||||||
int handle_nand_erase_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
|
|
||||||
|
|
||||||
int handle_nand_raw_access_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
|
static int handle_nand_raw_access_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
|
||||||
|
|
||||||
int nand_read_page_raw(struct nand_device_s *device, u32 page, u8 *data, u32 data_size, u8 *oob, u32 oob_size);
|
static int nand_read_page(struct nand_device_s *device, u32 page, u8 *data, u32 data_size, u8 *oob, u32 oob_size);
|
||||||
int nand_read_page(struct nand_device_s *device, u32 page, u8 *data, u32 data_size, u8 *oob, u32 oob_size);
|
//static int nand_read_plain(struct nand_device_s *device, u32 address, u8 *data, u32 data_size);
|
||||||
int nand_read_plain(struct nand_device_s *device, u32 address, u8 *data, u32 data_size);
|
|
||||||
|
|
||||||
int nand_write_page_raw(struct nand_device_s *device, u32 page, u8 *data, u32 data_size, u8 *oob, u32 oob_size);
|
static int nand_write_page(struct nand_device_s *device, u32 page, u8 *data, u32 data_size, u8 *oob, u32 oob_size);
|
||||||
int nand_write_page(struct nand_device_s *device, u32 page, u8 *data, u32 data_size, u8 *oob, u32 oob_size);
|
|
||||||
|
|
||||||
/* NAND flash controller
|
/* NAND flash controller
|
||||||
*/
|
*/
|
||||||
|
|
@ -69,7 +66,7 @@ extern nand_flash_controller_t s3c2443_nand_controller;
|
||||||
|
|
||||||
/* extern nand_flash_controller_t boundary_scan_nand_controller; */
|
/* extern nand_flash_controller_t boundary_scan_nand_controller; */
|
||||||
|
|
||||||
nand_flash_controller_t *nand_flash_controllers[] =
|
static nand_flash_controller_t *nand_flash_controllers[] =
|
||||||
{
|
{
|
||||||
&lpc3180_nand_controller,
|
&lpc3180_nand_controller,
|
||||||
&orion_nand_controller,
|
&orion_nand_controller,
|
||||||
|
|
@ -82,7 +79,7 @@ nand_flash_controller_t *nand_flash_controllers[] =
|
||||||
};
|
};
|
||||||
|
|
||||||
/* configured NAND devices and NAND Flash command handler */
|
/* configured NAND devices and NAND Flash command handler */
|
||||||
nand_device_t *nand_devices = NULL;
|
static nand_device_t *nand_devices = NULL;
|
||||||
static command_t *nand_cmd;
|
static command_t *nand_cmd;
|
||||||
|
|
||||||
/* Chip ID list
|
/* Chip ID list
|
||||||
|
|
@ -95,7 +92,7 @@ static command_t *nand_cmd;
|
||||||
* 256 256 Byte page size
|
* 256 256 Byte page size
|
||||||
* 512 512 Byte page size
|
* 512 512 Byte page size
|
||||||
*/
|
*/
|
||||||
nand_info_t nand_flash_ids[] =
|
static nand_info_t nand_flash_ids[] =
|
||||||
{
|
{
|
||||||
{"NAND 1MiB 5V 8-bit", 0x6e, 256, 1, 0x1000, 0},
|
{"NAND 1MiB 5V 8-bit", 0x6e, 256, 1, 0x1000, 0},
|
||||||
{"NAND 2MiB 5V 8-bit", 0x64, 256, 2, 0x1000, 0},
|
{"NAND 2MiB 5V 8-bit", 0x64, 256, 2, 0x1000, 0},
|
||||||
|
|
@ -173,7 +170,7 @@ nand_info_t nand_flash_ids[] =
|
||||||
|
|
||||||
/* Manufacturer ID list
|
/* Manufacturer ID list
|
||||||
*/
|
*/
|
||||||
nand_manufacturer_t nand_manuf_ids[] =
|
static nand_manufacturer_t nand_manuf_ids[] =
|
||||||
{
|
{
|
||||||
{0x0, "unknown"},
|
{0x0, "unknown"},
|
||||||
{NAND_MFR_TOSHIBA, "Toshiba"},
|
{NAND_MFR_TOSHIBA, "Toshiba"},
|
||||||
|
|
@ -190,7 +187,8 @@ nand_manufacturer_t nand_manuf_ids[] =
|
||||||
* Define default oob placement schemes for large and small page devices
|
* Define default oob placement schemes for large and small page devices
|
||||||
*/
|
*/
|
||||||
|
|
||||||
nand_ecclayout_t nand_oob_8 = {
|
#if 0
|
||||||
|
static nand_ecclayout_t nand_oob_8 = {
|
||||||
.eccbytes = 3,
|
.eccbytes = 3,
|
||||||
.eccpos = {0, 1, 2},
|
.eccpos = {0, 1, 2},
|
||||||
.oobfree = {
|
.oobfree = {
|
||||||
|
|
@ -199,8 +197,9 @@ nand_ecclayout_t nand_oob_8 = {
|
||||||
{.offset = 6,
|
{.offset = 6,
|
||||||
.length = 2}}
|
.length = 2}}
|
||||||
};
|
};
|
||||||
|
#endif
|
||||||
|
|
||||||
nand_ecclayout_t nand_oob_16 = {
|
static nand_ecclayout_t nand_oob_16 = {
|
||||||
.eccbytes = 6,
|
.eccbytes = 6,
|
||||||
.eccpos = {0, 1, 2, 3, 6, 7},
|
.eccpos = {0, 1, 2, 3, 6, 7},
|
||||||
.oobfree = {
|
.oobfree = {
|
||||||
|
|
@ -208,7 +207,7 @@ nand_ecclayout_t nand_oob_16 = {
|
||||||
. length = 8}}
|
. length = 8}}
|
||||||
};
|
};
|
||||||
|
|
||||||
nand_ecclayout_t nand_oob_64 = {
|
static nand_ecclayout_t nand_oob_64 = {
|
||||||
.eccbytes = 24,
|
.eccbytes = 24,
|
||||||
.eccpos = {
|
.eccpos = {
|
||||||
40, 41, 42, 43, 44, 45, 46, 47,
|
40, 41, 42, 43, 44, 45, 46, 47,
|
||||||
|
|
@ -221,7 +220,7 @@ nand_ecclayout_t nand_oob_64 = {
|
||||||
|
|
||||||
/* nand device <nand_controller> [controller options]
|
/* nand device <nand_controller> [controller options]
|
||||||
*/
|
*/
|
||||||
int handle_nand_device_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
|
static int handle_nand_device_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
|
||||||
{
|
{
|
||||||
int i;
|
int i;
|
||||||
int retval;
|
int retval;
|
||||||
|
|
@ -346,7 +345,7 @@ nand_device_t *get_nand_device_by_num(int num)
|
||||||
return NULL;
|
return NULL;
|
||||||
}
|
}
|
||||||
|
|
||||||
int nand_build_bbt(struct nand_device_s *device, int first, int last)
|
static int nand_build_bbt(struct nand_device_s *device, int first, int last)
|
||||||
{
|
{
|
||||||
u32 page = 0x0;
|
u32 page = 0x0;
|
||||||
int i;
|
int i;
|
||||||
|
|
@ -405,7 +404,7 @@ int nand_read_status(struct nand_device_s *device, u8 *status)
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
int nand_poll_ready(struct nand_device_s *device, int timeout)
|
static int nand_poll_ready(struct nand_device_s *device, int timeout)
|
||||||
{
|
{
|
||||||
u8 status;
|
u8 status;
|
||||||
|
|
||||||
|
|
@ -729,7 +728,8 @@ int nand_erase(struct nand_device_s *device, int first_block, int last_block)
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
int nand_read_plain(struct nand_device_s *device, u32 address, u8 *data, u32 data_size)
|
#if 0
|
||||||
|
static int nand_read_plain(struct nand_device_s *device, u32 address, u8 *data, u32 data_size)
|
||||||
{
|
{
|
||||||
u8 *page;
|
u8 *page;
|
||||||
|
|
||||||
|
|
@ -766,7 +766,7 @@ int nand_read_plain(struct nand_device_s *device, u32 address, u8 *data, u32 dat
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
int nand_write_plain(struct nand_device_s *device, u32 address, u8 *data, u32 data_size)
|
static int nand_write_plain(struct nand_device_s *device, u32 address, u8 *data, u32 data_size)
|
||||||
{
|
{
|
||||||
u8 *page;
|
u8 *page;
|
||||||
|
|
||||||
|
|
@ -802,6 +802,7 @@ int nand_write_plain(struct nand_device_s *device, u32 address, u8 *data, u32 da
|
||||||
|
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
int nand_write_page(struct nand_device_s *device, u32 page, u8 *data, u32 data_size, u8 *oob, u32 oob_size)
|
int nand_write_page(struct nand_device_s *device, u32 page, u8 *data, u32 data_size, u8 *oob, u32 oob_size)
|
||||||
{
|
{
|
||||||
|
|
@ -820,7 +821,7 @@ int nand_write_page(struct nand_device_s *device, u32 page, u8 *data, u32 data_s
|
||||||
return device->controller->write_page(device, page, data, data_size, oob, oob_size);
|
return device->controller->write_page(device, page, data, data_size, oob, oob_size);
|
||||||
}
|
}
|
||||||
|
|
||||||
int nand_read_page(struct nand_device_s *device, u32 page, u8 *data, u32 data_size, u8 *oob, u32 oob_size)
|
static int nand_read_page(struct nand_device_s *device, u32 page, u8 *data, u32 data_size, u8 *oob, u32 oob_size)
|
||||||
{
|
{
|
||||||
if (!device->device)
|
if (!device->device)
|
||||||
return ERROR_NAND_DEVICE_NOT_PROBED;
|
return ERROR_NAND_DEVICE_NOT_PROBED;
|
||||||
|
|
@ -1089,7 +1090,7 @@ int handle_nand_list_command(struct command_context_s *cmd_ctx, char *cmd, char
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
int handle_nand_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
|
static int handle_nand_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
|
||||||
{
|
{
|
||||||
nand_device_t *p;
|
nand_device_t *p;
|
||||||
int i = 0;
|
int i = 0;
|
||||||
|
|
@ -1159,7 +1160,7 @@ int handle_nand_info_command(struct command_context_s *cmd_ctx, char *cmd, char
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
int handle_nand_probe_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
|
static int handle_nand_probe_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
|
||||||
{
|
{
|
||||||
nand_device_t *p;
|
nand_device_t *p;
|
||||||
int retval;
|
int retval;
|
||||||
|
|
@ -1193,7 +1194,7 @@ int handle_nand_probe_command(struct command_context_s *cmd_ctx, char *cmd, char
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
int handle_nand_erase_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
|
static int handle_nand_erase_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
|
||||||
{
|
{
|
||||||
nand_device_t *p;
|
nand_device_t *p;
|
||||||
int retval;
|
int retval;
|
||||||
|
|
@ -1274,7 +1275,7 @@ int handle_nand_check_bad_blocks_command(struct command_context_s *cmd_ctx, char
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
int handle_nand_copy_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
|
static int handle_nand_copy_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
|
||||||
{
|
{
|
||||||
nand_device_t *p;
|
nand_device_t *p;
|
||||||
|
|
||||||
|
|
@ -1297,7 +1298,7 @@ int handle_nand_copy_command(struct command_context_s *cmd_ctx, char *cmd, char
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
int handle_nand_write_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
|
static int handle_nand_write_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
|
||||||
{
|
{
|
||||||
u32 offset;
|
u32 offset;
|
||||||
u32 binary_size;
|
u32 binary_size;
|
||||||
|
|
@ -1452,7 +1453,7 @@ int handle_nand_write_command(struct command_context_s *cmd_ctx, char *cmd, char
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
int handle_nand_dump_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
|
static int handle_nand_dump_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
|
||||||
{
|
{
|
||||||
nand_device_t *p;
|
nand_device_t *p;
|
||||||
|
|
||||||
|
|
@ -1574,7 +1575,7 @@ int handle_nand_dump_command(struct command_context_s *cmd_ctx, char *cmd, char
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
int handle_nand_raw_access_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
|
static int handle_nand_raw_access_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
|
||||||
{
|
{
|
||||||
nand_device_t *p;
|
nand_device_t *p;
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -37,16 +37,16 @@
|
||||||
#include <string.h>
|
#include <string.h>
|
||||||
#include <unistd.h>
|
#include <unistd.h>
|
||||||
|
|
||||||
int ocl_register_commands(struct command_context_s *cmd_ctx);
|
static int ocl_register_commands(struct command_context_s *cmd_ctx);
|
||||||
int ocl_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank);
|
static int ocl_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank);
|
||||||
int ocl_erase(struct flash_bank_s *bank, int first, int last);
|
static int ocl_erase(struct flash_bank_s *bank, int first, int last);
|
||||||
int ocl_protect(struct flash_bank_s *bank, int set, int first, int last);
|
static int ocl_protect(struct flash_bank_s *bank, int set, int first, int last);
|
||||||
int ocl_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count);
|
static int ocl_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count);
|
||||||
int ocl_probe(struct flash_bank_s *bank);
|
static int ocl_probe(struct flash_bank_s *bank);
|
||||||
int ocl_erase_check(struct flash_bank_s *bank);
|
static int ocl_erase_check(struct flash_bank_s *bank);
|
||||||
int ocl_protect_check(struct flash_bank_s *bank);
|
static int ocl_protect_check(struct flash_bank_s *bank);
|
||||||
int ocl_info(struct flash_bank_s *bank, char *buf, int buf_size);
|
static int ocl_info(struct flash_bank_s *bank, char *buf, int buf_size);
|
||||||
int ocl_auto_probe(struct flash_bank_s *bank);
|
static int ocl_auto_probe(struct flash_bank_s *bank);
|
||||||
|
|
||||||
flash_driver_t ocl_flash =
|
flash_driver_t ocl_flash =
|
||||||
{
|
{
|
||||||
|
|
@ -70,23 +70,23 @@ typedef struct ocl_priv_s
|
||||||
int bufalign;
|
int bufalign;
|
||||||
} ocl_priv_t;
|
} ocl_priv_t;
|
||||||
|
|
||||||
int ocl_register_commands(struct command_context_s *cmd_ctx)
|
static int ocl_register_commands(struct command_context_s *cmd_ctx)
|
||||||
{
|
{
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
int ocl_erase_check(struct flash_bank_s *bank)
|
static int ocl_erase_check(struct flash_bank_s *bank)
|
||||||
{
|
{
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
int ocl_protect_check(struct flash_bank_s *bank)
|
static int ocl_protect_check(struct flash_bank_s *bank)
|
||||||
{
|
{
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
/* flash_bank ocl 0 0 0 0 <target#> */
|
/* flash_bank ocl 0 0 0 0 <target#> */
|
||||||
int ocl_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank)
|
static int ocl_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank)
|
||||||
{
|
{
|
||||||
int retval;
|
int retval;
|
||||||
armv4_5_common_t *armv4_5;
|
armv4_5_common_t *armv4_5;
|
||||||
|
|
@ -110,7 +110,7 @@ int ocl_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
int ocl_erase(struct flash_bank_s *bank, int first, int last)
|
static int ocl_erase(struct flash_bank_s *bank, int first, int last)
|
||||||
{
|
{
|
||||||
ocl_priv_t *ocl = bank->driver_priv;
|
ocl_priv_t *ocl = bank->driver_priv;
|
||||||
int retval;
|
int retval;
|
||||||
|
|
@ -165,12 +165,12 @@ int ocl_erase(struct flash_bank_s *bank, int first, int last)
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
int ocl_protect(struct flash_bank_s *bank, int set, int first, int last)
|
static int ocl_protect(struct flash_bank_s *bank, int set, int first, int last)
|
||||||
{
|
{
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
int ocl_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
|
static int ocl_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
|
||||||
{
|
{
|
||||||
ocl_priv_t *ocl = bank->driver_priv;
|
ocl_priv_t *ocl = bank->driver_priv;
|
||||||
int retval;
|
int retval;
|
||||||
|
|
@ -277,7 +277,7 @@ int ocl_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
int ocl_probe(struct flash_bank_s *bank)
|
static int ocl_probe(struct flash_bank_s *bank)
|
||||||
{
|
{
|
||||||
ocl_priv_t *ocl = bank->driver_priv;
|
ocl_priv_t *ocl = bank->driver_priv;
|
||||||
int retval;
|
int retval;
|
||||||
|
|
@ -375,12 +375,12 @@ int ocl_probe(struct flash_bank_s *bank)
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
int ocl_info(struct flash_bank_s *bank, char *buf, int buf_size)
|
static int ocl_info(struct flash_bank_s *bank, char *buf, int buf_size)
|
||||||
{
|
{
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
int ocl_auto_probe(struct flash_bank_s *bank)
|
static int ocl_auto_probe(struct flash_bank_s *bank)
|
||||||
{
|
{
|
||||||
ocl_priv_t *ocl = bank->driver_priv;
|
ocl_priv_t *ocl = bank->driver_priv;
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -55,7 +55,7 @@ typedef struct orion_nand_controller_s
|
||||||
} \
|
} \
|
||||||
} while (0)
|
} while (0)
|
||||||
|
|
||||||
int orion_nand_command(struct nand_device_s *device, u8 command)
|
static int orion_nand_command(struct nand_device_s *device, u8 command)
|
||||||
{
|
{
|
||||||
orion_nand_controller_t *hw = device->controller_priv;
|
orion_nand_controller_t *hw = device->controller_priv;
|
||||||
target_t *target = hw->target;
|
target_t *target = hw->target;
|
||||||
|
|
@ -65,7 +65,7 @@ int orion_nand_command(struct nand_device_s *device, u8 command)
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
int orion_nand_address(struct nand_device_s *device, u8 address)
|
static int orion_nand_address(struct nand_device_s *device, u8 address)
|
||||||
{
|
{
|
||||||
orion_nand_controller_t *hw = device->controller_priv;
|
orion_nand_controller_t *hw = device->controller_priv;
|
||||||
target_t *target = hw->target;
|
target_t *target = hw->target;
|
||||||
|
|
@ -75,7 +75,7 @@ int orion_nand_address(struct nand_device_s *device, u8 address)
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
int orion_nand_read(struct nand_device_s *device, void *data)
|
static int orion_nand_read(struct nand_device_s *device, void *data)
|
||||||
{
|
{
|
||||||
orion_nand_controller_t *hw = device->controller_priv;
|
orion_nand_controller_t *hw = device->controller_priv;
|
||||||
target_t *target = hw->target;
|
target_t *target = hw->target;
|
||||||
|
|
@ -85,7 +85,7 @@ int orion_nand_read(struct nand_device_s *device, void *data)
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
int orion_nand_write(struct nand_device_s *device, u16 data)
|
static int orion_nand_write(struct nand_device_s *device, u16 data)
|
||||||
{
|
{
|
||||||
orion_nand_controller_t *hw = device->controller_priv;
|
orion_nand_controller_t *hw = device->controller_priv;
|
||||||
target_t *target = hw->target;
|
target_t *target = hw->target;
|
||||||
|
|
@ -95,14 +95,14 @@ int orion_nand_write(struct nand_device_s *device, u16 data)
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
int orion_nand_slow_block_write(struct nand_device_s *device, u8 *data, int size)
|
static int orion_nand_slow_block_write(struct nand_device_s *device, u8 *data, int size)
|
||||||
{
|
{
|
||||||
while (size--)
|
while (size--)
|
||||||
orion_nand_write(device, *data++);
|
orion_nand_write(device, *data++);
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
int orion_nand_fast_block_write(struct nand_device_s *device, u8 *data, int size)
|
static int orion_nand_fast_block_write(struct nand_device_s *device, u8 *data, int size)
|
||||||
{
|
{
|
||||||
orion_nand_controller_t *hw = device->controller_priv;
|
orion_nand_controller_t *hw = device->controller_priv;
|
||||||
target_t *target = hw->target;
|
target_t *target = hw->target;
|
||||||
|
|
@ -181,17 +181,17 @@ int orion_nand_fast_block_write(struct nand_device_s *device, u8 *data, int size
|
||||||
return retval;
|
return retval;
|
||||||
}
|
}
|
||||||
|
|
||||||
int orion_nand_reset(struct nand_device_s *device)
|
static int orion_nand_reset(struct nand_device_s *device)
|
||||||
{
|
{
|
||||||
return orion_nand_command(device, NAND_CMD_RESET);
|
return orion_nand_command(device, NAND_CMD_RESET);
|
||||||
}
|
}
|
||||||
|
|
||||||
int orion_nand_controller_ready(struct nand_device_s *device, int timeout)
|
static int orion_nand_controller_ready(struct nand_device_s *device, int timeout)
|
||||||
{
|
{
|
||||||
return 1;
|
return 1;
|
||||||
}
|
}
|
||||||
|
|
||||||
int orion_nand_register_commands(struct command_context_s *cmd_ctx)
|
static int orion_nand_register_commands(struct command_context_s *cmd_ctx)
|
||||||
{
|
{
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
@ -234,7 +234,7 @@ int orion_nand_device_command(struct command_context_s *cmd_ctx, char *cmd,
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
int orion_nand_init(struct nand_device_s *device)
|
static int orion_nand_init(struct nand_device_s *device)
|
||||||
{
|
{
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
|
||||||
|
|
@ -66,26 +66,26 @@ struct pic32mx_devs_s {
|
||||||
{ 0x00, NULL, 0 }
|
{ 0x00, NULL, 0 }
|
||||||
};
|
};
|
||||||
|
|
||||||
int pic32mx_register_commands(struct command_context_s *cmd_ctx);
|
static int pic32mx_register_commands(struct command_context_s *cmd_ctx);
|
||||||
int pic32mx_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank);
|
static int pic32mx_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank);
|
||||||
int pic32mx_erase(struct flash_bank_s *bank, int first, int last);
|
static int pic32mx_erase(struct flash_bank_s *bank, int first, int last);
|
||||||
int pic32mx_protect(struct flash_bank_s *bank, int set, int first, int last);
|
static int pic32mx_protect(struct flash_bank_s *bank, int set, int first, int last);
|
||||||
int pic32mx_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count);
|
static int pic32mx_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count);
|
||||||
int pic32mx_write_row(struct flash_bank_s *bank, u32 address, u32 srcaddr);
|
static int pic32mx_write_row(struct flash_bank_s *bank, u32 address, u32 srcaddr);
|
||||||
int pic32mx_write_word(struct flash_bank_s *bank, u32 address, u32 word);
|
static int pic32mx_write_word(struct flash_bank_s *bank, u32 address, u32 word);
|
||||||
int pic32mx_probe(struct flash_bank_s *bank);
|
static int pic32mx_probe(struct flash_bank_s *bank);
|
||||||
int pic32mx_auto_probe(struct flash_bank_s *bank);
|
static int pic32mx_auto_probe(struct flash_bank_s *bank);
|
||||||
int pic32mx_handle_part_id_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
|
//static int pic32mx_handle_part_id_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
|
||||||
int pic32mx_protect_check(struct flash_bank_s *bank);
|
static int pic32mx_protect_check(struct flash_bank_s *bank);
|
||||||
int pic32mx_info(struct flash_bank_s *bank, char *buf, int buf_size);
|
static int pic32mx_info(struct flash_bank_s *bank, char *buf, int buf_size);
|
||||||
|
|
||||||
#if 0
|
#if 0
|
||||||
int pic32mx_handle_lock_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
|
int pic32mx_handle_lock_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
|
||||||
int pic32mx_handle_unlock_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
|
int pic32mx_handle_unlock_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
|
||||||
#endif
|
#endif
|
||||||
int pic32mx_handle_chip_erase_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
|
static int pic32mx_handle_chip_erase_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
|
||||||
int pic32mx_handle_pgm_word_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
|
static int pic32mx_handle_pgm_word_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
|
||||||
int pic32mx_chip_erase(struct flash_bank_s *bank);
|
//static int pic32mx_chip_erase(struct flash_bank_s *bank);
|
||||||
|
|
||||||
flash_driver_t pic32mx_flash =
|
flash_driver_t pic32mx_flash =
|
||||||
{
|
{
|
||||||
|
|
@ -102,7 +102,7 @@ flash_driver_t pic32mx_flash =
|
||||||
.info = pic32mx_info
|
.info = pic32mx_info
|
||||||
};
|
};
|
||||||
|
|
||||||
int pic32mx_register_commands(struct command_context_s *cmd_ctx)
|
static int pic32mx_register_commands(struct command_context_s *cmd_ctx)
|
||||||
{
|
{
|
||||||
command_t *pic32mx_cmd = register_command(cmd_ctx, NULL, "pic32mx", NULL, COMMAND_ANY, "pic32mx flash specific commands");
|
command_t *pic32mx_cmd = register_command(cmd_ctx, NULL, "pic32mx", NULL, COMMAND_ANY, "pic32mx flash specific commands");
|
||||||
|
|
||||||
|
|
@ -121,7 +121,7 @@ int pic32mx_register_commands(struct command_context_s *cmd_ctx)
|
||||||
|
|
||||||
/* flash bank pic32mx <base> <size> 0 0 <target#>
|
/* flash bank pic32mx <base> <size> 0 0 <target#>
|
||||||
*/
|
*/
|
||||||
int pic32mx_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank)
|
static int pic32mx_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank)
|
||||||
{
|
{
|
||||||
pic32mx_flash_bank_t *pic32mx_info;
|
pic32mx_flash_bank_t *pic32mx_info;
|
||||||
|
|
||||||
|
|
@ -140,7 +140,7 @@ int pic32mx_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, cha
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
u32 pic32mx_get_flash_status(flash_bank_t *bank)
|
static u32 pic32mx_get_flash_status(flash_bank_t *bank)
|
||||||
{
|
{
|
||||||
target_t *target = bank->target;
|
target_t *target = bank->target;
|
||||||
u32 status;
|
u32 status;
|
||||||
|
|
@ -150,7 +150,7 @@ u32 pic32mx_get_flash_status(flash_bank_t *bank)
|
||||||
return status;
|
return status;
|
||||||
}
|
}
|
||||||
|
|
||||||
u32 pic32mx_wait_status_busy(flash_bank_t *bank, int timeout)
|
static u32 pic32mx_wait_status_busy(flash_bank_t *bank, int timeout)
|
||||||
{
|
{
|
||||||
u32 status;
|
u32 status;
|
||||||
|
|
||||||
|
|
@ -166,7 +166,7 @@ u32 pic32mx_wait_status_busy(flash_bank_t *bank, int timeout)
|
||||||
return status;
|
return status;
|
||||||
}
|
}
|
||||||
|
|
||||||
int pic32mx_nvm_exec(struct flash_bank_s *bank, u32 op, u32 timeout)
|
static int pic32mx_nvm_exec(struct flash_bank_s *bank, u32 op, u32 timeout)
|
||||||
{
|
{
|
||||||
target_t *target = bank->target;
|
target_t *target = bank->target;
|
||||||
u32 status;
|
u32 status;
|
||||||
|
|
@ -188,7 +188,7 @@ int pic32mx_nvm_exec(struct flash_bank_s *bank, u32 op, u32 timeout)
|
||||||
return status;
|
return status;
|
||||||
}
|
}
|
||||||
|
|
||||||
int pic32mx_protect_check(struct flash_bank_s *bank)
|
static int pic32mx_protect_check(struct flash_bank_s *bank)
|
||||||
{
|
{
|
||||||
target_t *target = bank->target;
|
target_t *target = bank->target;
|
||||||
|
|
||||||
|
|
@ -222,7 +222,7 @@ int pic32mx_protect_check(struct flash_bank_s *bank)
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
int pic32mx_erase(struct flash_bank_s *bank, int first, int last)
|
static int pic32mx_erase(struct flash_bank_s *bank, int first, int last)
|
||||||
{
|
{
|
||||||
target_t *target = bank->target;
|
target_t *target = bank->target;
|
||||||
int i;
|
int i;
|
||||||
|
|
@ -264,7 +264,7 @@ int pic32mx_erase(struct flash_bank_s *bank, int first, int last)
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
int pic32mx_protect(struct flash_bank_s *bank, int set, int first, int last)
|
static int pic32mx_protect(struct flash_bank_s *bank, int set, int first, int last)
|
||||||
{
|
{
|
||||||
pic32mx_flash_bank_t *pic32mx_info = NULL;
|
pic32mx_flash_bank_t *pic32mx_info = NULL;
|
||||||
target_t *target = bank->target;
|
target_t *target = bank->target;
|
||||||
|
|
@ -357,7 +357,7 @@ int pic32mx_protect(struct flash_bank_s *bank, int set, int first, int last)
|
||||||
#endif
|
#endif
|
||||||
}
|
}
|
||||||
|
|
||||||
int pic32mx_write_block(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
|
static int pic32mx_write_block(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
|
||||||
{
|
{
|
||||||
target_t *target = bank->target;
|
target_t *target = bank->target;
|
||||||
u32 buffer_size = 512;
|
u32 buffer_size = 512;
|
||||||
|
|
@ -485,7 +485,7 @@ int pic32mx_write_block(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 c
|
||||||
return retval;
|
return retval;
|
||||||
}
|
}
|
||||||
|
|
||||||
int pic32mx_write_word(struct flash_bank_s *bank, u32 address, u32 word)
|
static int pic32mx_write_word(struct flash_bank_s *bank, u32 address, u32 word)
|
||||||
{
|
{
|
||||||
target_t *target = bank->target;
|
target_t *target = bank->target;
|
||||||
|
|
||||||
|
|
@ -501,7 +501,7 @@ int pic32mx_write_word(struct flash_bank_s *bank, u32 address, u32 word)
|
||||||
/*
|
/*
|
||||||
* Write a 128 word (512 byte) row to flash address from RAM srcaddr.
|
* Write a 128 word (512 byte) row to flash address from RAM srcaddr.
|
||||||
*/
|
*/
|
||||||
int pic32mx_write_row(struct flash_bank_s *bank, u32 address, u32 srcaddr)
|
static int pic32mx_write_row(struct flash_bank_s *bank, u32 address, u32 srcaddr)
|
||||||
{
|
{
|
||||||
target_t *target = bank->target;
|
target_t *target = bank->target;
|
||||||
|
|
||||||
|
|
@ -519,7 +519,7 @@ int pic32mx_write_row(struct flash_bank_s *bank, u32 address, u32 srcaddr)
|
||||||
return pic32mx_nvm_exec(bank, NVMCON_OP_ROW_PROG, 100);
|
return pic32mx_nvm_exec(bank, NVMCON_OP_ROW_PROG, 100);
|
||||||
}
|
}
|
||||||
|
|
||||||
int pic32mx_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
|
static int pic32mx_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
|
||||||
{
|
{
|
||||||
u32 words_remaining = (count / 4);
|
u32 words_remaining = (count / 4);
|
||||||
u32 bytes_remaining = (count & 0x00000003);
|
u32 bytes_remaining = (count & 0x00000003);
|
||||||
|
|
@ -604,7 +604,7 @@ int pic32mx_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
int pic32mx_probe(struct flash_bank_s *bank)
|
static int pic32mx_probe(struct flash_bank_s *bank)
|
||||||
{
|
{
|
||||||
target_t *target = bank->target;
|
target_t *target = bank->target;
|
||||||
pic32mx_flash_bank_t *pic32mx_info = bank->driver_priv;
|
pic32mx_flash_bank_t *pic32mx_info = bank->driver_priv;
|
||||||
|
|
@ -683,7 +683,7 @@ int pic32mx_probe(struct flash_bank_s *bank)
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
int pic32mx_auto_probe(struct flash_bank_s *bank)
|
static int pic32mx_auto_probe(struct flash_bank_s *bank)
|
||||||
{
|
{
|
||||||
pic32mx_flash_bank_t *pic32mx_info = bank->driver_priv;
|
pic32mx_flash_bank_t *pic32mx_info = bank->driver_priv;
|
||||||
if (pic32mx_info->probed)
|
if (pic32mx_info->probed)
|
||||||
|
|
@ -691,12 +691,14 @@ int pic32mx_auto_probe(struct flash_bank_s *bank)
|
||||||
return pic32mx_probe(bank);
|
return pic32mx_probe(bank);
|
||||||
}
|
}
|
||||||
|
|
||||||
int pic32mx_handle_part_id_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
|
#if 0
|
||||||
|
static int pic32mx_handle_part_id_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
|
||||||
{
|
{
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
int pic32mx_info(struct flash_bank_s *bank, char *buf, int buf_size)
|
static int pic32mx_info(struct flash_bank_s *bank, char *buf, int buf_size)
|
||||||
{
|
{
|
||||||
target_t *target = bank->target;
|
target_t *target = bank->target;
|
||||||
mips32_common_t *mips32 = target->arch_info;
|
mips32_common_t *mips32 = target->arch_info;
|
||||||
|
|
@ -823,7 +825,8 @@ int pic32mx_handle_unlock_command(struct command_context_s *cmd_ctx, char *cmd,
|
||||||
}
|
}
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
int pic32mx_chip_erase(struct flash_bank_s *bank)
|
#if 0
|
||||||
|
static int pic32mx_chip_erase(struct flash_bank_s *bank)
|
||||||
{
|
{
|
||||||
target_t *target = bank->target;
|
target_t *target = bank->target;
|
||||||
#if 0
|
#if 0
|
||||||
|
|
@ -866,8 +869,9 @@ int pic32mx_chip_erase(struct flash_bank_s *bank)
|
||||||
|
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
int pic32mx_handle_chip_erase_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
|
static int pic32mx_handle_chip_erase_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
|
||||||
{
|
{
|
||||||
#if 0
|
#if 0
|
||||||
flash_bank_t *bank;
|
flash_bank_t *bank;
|
||||||
|
|
@ -905,7 +909,7 @@ int pic32mx_handle_chip_erase_command(struct command_context_s *cmd_ctx, char *c
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
int pic32mx_handle_pgm_word_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
|
static int pic32mx_handle_pgm_word_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
|
||||||
{
|
{
|
||||||
flash_bank_t *bank;
|
flash_bank_t *bank;
|
||||||
u32 address, value;
|
u32 address, value;
|
||||||
|
|
|
||||||
|
|
@ -38,11 +38,11 @@
|
||||||
#include "s3c24xx_nand.h"
|
#include "s3c24xx_nand.h"
|
||||||
#include "target.h"
|
#include "target.h"
|
||||||
|
|
||||||
int s3c2410_nand_device_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct nand_device_s *device);
|
static int s3c2410_nand_device_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct nand_device_s *device);
|
||||||
int s3c2410_init(struct nand_device_s *device);
|
static int s3c2410_init(struct nand_device_s *device);
|
||||||
int s3c2410_read_data(struct nand_device_s *device, void *data);
|
static int s3c2410_read_data(struct nand_device_s *device, void *data);
|
||||||
int s3c2410_write_data(struct nand_device_s *device, u16 data);
|
static int s3c2410_write_data(struct nand_device_s *device, u16 data);
|
||||||
int s3c2410_nand_ready(struct nand_device_s *device, int timeout);
|
static int s3c2410_nand_ready(struct nand_device_s *device, int timeout);
|
||||||
|
|
||||||
nand_flash_controller_t s3c2410_nand_controller =
|
nand_flash_controller_t s3c2410_nand_controller =
|
||||||
{
|
{
|
||||||
|
|
@ -61,7 +61,7 @@ nand_flash_controller_t s3c2410_nand_controller =
|
||||||
.nand_ready = s3c2410_nand_ready,
|
.nand_ready = s3c2410_nand_ready,
|
||||||
};
|
};
|
||||||
|
|
||||||
int s3c2410_nand_device_command(struct command_context_s *cmd_ctx, char *cmd,
|
static int s3c2410_nand_device_command(struct command_context_s *cmd_ctx, char *cmd,
|
||||||
char **args, int argc,
|
char **args, int argc,
|
||||||
struct nand_device_s *device)
|
struct nand_device_s *device)
|
||||||
{
|
{
|
||||||
|
|
@ -81,7 +81,7 @@ int s3c2410_nand_device_command(struct command_context_s *cmd_ctx, char *cmd,
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
int s3c2410_init(struct nand_device_s *device)
|
static int s3c2410_init(struct nand_device_s *device)
|
||||||
{
|
{
|
||||||
s3c24xx_nand_controller_t *s3c24xx_info = device->controller_priv;
|
s3c24xx_nand_controller_t *s3c24xx_info = device->controller_priv;
|
||||||
target_t *target = s3c24xx_info->target;
|
target_t *target = s3c24xx_info->target;
|
||||||
|
|
@ -93,7 +93,7 @@ int s3c2410_init(struct nand_device_s *device)
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
int s3c2410_write_data(struct nand_device_s *device, u16 data)
|
static int s3c2410_write_data(struct nand_device_s *device, u16 data)
|
||||||
{
|
{
|
||||||
s3c24xx_nand_controller_t *s3c24xx_info = device->controller_priv;
|
s3c24xx_nand_controller_t *s3c24xx_info = device->controller_priv;
|
||||||
target_t *target = s3c24xx_info->target;
|
target_t *target = s3c24xx_info->target;
|
||||||
|
|
@ -107,7 +107,7 @@ int s3c2410_write_data(struct nand_device_s *device, u16 data)
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
int s3c2410_read_data(struct nand_device_s *device, void *data)
|
static int s3c2410_read_data(struct nand_device_s *device, void *data)
|
||||||
{
|
{
|
||||||
s3c24xx_nand_controller_t *s3c24xx_info = device->controller_priv;
|
s3c24xx_nand_controller_t *s3c24xx_info = device->controller_priv;
|
||||||
target_t *target = s3c24xx_info->target;
|
target_t *target = s3c24xx_info->target;
|
||||||
|
|
@ -121,7 +121,7 @@ int s3c2410_read_data(struct nand_device_s *device, void *data)
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
int s3c2410_nand_ready(struct nand_device_s *device, int timeout)
|
static int s3c2410_nand_ready(struct nand_device_s *device, int timeout)
|
||||||
{
|
{
|
||||||
s3c24xx_nand_controller_t *s3c24xx_info = device->controller_priv;
|
s3c24xx_nand_controller_t *s3c24xx_info = device->controller_priv;
|
||||||
target_t *target = s3c24xx_info->target;
|
target_t *target = s3c24xx_info->target;
|
||||||
|
|
|
||||||
|
|
@ -38,8 +38,8 @@
|
||||||
#include "s3c24xx_nand.h"
|
#include "s3c24xx_nand.h"
|
||||||
#include "target.h"
|
#include "target.h"
|
||||||
|
|
||||||
int s3c2412_nand_device_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct nand_device_s *device);
|
static int s3c2412_nand_device_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct nand_device_s *device);
|
||||||
int s3c2412_init(struct nand_device_s *device);
|
static int s3c2412_init(struct nand_device_s *device);
|
||||||
|
|
||||||
nand_flash_controller_t s3c2412_nand_controller =
|
nand_flash_controller_t s3c2412_nand_controller =
|
||||||
{
|
{
|
||||||
|
|
@ -60,7 +60,7 @@ nand_flash_controller_t s3c2412_nand_controller =
|
||||||
.nand_ready = s3c2440_nand_ready,
|
.nand_ready = s3c2440_nand_ready,
|
||||||
};
|
};
|
||||||
|
|
||||||
int s3c2412_nand_device_command(struct command_context_s *cmd_ctx, char *cmd,
|
static int s3c2412_nand_device_command(struct command_context_s *cmd_ctx, char *cmd,
|
||||||
char **args, int argc,
|
char **args, int argc,
|
||||||
struct nand_device_s *device)
|
struct nand_device_s *device)
|
||||||
{
|
{
|
||||||
|
|
@ -80,7 +80,7 @@ int s3c2412_nand_device_command(struct command_context_s *cmd_ctx, char *cmd,
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
int s3c2412_init(struct nand_device_s *device)
|
static int s3c2412_init(struct nand_device_s *device)
|
||||||
{
|
{
|
||||||
s3c24xx_nand_controller_t *s3c24xx_info = device->controller_priv;
|
s3c24xx_nand_controller_t *s3c24xx_info = device->controller_priv;
|
||||||
target_t *target = s3c24xx_info->target;
|
target_t *target = s3c24xx_info->target;
|
||||||
|
|
|
||||||
|
|
@ -38,9 +38,9 @@
|
||||||
#include "s3c24xx_nand.h"
|
#include "s3c24xx_nand.h"
|
||||||
#include "target.h"
|
#include "target.h"
|
||||||
|
|
||||||
int s3c2440_nand_device_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct nand_device_s *device);
|
static int s3c2440_nand_device_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct nand_device_s *device);
|
||||||
int s3c2440_init(struct nand_device_s *device);
|
static int s3c2440_init(struct nand_device_s *device);
|
||||||
int s3c2440_nand_ready(struct nand_device_s *device, int timeout);
|
//static int s3c2440_nand_ready(struct nand_device_s *device, int timeout);
|
||||||
|
|
||||||
nand_flash_controller_t s3c2440_nand_controller =
|
nand_flash_controller_t s3c2440_nand_controller =
|
||||||
{
|
{
|
||||||
|
|
@ -61,7 +61,7 @@ nand_flash_controller_t s3c2440_nand_controller =
|
||||||
.nand_ready = s3c2440_nand_ready,
|
.nand_ready = s3c2440_nand_ready,
|
||||||
};
|
};
|
||||||
|
|
||||||
int s3c2440_nand_device_command(struct command_context_s *cmd_ctx, char *cmd,
|
static int s3c2440_nand_device_command(struct command_context_s *cmd_ctx, char *cmd,
|
||||||
char **args, int argc,
|
char **args, int argc,
|
||||||
struct nand_device_s *device)
|
struct nand_device_s *device)
|
||||||
{
|
{
|
||||||
|
|
@ -81,7 +81,7 @@ int s3c2440_nand_device_command(struct command_context_s *cmd_ctx, char *cmd,
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
int s3c2440_init(struct nand_device_s *device)
|
static int s3c2440_init(struct nand_device_s *device)
|
||||||
{
|
{
|
||||||
s3c24xx_nand_controller_t *s3c24xx_info = device->controller_priv;
|
s3c24xx_nand_controller_t *s3c24xx_info = device->controller_priv;
|
||||||
target_t *target = s3c24xx_info->target;
|
target_t *target = s3c24xx_info->target;
|
||||||
|
|
|
||||||
|
|
@ -38,9 +38,8 @@
|
||||||
#include "s3c24xx_nand.h"
|
#include "s3c24xx_nand.h"
|
||||||
#include "target.h"
|
#include "target.h"
|
||||||
|
|
||||||
int s3c2443_nand_device_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct nand_device_s *device);
|
static int s3c2443_nand_device_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct nand_device_s *device);
|
||||||
int s3c2443_init(struct nand_device_s *device);
|
static int s3c2443_init(struct nand_device_s *device);
|
||||||
int s3c2443_nand_ready(struct nand_device_s *device, int timeout);
|
|
||||||
|
|
||||||
nand_flash_controller_t s3c2443_nand_controller =
|
nand_flash_controller_t s3c2443_nand_controller =
|
||||||
{
|
{
|
||||||
|
|
@ -61,7 +60,7 @@ nand_flash_controller_t s3c2443_nand_controller =
|
||||||
.nand_ready = s3c2440_nand_ready,
|
.nand_ready = s3c2440_nand_ready,
|
||||||
};
|
};
|
||||||
|
|
||||||
int s3c2443_nand_device_command(struct command_context_s *cmd_ctx, char *cmd,
|
static int s3c2443_nand_device_command(struct command_context_s *cmd_ctx, char *cmd,
|
||||||
char **args, int argc,
|
char **args, int argc,
|
||||||
struct nand_device_s *device)
|
struct nand_device_s *device)
|
||||||
{
|
{
|
||||||
|
|
@ -81,7 +80,7 @@ int s3c2443_nand_device_command(struct command_context_s *cmd_ctx, char *cmd,
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
int s3c2443_init(struct nand_device_s *device)
|
static int s3c2443_init(struct nand_device_s *device)
|
||||||
{
|
{
|
||||||
s3c24xx_nand_controller_t *s3c24xx_info = device->controller_priv;
|
s3c24xx_nand_controller_t *s3c24xx_info = device->controller_priv;
|
||||||
target_t *target = s3c24xx_info->target;
|
target_t *target = s3c24xx_info->target;
|
||||||
|
|
|
||||||
|
|
@ -44,24 +44,24 @@
|
||||||
#include <unistd.h>
|
#include <unistd.h>
|
||||||
|
|
||||||
#define DID0_VER(did0) ((did0>>28)&0x07)
|
#define DID0_VER(did0) ((did0>>28)&0x07)
|
||||||
int stellaris_register_commands(struct command_context_s *cmd_ctx);
|
static int stellaris_register_commands(struct command_context_s *cmd_ctx);
|
||||||
int stellaris_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank);
|
static int stellaris_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank);
|
||||||
int stellaris_erase(struct flash_bank_s *bank, int first, int last);
|
static int stellaris_erase(struct flash_bank_s *bank, int first, int last);
|
||||||
int stellaris_protect(struct flash_bank_s *bank, int set, int first, int last);
|
static int stellaris_protect(struct flash_bank_s *bank, int set, int first, int last);
|
||||||
int stellaris_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count);
|
static int stellaris_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count);
|
||||||
int stellaris_auto_probe(struct flash_bank_s *bank);
|
static int stellaris_auto_probe(struct flash_bank_s *bank);
|
||||||
int stellaris_probe(struct flash_bank_s *bank);
|
static int stellaris_probe(struct flash_bank_s *bank);
|
||||||
int stellaris_protect_check(struct flash_bank_s *bank);
|
static int stellaris_protect_check(struct flash_bank_s *bank);
|
||||||
int stellaris_info(struct flash_bank_s *bank, char *buf, int buf_size);
|
static int stellaris_info(struct flash_bank_s *bank, char *buf, int buf_size);
|
||||||
|
|
||||||
int stellaris_read_part_info(struct flash_bank_s *bank);
|
static int stellaris_read_part_info(struct flash_bank_s *bank);
|
||||||
u32 stellaris_get_flash_status(flash_bank_t *bank);
|
static u32 stellaris_get_flash_status(flash_bank_t *bank);
|
||||||
void stellaris_set_flash_mode(flash_bank_t *bank,int mode);
|
static void stellaris_set_flash_mode(flash_bank_t *bank,int mode);
|
||||||
u32 stellaris_wait_status_busy(flash_bank_t *bank, u32 waitbits, int timeout);
|
//static u32 stellaris_wait_status_busy(flash_bank_t *bank, u32 waitbits, int timeout);
|
||||||
|
|
||||||
int stellaris_read_part_info(struct flash_bank_s *bank);
|
static int stellaris_read_part_info(struct flash_bank_s *bank);
|
||||||
int stellaris_handle_mass_erase_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
|
static int stellaris_handle_mass_erase_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
|
||||||
int stellaris_mass_erase(struct flash_bank_s *bank);
|
static int stellaris_mass_erase(struct flash_bank_s *bank);
|
||||||
|
|
||||||
flash_driver_t stellaris_flash =
|
flash_driver_t stellaris_flash =
|
||||||
{
|
{
|
||||||
|
|
@ -78,7 +78,7 @@ flash_driver_t stellaris_flash =
|
||||||
.info = stellaris_info
|
.info = stellaris_info
|
||||||
};
|
};
|
||||||
|
|
||||||
struct {
|
static struct {
|
||||||
u32 partno;
|
u32 partno;
|
||||||
char *partname;
|
char *partname;
|
||||||
} StellarisParts[] =
|
} StellarisParts[] =
|
||||||
|
|
@ -234,7 +234,7 @@ struct {
|
||||||
{0,"Unknown part"}
|
{0,"Unknown part"}
|
||||||
};
|
};
|
||||||
|
|
||||||
char * StellarisClassname[5] =
|
static char * StellarisClassname[5] =
|
||||||
{
|
{
|
||||||
"Sandstorm",
|
"Sandstorm",
|
||||||
"Fury",
|
"Fury",
|
||||||
|
|
@ -249,7 +249,7 @@ char * StellarisClassname[5] =
|
||||||
|
|
||||||
/* flash_bank stellaris <base> <size> 0 0 <target#>
|
/* flash_bank stellaris <base> <size> 0 0 <target#>
|
||||||
*/
|
*/
|
||||||
int stellaris_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank)
|
static int stellaris_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank)
|
||||||
{
|
{
|
||||||
stellaris_flash_bank_t *stellaris_info;
|
stellaris_flash_bank_t *stellaris_info;
|
||||||
|
|
||||||
|
|
@ -272,7 +272,7 @@ int stellaris_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, c
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
int stellaris_register_commands(struct command_context_s *cmd_ctx)
|
static int stellaris_register_commands(struct command_context_s *cmd_ctx)
|
||||||
{
|
{
|
||||||
command_t *stm32x_cmd = register_command(cmd_ctx, NULL, "stellaris", NULL, COMMAND_ANY, "stellaris flash specific commands");
|
command_t *stm32x_cmd = register_command(cmd_ctx, NULL, "stellaris", NULL, COMMAND_ANY, "stellaris flash specific commands");
|
||||||
|
|
||||||
|
|
@ -280,7 +280,7 @@ int stellaris_register_commands(struct command_context_s *cmd_ctx)
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
int stellaris_info(struct flash_bank_s *bank, char *buf, int buf_size)
|
static int stellaris_info(struct flash_bank_s *bank, char *buf, int buf_size)
|
||||||
{
|
{
|
||||||
int printed, device_class;
|
int printed, device_class;
|
||||||
stellaris_flash_bank_t *stellaris_info = bank->driver_priv;
|
stellaris_flash_bank_t *stellaris_info = bank->driver_priv;
|
||||||
|
|
@ -331,7 +331,7 @@ int stellaris_info(struct flash_bank_s *bank, char *buf, int buf_size)
|
||||||
* chip identification and status *
|
* chip identification and status *
|
||||||
***************************************************************************/
|
***************************************************************************/
|
||||||
|
|
||||||
u32 stellaris_get_flash_status(flash_bank_t *bank)
|
static u32 stellaris_get_flash_status(flash_bank_t *bank)
|
||||||
{
|
{
|
||||||
target_t *target = bank->target;
|
target_t *target = bank->target;
|
||||||
u32 fmc;
|
u32 fmc;
|
||||||
|
|
@ -343,7 +343,7 @@ u32 stellaris_get_flash_status(flash_bank_t *bank)
|
||||||
|
|
||||||
/** Read clock configuration and set stellaris_info->usec_clocks*/
|
/** Read clock configuration and set stellaris_info->usec_clocks*/
|
||||||
|
|
||||||
void stellaris_read_clock_info(flash_bank_t *bank)
|
static void stellaris_read_clock_info(flash_bank_t *bank)
|
||||||
{
|
{
|
||||||
stellaris_flash_bank_t *stellaris_info = bank->driver_priv;
|
stellaris_flash_bank_t *stellaris_info = bank->driver_priv;
|
||||||
target_t *target = bank->target;
|
target_t *target = bank->target;
|
||||||
|
|
@ -395,7 +395,7 @@ void stellaris_read_clock_info(flash_bank_t *bank)
|
||||||
}
|
}
|
||||||
|
|
||||||
/* Setup the timimg registers */
|
/* Setup the timimg registers */
|
||||||
void stellaris_set_flash_mode(flash_bank_t *bank,int mode)
|
static void stellaris_set_flash_mode(flash_bank_t *bank,int mode)
|
||||||
{
|
{
|
||||||
stellaris_flash_bank_t *stellaris_info = bank->driver_priv;
|
stellaris_flash_bank_t *stellaris_info = bank->driver_priv;
|
||||||
target_t *target = bank->target;
|
target_t *target = bank->target;
|
||||||
|
|
@ -405,7 +405,8 @@ void stellaris_set_flash_mode(flash_bank_t *bank,int mode)
|
||||||
target_write_u32(target, SCB_BASE|USECRL, usecrl);
|
target_write_u32(target, SCB_BASE|USECRL, usecrl);
|
||||||
}
|
}
|
||||||
|
|
||||||
u32 stellaris_wait_status_busy(flash_bank_t *bank, u32 waitbits, int timeout)
|
#if 0
|
||||||
|
static u32 stellaris_wait_status_busy(flash_bank_t *bank, u32 waitbits, int timeout)
|
||||||
{
|
{
|
||||||
u32 status;
|
u32 status;
|
||||||
|
|
||||||
|
|
@ -422,7 +423,7 @@ u32 stellaris_wait_status_busy(flash_bank_t *bank, u32 waitbits, int timeout)
|
||||||
}
|
}
|
||||||
|
|
||||||
/* Send one command to the flash controller */
|
/* Send one command to the flash controller */
|
||||||
int stellaris_flash_command(struct flash_bank_s *bank,u8 cmd,u16 pagen)
|
static int stellaris_flash_command(struct flash_bank_s *bank,u8 cmd,u16 pagen)
|
||||||
{
|
{
|
||||||
u32 fmc;
|
u32 fmc;
|
||||||
target_t *target = bank->target;
|
target_t *target = bank->target;
|
||||||
|
|
@ -438,9 +439,10 @@ int stellaris_flash_command(struct flash_bank_s *bank,u8 cmd,u16 pagen)
|
||||||
|
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
/* Read device id register, main clock frequency register and fill in driver info structure */
|
/* Read device id register, main clock frequency register and fill in driver info structure */
|
||||||
int stellaris_read_part_info(struct flash_bank_s *bank)
|
static int stellaris_read_part_info(struct flash_bank_s *bank)
|
||||||
{
|
{
|
||||||
stellaris_flash_bank_t *stellaris_info = bank->driver_priv;
|
stellaris_flash_bank_t *stellaris_info = bank->driver_priv;
|
||||||
target_t *target = bank->target;
|
target_t *target = bank->target;
|
||||||
|
|
@ -515,7 +517,7 @@ int stellaris_read_part_info(struct flash_bank_s *bank)
|
||||||
* flash operations *
|
* flash operations *
|
||||||
***************************************************************************/
|
***************************************************************************/
|
||||||
|
|
||||||
int stellaris_protect_check(struct flash_bank_s *bank)
|
static int stellaris_protect_check(struct flash_bank_s *bank)
|
||||||
{
|
{
|
||||||
u32 status;
|
u32 status;
|
||||||
|
|
||||||
|
|
@ -544,7 +546,7 @@ int stellaris_protect_check(struct flash_bank_s *bank)
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
int stellaris_erase(struct flash_bank_s *bank, int first, int last)
|
static int stellaris_erase(struct flash_bank_s *bank, int first, int last)
|
||||||
{
|
{
|
||||||
int banknr;
|
int banknr;
|
||||||
u32 flash_fmc, flash_cris;
|
u32 flash_fmc, flash_cris;
|
||||||
|
|
@ -614,7 +616,7 @@ int stellaris_erase(struct flash_bank_s *bank, int first, int last)
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
int stellaris_protect(struct flash_bank_s *bank, int set, int first, int last)
|
static int stellaris_protect(struct flash_bank_s *bank, int set, int first, int last)
|
||||||
{
|
{
|
||||||
u32 fmppe, flash_fmc, flash_cris;
|
u32 fmppe, flash_fmc, flash_cris;
|
||||||
int lockregion;
|
int lockregion;
|
||||||
|
|
@ -690,7 +692,7 @@ int stellaris_protect(struct flash_bank_s *bank, int set, int first, int last)
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
u8 stellaris_write_code[] =
|
static u8 stellaris_write_code[] =
|
||||||
{
|
{
|
||||||
/*
|
/*
|
||||||
Call with :
|
Call with :
|
||||||
|
|
@ -730,7 +732,7 @@ u8 stellaris_write_code[] =
|
||||||
0x01,0x00,0x42,0xA4 /* .word 0xA4420001 */
|
0x01,0x00,0x42,0xA4 /* .word 0xA4420001 */
|
||||||
};
|
};
|
||||||
|
|
||||||
int stellaris_write_block(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 wcount)
|
static int stellaris_write_block(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 wcount)
|
||||||
{
|
{
|
||||||
target_t *target = bank->target;
|
target_t *target = bank->target;
|
||||||
u32 buffer_size = 8192;
|
u32 buffer_size = 8192;
|
||||||
|
|
@ -810,7 +812,7 @@ int stellaris_write_block(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32
|
||||||
return retval;
|
return retval;
|
||||||
}
|
}
|
||||||
|
|
||||||
int stellaris_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
|
static int stellaris_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
|
||||||
{
|
{
|
||||||
stellaris_flash_bank_t *stellaris_info = bank->driver_priv;
|
stellaris_flash_bank_t *stellaris_info = bank->driver_priv;
|
||||||
target_t *target = bank->target;
|
target_t *target = bank->target;
|
||||||
|
|
@ -945,7 +947,7 @@ int stellaris_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
int stellaris_probe(struct flash_bank_s *bank)
|
static int stellaris_probe(struct flash_bank_s *bank)
|
||||||
{
|
{
|
||||||
/* we can't probe on an stellaris
|
/* we can't probe on an stellaris
|
||||||
* if this is an stellaris, it has the configured flash
|
* if this is an stellaris, it has the configured flash
|
||||||
|
|
@ -961,7 +963,7 @@ int stellaris_probe(struct flash_bank_s *bank)
|
||||||
return stellaris_read_part_info(bank);
|
return stellaris_read_part_info(bank);
|
||||||
}
|
}
|
||||||
|
|
||||||
int stellaris_auto_probe(struct flash_bank_s *bank)
|
static int stellaris_auto_probe(struct flash_bank_s *bank)
|
||||||
{
|
{
|
||||||
stellaris_flash_bank_t *stellaris_info = bank->driver_priv;
|
stellaris_flash_bank_t *stellaris_info = bank->driver_priv;
|
||||||
if (stellaris_info->did1)
|
if (stellaris_info->did1)
|
||||||
|
|
@ -969,7 +971,7 @@ int stellaris_auto_probe(struct flash_bank_s *bank)
|
||||||
return stellaris_probe(bank);
|
return stellaris_probe(bank);
|
||||||
}
|
}
|
||||||
|
|
||||||
int stellaris_mass_erase(struct flash_bank_s *bank)
|
static int stellaris_mass_erase(struct flash_bank_s *bank)
|
||||||
{
|
{
|
||||||
target_t *target = NULL;
|
target_t *target = NULL;
|
||||||
stellaris_flash_bank_t *stellaris_info = NULL;
|
stellaris_flash_bank_t *stellaris_info = NULL;
|
||||||
|
|
@ -1029,7 +1031,7 @@ int stellaris_mass_erase(struct flash_bank_s *bank)
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
int stellaris_handle_mass_erase_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
|
static int stellaris_handle_mass_erase_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
|
||||||
{
|
{
|
||||||
flash_bank_t *bank;
|
flash_bank_t *bank;
|
||||||
int i;
|
int i;
|
||||||
|
|
|
||||||
|
|
@ -37,23 +37,23 @@
|
||||||
#include <stdlib.h>
|
#include <stdlib.h>
|
||||||
#include <string.h>
|
#include <string.h>
|
||||||
|
|
||||||
int stm32x_register_commands(struct command_context_s *cmd_ctx);
|
static int stm32x_register_commands(struct command_context_s *cmd_ctx);
|
||||||
int stm32x_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank);
|
static int stm32x_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank);
|
||||||
int stm32x_erase(struct flash_bank_s *bank, int first, int last);
|
static int stm32x_erase(struct flash_bank_s *bank, int first, int last);
|
||||||
int stm32x_protect(struct flash_bank_s *bank, int set, int first, int last);
|
static int stm32x_protect(struct flash_bank_s *bank, int set, int first, int last);
|
||||||
int stm32x_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count);
|
static int stm32x_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count);
|
||||||
int stm32x_probe(struct flash_bank_s *bank);
|
static int stm32x_probe(struct flash_bank_s *bank);
|
||||||
int stm32x_auto_probe(struct flash_bank_s *bank);
|
static int stm32x_auto_probe(struct flash_bank_s *bank);
|
||||||
int stm32x_handle_part_id_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
|
//static int stm32x_handle_part_id_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
|
||||||
int stm32x_protect_check(struct flash_bank_s *bank);
|
static int stm32x_protect_check(struct flash_bank_s *bank);
|
||||||
int stm32x_info(struct flash_bank_s *bank, char *buf, int buf_size);
|
static int stm32x_info(struct flash_bank_s *bank, char *buf, int buf_size);
|
||||||
|
|
||||||
int stm32x_handle_lock_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
|
static int stm32x_handle_lock_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
|
||||||
int stm32x_handle_unlock_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
|
static int stm32x_handle_unlock_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
|
||||||
int stm32x_handle_options_read_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
|
static int stm32x_handle_options_read_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
|
||||||
int stm32x_handle_options_write_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
|
static int stm32x_handle_options_write_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
|
||||||
int stm32x_handle_mass_erase_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
|
static int stm32x_handle_mass_erase_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
|
||||||
int stm32x_mass_erase(struct flash_bank_s *bank);
|
static int stm32x_mass_erase(struct flash_bank_s *bank);
|
||||||
|
|
||||||
flash_driver_t stm32x_flash =
|
flash_driver_t stm32x_flash =
|
||||||
{
|
{
|
||||||
|
|
@ -70,7 +70,7 @@ flash_driver_t stm32x_flash =
|
||||||
.info = stm32x_info
|
.info = stm32x_info
|
||||||
};
|
};
|
||||||
|
|
||||||
int stm32x_register_commands(struct command_context_s *cmd_ctx)
|
static int stm32x_register_commands(struct command_context_s *cmd_ctx)
|
||||||
{
|
{
|
||||||
command_t *stm32x_cmd = register_command(cmd_ctx, NULL, "stm32x", NULL, COMMAND_ANY, "stm32x flash specific commands");
|
command_t *stm32x_cmd = register_command(cmd_ctx, NULL, "stm32x", NULL, COMMAND_ANY, "stm32x flash specific commands");
|
||||||
|
|
||||||
|
|
@ -89,7 +89,7 @@ int stm32x_register_commands(struct command_context_s *cmd_ctx)
|
||||||
|
|
||||||
/* flash bank stm32x <base> <size> 0 0 <target#>
|
/* flash bank stm32x <base> <size> 0 0 <target#>
|
||||||
*/
|
*/
|
||||||
int stm32x_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank)
|
static int stm32x_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank)
|
||||||
{
|
{
|
||||||
stm32x_flash_bank_t *stm32x_info;
|
stm32x_flash_bank_t *stm32x_info;
|
||||||
|
|
||||||
|
|
@ -108,7 +108,7 @@ int stm32x_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
u32 stm32x_get_flash_status(flash_bank_t *bank)
|
static u32 stm32x_get_flash_status(flash_bank_t *bank)
|
||||||
{
|
{
|
||||||
target_t *target = bank->target;
|
target_t *target = bank->target;
|
||||||
u32 status;
|
u32 status;
|
||||||
|
|
@ -118,7 +118,7 @@ u32 stm32x_get_flash_status(flash_bank_t *bank)
|
||||||
return status;
|
return status;
|
||||||
}
|
}
|
||||||
|
|
||||||
u32 stm32x_wait_status_busy(flash_bank_t *bank, int timeout)
|
static u32 stm32x_wait_status_busy(flash_bank_t *bank, int timeout)
|
||||||
{
|
{
|
||||||
u32 status;
|
u32 status;
|
||||||
|
|
||||||
|
|
@ -132,7 +132,7 @@ u32 stm32x_wait_status_busy(flash_bank_t *bank, int timeout)
|
||||||
return status;
|
return status;
|
||||||
}
|
}
|
||||||
|
|
||||||
int stm32x_read_options(struct flash_bank_s *bank)
|
static int stm32x_read_options(struct flash_bank_s *bank)
|
||||||
{
|
{
|
||||||
u32 optiondata;
|
u32 optiondata;
|
||||||
stm32x_flash_bank_t *stm32x_info = NULL;
|
stm32x_flash_bank_t *stm32x_info = NULL;
|
||||||
|
|
@ -160,7 +160,7 @@ int stm32x_read_options(struct flash_bank_s *bank)
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
int stm32x_erase_options(struct flash_bank_s *bank)
|
static int stm32x_erase_options(struct flash_bank_s *bank)
|
||||||
{
|
{
|
||||||
stm32x_flash_bank_t *stm32x_info = NULL;
|
stm32x_flash_bank_t *stm32x_info = NULL;
|
||||||
target_t *target = bank->target;
|
target_t *target = bank->target;
|
||||||
|
|
@ -197,7 +197,7 @@ int stm32x_erase_options(struct flash_bank_s *bank)
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
int stm32x_write_options(struct flash_bank_s *bank)
|
static int stm32x_write_options(struct flash_bank_s *bank)
|
||||||
{
|
{
|
||||||
stm32x_flash_bank_t *stm32x_info = NULL;
|
stm32x_flash_bank_t *stm32x_info = NULL;
|
||||||
target_t *target = bank->target;
|
target_t *target = bank->target;
|
||||||
|
|
@ -281,7 +281,7 @@ int stm32x_write_options(struct flash_bank_s *bank)
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
int stm32x_protect_check(struct flash_bank_s *bank)
|
static int stm32x_protect_check(struct flash_bank_s *bank)
|
||||||
{
|
{
|
||||||
target_t *target = bank->target;
|
target_t *target = bank->target;
|
||||||
stm32x_flash_bank_t *stm32x_info = bank->driver_priv;
|
stm32x_flash_bank_t *stm32x_info = bank->driver_priv;
|
||||||
|
|
@ -352,7 +352,7 @@ int stm32x_protect_check(struct flash_bank_s *bank)
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
int stm32x_erase(struct flash_bank_s *bank, int first, int last)
|
static int stm32x_erase(struct flash_bank_s *bank, int first, int last)
|
||||||
{
|
{
|
||||||
target_t *target = bank->target;
|
target_t *target = bank->target;
|
||||||
int i;
|
int i;
|
||||||
|
|
@ -393,7 +393,7 @@ int stm32x_erase(struct flash_bank_s *bank, int first, int last)
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
int stm32x_protect(struct flash_bank_s *bank, int set, int first, int last)
|
static int stm32x_protect(struct flash_bank_s *bank, int set, int first, int last)
|
||||||
{
|
{
|
||||||
stm32x_flash_bank_t *stm32x_info = NULL;
|
stm32x_flash_bank_t *stm32x_info = NULL;
|
||||||
target_t *target = bank->target;
|
target_t *target = bank->target;
|
||||||
|
|
@ -480,7 +480,7 @@ int stm32x_protect(struct flash_bank_s *bank, int set, int first, int last)
|
||||||
return stm32x_write_options(bank);
|
return stm32x_write_options(bank);
|
||||||
}
|
}
|
||||||
|
|
||||||
int stm32x_write_block(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
|
static int stm32x_write_block(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
|
||||||
{
|
{
|
||||||
stm32x_flash_bank_t *stm32x_info = bank->driver_priv;
|
stm32x_flash_bank_t *stm32x_info = bank->driver_priv;
|
||||||
target_t *target = bank->target;
|
target_t *target = bank->target;
|
||||||
|
|
@ -595,7 +595,7 @@ int stm32x_write_block(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 co
|
||||||
return retval;
|
return retval;
|
||||||
}
|
}
|
||||||
|
|
||||||
int stm32x_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
|
static int stm32x_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
|
||||||
{
|
{
|
||||||
target_t *target = bank->target;
|
target_t *target = bank->target;
|
||||||
u32 words_remaining = (count / 2);
|
u32 words_remaining = (count / 2);
|
||||||
|
|
@ -704,7 +704,7 @@ int stm32x_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
int stm32x_probe(struct flash_bank_s *bank)
|
static int stm32x_probe(struct flash_bank_s *bank)
|
||||||
{
|
{
|
||||||
target_t *target = bank->target;
|
target_t *target = bank->target;
|
||||||
stm32x_flash_bank_t *stm32x_info = bank->driver_priv;
|
stm32x_flash_bank_t *stm32x_info = bank->driver_priv;
|
||||||
|
|
@ -821,7 +821,7 @@ int stm32x_probe(struct flash_bank_s *bank)
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
int stm32x_auto_probe(struct flash_bank_s *bank)
|
static int stm32x_auto_probe(struct flash_bank_s *bank)
|
||||||
{
|
{
|
||||||
stm32x_flash_bank_t *stm32x_info = bank->driver_priv;
|
stm32x_flash_bank_t *stm32x_info = bank->driver_priv;
|
||||||
if (stm32x_info->probed)
|
if (stm32x_info->probed)
|
||||||
|
|
@ -829,12 +829,14 @@ int stm32x_auto_probe(struct flash_bank_s *bank)
|
||||||
return stm32x_probe(bank);
|
return stm32x_probe(bank);
|
||||||
}
|
}
|
||||||
|
|
||||||
int stm32x_handle_part_id_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
|
#if 0
|
||||||
|
static int stm32x_handle_part_id_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
|
||||||
{
|
{
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
int stm32x_info(struct flash_bank_s *bank, char *buf, int buf_size)
|
static int stm32x_info(struct flash_bank_s *bank, char *buf, int buf_size)
|
||||||
{
|
{
|
||||||
target_t *target = bank->target;
|
target_t *target = bank->target;
|
||||||
u32 device_id;
|
u32 device_id;
|
||||||
|
|
@ -936,7 +938,7 @@ int stm32x_info(struct flash_bank_s *bank, char *buf, int buf_size)
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
int stm32x_handle_lock_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
|
static int stm32x_handle_lock_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
|
||||||
{
|
{
|
||||||
flash_bank_t *bank;
|
flash_bank_t *bank;
|
||||||
target_t *target = NULL;
|
target_t *target = NULL;
|
||||||
|
|
@ -985,7 +987,7 @@ int stm32x_handle_lock_command(struct command_context_s *cmd_ctx, char *cmd, cha
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
int stm32x_handle_unlock_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
|
static int stm32x_handle_unlock_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
|
||||||
{
|
{
|
||||||
flash_bank_t *bank;
|
flash_bank_t *bank;
|
||||||
target_t *target = NULL;
|
target_t *target = NULL;
|
||||||
|
|
@ -1031,7 +1033,7 @@ int stm32x_handle_unlock_command(struct command_context_s *cmd_ctx, char *cmd, c
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
int stm32x_handle_options_read_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
|
static int stm32x_handle_options_read_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
|
||||||
{
|
{
|
||||||
flash_bank_t *bank;
|
flash_bank_t *bank;
|
||||||
u32 optionbyte;
|
u32 optionbyte;
|
||||||
|
|
@ -1090,7 +1092,7 @@ int stm32x_handle_options_read_command(struct command_context_s *cmd_ctx, char *
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
int stm32x_handle_options_write_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
|
static int stm32x_handle_options_write_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
|
||||||
{
|
{
|
||||||
flash_bank_t *bank;
|
flash_bank_t *bank;
|
||||||
target_t *target = NULL;
|
target_t *target = NULL;
|
||||||
|
|
@ -1166,7 +1168,7 @@ int stm32x_handle_options_write_command(struct command_context_s *cmd_ctx, char
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
int stm32x_mass_erase(struct flash_bank_s *bank)
|
static int stm32x_mass_erase(struct flash_bank_s *bank)
|
||||||
{
|
{
|
||||||
target_t *target = bank->target;
|
target_t *target = bank->target;
|
||||||
u32 status;
|
u32 status;
|
||||||
|
|
@ -1204,7 +1206,7 @@ int stm32x_mass_erase(struct flash_bank_s *bank)
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
int stm32x_handle_mass_erase_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
|
static int stm32x_handle_mass_erase_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
|
||||||
{
|
{
|
||||||
flash_bank_t *bank;
|
flash_bank_t *bank;
|
||||||
int i;
|
int i;
|
||||||
|
|
|
||||||
|
|
@ -54,17 +54,17 @@ str7x_mem_layout_t mem_layout_str7bank1[] = {
|
||||||
{0x00002000, 0x02000, 0x20000}
|
{0x00002000, 0x02000, 0x20000}
|
||||||
};
|
};
|
||||||
|
|
||||||
int str7x_register_commands(struct command_context_s *cmd_ctx);
|
static int str7x_register_commands(struct command_context_s *cmd_ctx);
|
||||||
int str7x_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank);
|
static int str7x_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank);
|
||||||
int str7x_erase(struct flash_bank_s *bank, int first, int last);
|
static int str7x_erase(struct flash_bank_s *bank, int first, int last);
|
||||||
int str7x_protect(struct flash_bank_s *bank, int set, int first, int last);
|
static int str7x_protect(struct flash_bank_s *bank, int set, int first, int last);
|
||||||
int str7x_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count);
|
static int str7x_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count);
|
||||||
int str7x_probe(struct flash_bank_s *bank);
|
static int str7x_probe(struct flash_bank_s *bank);
|
||||||
int str7x_handle_part_id_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
|
//static int str7x_handle_part_id_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
|
||||||
int str7x_protect_check(struct flash_bank_s *bank);
|
static int str7x_protect_check(struct flash_bank_s *bank);
|
||||||
int str7x_info(struct flash_bank_s *bank, char *buf, int buf_size);
|
static int str7x_info(struct flash_bank_s *bank, char *buf, int buf_size);
|
||||||
|
|
||||||
int str7x_handle_disable_jtag_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
|
static int str7x_handle_disable_jtag_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
|
||||||
|
|
||||||
flash_driver_t str7x_flash =
|
flash_driver_t str7x_flash =
|
||||||
{
|
{
|
||||||
|
|
@ -81,7 +81,7 @@ flash_driver_t str7x_flash =
|
||||||
.info = str7x_info
|
.info = str7x_info
|
||||||
};
|
};
|
||||||
|
|
||||||
int str7x_register_commands(struct command_context_s *cmd_ctx)
|
static int str7x_register_commands(struct command_context_s *cmd_ctx)
|
||||||
{
|
{
|
||||||
command_t *str7x_cmd = register_command(cmd_ctx, NULL, "str7x", NULL, COMMAND_ANY, NULL);
|
command_t *str7x_cmd = register_command(cmd_ctx, NULL, "str7x", NULL, COMMAND_ANY, NULL);
|
||||||
|
|
||||||
|
|
@ -91,13 +91,13 @@ int str7x_register_commands(struct command_context_s *cmd_ctx)
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
int str7x_get_flash_adr(struct flash_bank_s *bank, u32 reg)
|
static int str7x_get_flash_adr(struct flash_bank_s *bank, u32 reg)
|
||||||
{
|
{
|
||||||
str7x_flash_bank_t *str7x_info = bank->driver_priv;
|
str7x_flash_bank_t *str7x_info = bank->driver_priv;
|
||||||
return (str7x_info->register_base | reg);
|
return (str7x_info->register_base | reg);
|
||||||
}
|
}
|
||||||
|
|
||||||
int str7x_build_block_list(struct flash_bank_s *bank)
|
static int str7x_build_block_list(struct flash_bank_s *bank)
|
||||||
{
|
{
|
||||||
str7x_flash_bank_t *str7x_info = bank->driver_priv;
|
str7x_flash_bank_t *str7x_info = bank->driver_priv;
|
||||||
|
|
||||||
|
|
@ -155,7 +155,7 @@ int str7x_build_block_list(struct flash_bank_s *bank)
|
||||||
|
|
||||||
/* flash bank str7x <base> <size> 0 0 <target#> <str71_variant>
|
/* flash bank str7x <base> <size> 0 0 <target#> <str71_variant>
|
||||||
*/
|
*/
|
||||||
int str7x_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank)
|
static int str7x_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank)
|
||||||
{
|
{
|
||||||
str7x_flash_bank_t *str7x_info;
|
str7x_flash_bank_t *str7x_info;
|
||||||
|
|
||||||
|
|
@ -200,7 +200,7 @@ int str7x_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
u32 str7x_status(struct flash_bank_s *bank)
|
static u32 str7x_status(struct flash_bank_s *bank)
|
||||||
{
|
{
|
||||||
target_t *target = bank->target;
|
target_t *target = bank->target;
|
||||||
u32 retval;
|
u32 retval;
|
||||||
|
|
@ -210,7 +210,7 @@ u32 str7x_status(struct flash_bank_s *bank)
|
||||||
return retval;
|
return retval;
|
||||||
}
|
}
|
||||||
|
|
||||||
u32 str7x_result(struct flash_bank_s *bank)
|
static u32 str7x_result(struct flash_bank_s *bank)
|
||||||
{
|
{
|
||||||
target_t *target = bank->target;
|
target_t *target = bank->target;
|
||||||
u32 retval;
|
u32 retval;
|
||||||
|
|
@ -220,7 +220,7 @@ u32 str7x_result(struct flash_bank_s *bank)
|
||||||
return retval;
|
return retval;
|
||||||
}
|
}
|
||||||
|
|
||||||
int str7x_protect_check(struct flash_bank_s *bank)
|
static int str7x_protect_check(struct flash_bank_s *bank)
|
||||||
{
|
{
|
||||||
str7x_flash_bank_t *str7x_info = bank->driver_priv;
|
str7x_flash_bank_t *str7x_info = bank->driver_priv;
|
||||||
target_t *target = bank->target;
|
target_t *target = bank->target;
|
||||||
|
|
@ -247,7 +247,7 @@ int str7x_protect_check(struct flash_bank_s *bank)
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
int str7x_erase(struct flash_bank_s *bank, int first, int last)
|
static int str7x_erase(struct flash_bank_s *bank, int first, int last)
|
||||||
{
|
{
|
||||||
str7x_flash_bank_t *str7x_info = bank->driver_priv;
|
str7x_flash_bank_t *str7x_info = bank->driver_priv;
|
||||||
target_t *target = bank->target;
|
target_t *target = bank->target;
|
||||||
|
|
@ -300,7 +300,7 @@ int str7x_erase(struct flash_bank_s *bank, int first, int last)
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
int str7x_protect(struct flash_bank_s *bank, int set, int first, int last)
|
static int str7x_protect(struct flash_bank_s *bank, int set, int first, int last)
|
||||||
{
|
{
|
||||||
str7x_flash_bank_t *str7x_info = bank->driver_priv;
|
str7x_flash_bank_t *str7x_info = bank->driver_priv;
|
||||||
target_t *target = bank->target;
|
target_t *target = bank->target;
|
||||||
|
|
@ -354,7 +354,7 @@ int str7x_protect(struct flash_bank_s *bank, int set, int first, int last)
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
int str7x_write_block(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
|
static int str7x_write_block(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
|
||||||
{
|
{
|
||||||
str7x_flash_bank_t *str7x_info = bank->driver_priv;
|
str7x_flash_bank_t *str7x_info = bank->driver_priv;
|
||||||
target_t *target = bank->target;
|
target_t *target = bank->target;
|
||||||
|
|
@ -469,7 +469,7 @@ int str7x_write_block(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 cou
|
||||||
return retval;
|
return retval;
|
||||||
}
|
}
|
||||||
|
|
||||||
int str7x_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
|
static int str7x_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
|
||||||
{
|
{
|
||||||
target_t *target = bank->target;
|
target_t *target = bank->target;
|
||||||
str7x_flash_bank_t *str7x_info = bank->driver_priv;
|
str7x_flash_bank_t *str7x_info = bank->driver_priv;
|
||||||
|
|
@ -629,23 +629,25 @@ int str7x_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
int str7x_probe(struct flash_bank_s *bank)
|
static int str7x_probe(struct flash_bank_s *bank)
|
||||||
{
|
{
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
int str7x_handle_part_id_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
|
#if 0
|
||||||
|
static int str7x_handle_part_id_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
|
||||||
{
|
{
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
int str7x_info(struct flash_bank_s *bank, char *buf, int buf_size)
|
static int str7x_info(struct flash_bank_s *bank, char *buf, int buf_size)
|
||||||
{
|
{
|
||||||
snprintf(buf, buf_size, "str7x flash driver info" );
|
snprintf(buf, buf_size, "str7x flash driver info" );
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
int str7x_handle_disable_jtag_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
|
static int str7x_handle_disable_jtag_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
|
||||||
{
|
{
|
||||||
flash_bank_t *bank;
|
flash_bank_t *bank;
|
||||||
target_t *target = NULL;
|
target_t *target = NULL;
|
||||||
|
|
|
||||||
|
|
@ -44,17 +44,17 @@
|
||||||
|
|
||||||
static u32 bank1start = 0x00080000;
|
static u32 bank1start = 0x00080000;
|
||||||
|
|
||||||
int str9x_register_commands(struct command_context_s *cmd_ctx);
|
static int str9x_register_commands(struct command_context_s *cmd_ctx);
|
||||||
int str9x_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank);
|
static int str9x_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank);
|
||||||
int str9x_erase(struct flash_bank_s *bank, int first, int last);
|
static int str9x_erase(struct flash_bank_s *bank, int first, int last);
|
||||||
int str9x_protect(struct flash_bank_s *bank, int set, int first, int last);
|
static int str9x_protect(struct flash_bank_s *bank, int set, int first, int last);
|
||||||
int str9x_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count);
|
static int str9x_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count);
|
||||||
int str9x_probe(struct flash_bank_s *bank);
|
static int str9x_probe(struct flash_bank_s *bank);
|
||||||
int str9x_handle_part_id_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
|
//static int str9x_handle_part_id_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
|
||||||
int str9x_protect_check(struct flash_bank_s *bank);
|
static int str9x_protect_check(struct flash_bank_s *bank);
|
||||||
int str9x_info(struct flash_bank_s *bank, char *buf, int buf_size);
|
static int str9x_info(struct flash_bank_s *bank, char *buf, int buf_size);
|
||||||
|
|
||||||
int str9x_handle_flash_config_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
|
static int str9x_handle_flash_config_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
|
||||||
|
|
||||||
flash_driver_t str9x_flash =
|
flash_driver_t str9x_flash =
|
||||||
{
|
{
|
||||||
|
|
@ -71,7 +71,7 @@ flash_driver_t str9x_flash =
|
||||||
.info = str9x_info
|
.info = str9x_info
|
||||||
};
|
};
|
||||||
|
|
||||||
int str9x_register_commands(struct command_context_s *cmd_ctx)
|
static int str9x_register_commands(struct command_context_s *cmd_ctx)
|
||||||
{
|
{
|
||||||
command_t *str9x_cmd = register_command(cmd_ctx, NULL, "str9x", NULL, COMMAND_ANY, NULL);
|
command_t *str9x_cmd = register_command(cmd_ctx, NULL, "str9x", NULL, COMMAND_ANY, NULL);
|
||||||
|
|
||||||
|
|
@ -81,7 +81,7 @@ int str9x_register_commands(struct command_context_s *cmd_ctx)
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
int str9x_build_block_list(struct flash_bank_s *bank)
|
static int str9x_build_block_list(struct flash_bank_s *bank)
|
||||||
{
|
{
|
||||||
str9x_flash_bank_t *str9x_info = bank->driver_priv;
|
str9x_flash_bank_t *str9x_info = bank->driver_priv;
|
||||||
|
|
||||||
|
|
@ -164,7 +164,8 @@ int str9x_build_block_list(struct flash_bank_s *bank)
|
||||||
|
|
||||||
/* flash bank str9x <base> <size> 0 0 <target#>
|
/* flash bank str9x <base> <size> 0 0 <target#>
|
||||||
*/
|
*/
|
||||||
int str9x_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank)
|
static int str9x_flash_bank_command(struct command_context_s *cmd_ctx,
|
||||||
|
char *cmd, char **args, int argc, struct flash_bank_s *bank)
|
||||||
{
|
{
|
||||||
str9x_flash_bank_t *str9x_info;
|
str9x_flash_bank_t *str9x_info;
|
||||||
|
|
||||||
|
|
@ -184,7 +185,7 @@ int str9x_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
int str9x_protect_check(struct flash_bank_s *bank)
|
static int str9x_protect_check(struct flash_bank_s *bank)
|
||||||
{
|
{
|
||||||
int retval;
|
int retval;
|
||||||
str9x_flash_bank_t *str9x_info = bank->driver_priv;
|
str9x_flash_bank_t *str9x_info = bank->driver_priv;
|
||||||
|
|
@ -259,7 +260,7 @@ int str9x_protect_check(struct flash_bank_s *bank)
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
int str9x_erase(struct flash_bank_s *bank, int first, int last)
|
static int str9x_erase(struct flash_bank_s *bank, int first, int last)
|
||||||
{
|
{
|
||||||
target_t *target = bank->target;
|
target_t *target = bank->target;
|
||||||
int i;
|
int i;
|
||||||
|
|
@ -351,7 +352,8 @@ int str9x_erase(struct flash_bank_s *bank, int first, int last)
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
int str9x_protect(struct flash_bank_s *bank, int set, int first, int last)
|
static int str9x_protect(struct flash_bank_s *bank,
|
||||||
|
int set, int first, int last)
|
||||||
{
|
{
|
||||||
target_t *target = bank->target;
|
target_t *target = bank->target;
|
||||||
int i;
|
int i;
|
||||||
|
|
@ -389,7 +391,8 @@ int str9x_protect(struct flash_bank_s *bank, int set, int first, int last)
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
int str9x_write_block(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
|
static int str9x_write_block(struct flash_bank_s *bank,
|
||||||
|
u8 *buffer, u32 offset, u32 count)
|
||||||
{
|
{
|
||||||
str9x_flash_bank_t *str9x_info = bank->driver_priv;
|
str9x_flash_bank_t *str9x_info = bank->driver_priv;
|
||||||
target_t *target = bank->target;
|
target_t *target = bank->target;
|
||||||
|
|
@ -497,7 +500,8 @@ int str9x_write_block(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 cou
|
||||||
return retval;
|
return retval;
|
||||||
}
|
}
|
||||||
|
|
||||||
int str9x_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
|
static int str9x_write(struct flash_bank_s *bank,
|
||||||
|
u8 *buffer, u32 offset, u32 count)
|
||||||
{
|
{
|
||||||
target_t *target = bank->target;
|
target_t *target = bank->target;
|
||||||
u32 words_remaining = (count / 2);
|
u32 words_remaining = (count / 2);
|
||||||
|
|
@ -654,23 +658,27 @@ int str9x_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
int str9x_probe(struct flash_bank_s *bank)
|
static int str9x_probe(struct flash_bank_s *bank)
|
||||||
{
|
{
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
int str9x_handle_part_id_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
|
#if 0
|
||||||
|
static int str9x_handle_part_id_command(struct command_context_s *cmd_ctx,
|
||||||
|
char *cmd, char **args, int argc)
|
||||||
{
|
{
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
int str9x_info(struct flash_bank_s *bank, char *buf, int buf_size)
|
static int str9x_info(struct flash_bank_s *bank, char *buf, int buf_size)
|
||||||
{
|
{
|
||||||
snprintf(buf, buf_size, "str9x flash driver info" );
|
snprintf(buf, buf_size, "str9x flash driver info" );
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
int str9x_handle_flash_config_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
|
static int str9x_handle_flash_config_command(struct command_context_s *cmd_ctx,
|
||||||
|
char *cmd, char **args, int argc)
|
||||||
{
|
{
|
||||||
str9x_flash_bank_t *str9x_info;
|
str9x_flash_bank_t *str9x_info;
|
||||||
flash_bank_t *bank;
|
flash_bank_t *bank;
|
||||||
|
|
|
||||||
|
|
@ -40,31 +40,31 @@
|
||||||
#include <unistd.h>
|
#include <unistd.h>
|
||||||
#include <getopt.h>
|
#include <getopt.h>
|
||||||
|
|
||||||
int str9xpec_register_commands(struct command_context_s *cmd_ctx);
|
static int str9xpec_register_commands(struct command_context_s *cmd_ctx);
|
||||||
int str9xpec_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank);
|
static int str9xpec_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank);
|
||||||
int str9xpec_erase(struct flash_bank_s *bank, int first, int last);
|
static int str9xpec_erase(struct flash_bank_s *bank, int first, int last);
|
||||||
int str9xpec_protect(struct flash_bank_s *bank, int set, int first, int last);
|
static int str9xpec_protect(struct flash_bank_s *bank, int set, int first, int last);
|
||||||
int str9xpec_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count);
|
static int str9xpec_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count);
|
||||||
int str9xpec_probe(struct flash_bank_s *bank);
|
static int str9xpec_probe(struct flash_bank_s *bank);
|
||||||
int str9xpec_handle_part_id_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
|
static int str9xpec_handle_part_id_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
|
||||||
int str9xpec_protect_check(struct flash_bank_s *bank);
|
static int str9xpec_protect_check(struct flash_bank_s *bank);
|
||||||
int str9xpec_erase_check(struct flash_bank_s *bank);
|
static int str9xpec_erase_check(struct flash_bank_s *bank);
|
||||||
int str9xpec_info(struct flash_bank_s *bank, char *buf, int buf_size);
|
static int str9xpec_info(struct flash_bank_s *bank, char *buf, int buf_size);
|
||||||
|
|
||||||
int str9xpec_erase_area(struct flash_bank_s *bank, int first, int last);
|
static int str9xpec_erase_area(struct flash_bank_s *bank, int first, int last);
|
||||||
int str9xpec_set_address(struct flash_bank_s *bank, u8 sector);
|
static int str9xpec_set_address(struct flash_bank_s *bank, u8 sector);
|
||||||
int str9xpec_write_options(struct flash_bank_s *bank);
|
static int str9xpec_write_options(struct flash_bank_s *bank);
|
||||||
|
|
||||||
int str9xpec_handle_flash_options_cmap_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
|
static int str9xpec_handle_flash_options_cmap_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
|
||||||
int str9xpec_handle_flash_options_lvdthd_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
|
static int str9xpec_handle_flash_options_lvdthd_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
|
||||||
int str9xpec_handle_flash_options_lvdsel_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
|
static int str9xpec_handle_flash_options_lvdsel_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
|
||||||
int str9xpec_handle_flash_options_lvdwarn_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
|
static int str9xpec_handle_flash_options_lvdwarn_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
|
||||||
int str9xpec_handle_flash_options_read_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
|
static int str9xpec_handle_flash_options_read_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
|
||||||
int str9xpec_handle_flash_options_write_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
|
static int str9xpec_handle_flash_options_write_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
|
||||||
int str9xpec_handle_flash_lock_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
|
static int str9xpec_handle_flash_lock_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
|
||||||
int str9xpec_handle_flash_unlock_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
|
static int str9xpec_handle_flash_unlock_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
|
||||||
int str9xpec_handle_flash_enable_turbo_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
|
static int str9xpec_handle_flash_enable_turbo_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
|
||||||
int str9xpec_handle_flash_disable_turbo_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
|
static int str9xpec_handle_flash_disable_turbo_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
|
||||||
|
|
||||||
flash_driver_t str9xpec_flash =
|
flash_driver_t str9xpec_flash =
|
||||||
{
|
{
|
||||||
|
|
@ -81,7 +81,7 @@ flash_driver_t str9xpec_flash =
|
||||||
.info = str9xpec_info
|
.info = str9xpec_info
|
||||||
};
|
};
|
||||||
|
|
||||||
int str9xpec_register_commands(struct command_context_s *cmd_ctx)
|
static int str9xpec_register_commands(struct command_context_s *cmd_ctx)
|
||||||
{
|
{
|
||||||
command_t *str9xpec_cmd = register_command(cmd_ctx, NULL, "str9xpec", NULL, COMMAND_ANY, "str9xpec flash specific commands");
|
command_t *str9xpec_cmd = register_command(cmd_ctx, NULL, "str9xpec", NULL, COMMAND_ANY, "str9xpec flash specific commands");
|
||||||
|
|
||||||
|
|
@ -140,7 +140,7 @@ int str9xpec_set_instr(jtag_tap_t *tap, u32 new_instr, tap_state_t end_state)
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
u8 str9xpec_isc_status(jtag_tap_t *tap)
|
static u8 str9xpec_isc_status(jtag_tap_t *tap)
|
||||||
{
|
{
|
||||||
scan_field_t field;
|
scan_field_t field;
|
||||||
u8 status;
|
u8 status;
|
||||||
|
|
@ -169,7 +169,7 @@ u8 str9xpec_isc_status(jtag_tap_t *tap)
|
||||||
return status;
|
return status;
|
||||||
}
|
}
|
||||||
|
|
||||||
int str9xpec_isc_enable(struct flash_bank_s *bank)
|
static int str9xpec_isc_enable(struct flash_bank_s *bank)
|
||||||
{
|
{
|
||||||
u8 status;
|
u8 status;
|
||||||
jtag_tap_t *tap;
|
jtag_tap_t *tap;
|
||||||
|
|
@ -196,7 +196,7 @@ int str9xpec_isc_enable(struct flash_bank_s *bank)
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
int str9xpec_isc_disable(struct flash_bank_s *bank)
|
static int str9xpec_isc_disable(struct flash_bank_s *bank)
|
||||||
{
|
{
|
||||||
u8 status;
|
u8 status;
|
||||||
jtag_tap_t *tap;
|
jtag_tap_t *tap;
|
||||||
|
|
@ -225,7 +225,7 @@ int str9xpec_isc_disable(struct flash_bank_s *bank)
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
int str9xpec_read_config(struct flash_bank_s *bank)
|
static int str9xpec_read_config(struct flash_bank_s *bank)
|
||||||
{
|
{
|
||||||
scan_field_t field;
|
scan_field_t field;
|
||||||
u8 status;
|
u8 status;
|
||||||
|
|
@ -258,7 +258,7 @@ int str9xpec_read_config(struct flash_bank_s *bank)
|
||||||
return status;
|
return status;
|
||||||
}
|
}
|
||||||
|
|
||||||
int str9xpec_build_block_list(struct flash_bank_s *bank)
|
static int str9xpec_build_block_list(struct flash_bank_s *bank)
|
||||||
{
|
{
|
||||||
str9xpec_flash_controller_t *str9xpec_info = bank->driver_priv;
|
str9xpec_flash_controller_t *str9xpec_info = bank->driver_priv;
|
||||||
|
|
||||||
|
|
@ -327,7 +327,7 @@ int str9xpec_build_block_list(struct flash_bank_s *bank)
|
||||||
|
|
||||||
/* flash bank str9x <base> <size> 0 0 <target#>
|
/* flash bank str9x <base> <size> 0 0 <target#>
|
||||||
*/
|
*/
|
||||||
int str9xpec_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank)
|
static int str9xpec_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank)
|
||||||
{
|
{
|
||||||
str9xpec_flash_controller_t *str9xpec_info;
|
str9xpec_flash_controller_t *str9xpec_info;
|
||||||
armv4_5_common_t *armv4_5 = NULL;
|
armv4_5_common_t *armv4_5 = NULL;
|
||||||
|
|
@ -361,7 +361,7 @@ int str9xpec_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, ch
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
int str9xpec_blank_check(struct flash_bank_s *bank, int first, int last)
|
static int str9xpec_blank_check(struct flash_bank_s *bank, int first, int last)
|
||||||
{
|
{
|
||||||
scan_field_t field;
|
scan_field_t field;
|
||||||
u8 status;
|
u8 status;
|
||||||
|
|
@ -438,7 +438,7 @@ int str9xpec_blank_check(struct flash_bank_s *bank, int first, int last)
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
int str9xpec_protect_check(struct flash_bank_s *bank)
|
static int str9xpec_protect_check(struct flash_bank_s *bank)
|
||||||
{
|
{
|
||||||
u8 status;
|
u8 status;
|
||||||
int i;
|
int i;
|
||||||
|
|
@ -460,7 +460,7 @@ int str9xpec_protect_check(struct flash_bank_s *bank)
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
int str9xpec_erase_area(struct flash_bank_s *bank, int first, int last)
|
static int str9xpec_erase_area(struct flash_bank_s *bank, int first, int last)
|
||||||
{
|
{
|
||||||
scan_field_t field;
|
scan_field_t field;
|
||||||
u8 status;
|
u8 status;
|
||||||
|
|
@ -535,7 +535,7 @@ int str9xpec_erase_area(struct flash_bank_s *bank, int first, int last)
|
||||||
return status;
|
return status;
|
||||||
}
|
}
|
||||||
|
|
||||||
int str9xpec_erase(struct flash_bank_s *bank, int first, int last)
|
static int str9xpec_erase(struct flash_bank_s *bank, int first, int last)
|
||||||
{
|
{
|
||||||
int status;
|
int status;
|
||||||
|
|
||||||
|
|
@ -547,7 +547,7 @@ int str9xpec_erase(struct flash_bank_s *bank, int first, int last)
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
int str9xpec_lock_device(struct flash_bank_s *bank)
|
static int str9xpec_lock_device(struct flash_bank_s *bank)
|
||||||
{
|
{
|
||||||
scan_field_t field;
|
scan_field_t field;
|
||||||
u8 status;
|
u8 status;
|
||||||
|
|
@ -594,7 +594,7 @@ int str9xpec_lock_device(struct flash_bank_s *bank)
|
||||||
return status;
|
return status;
|
||||||
}
|
}
|
||||||
|
|
||||||
int str9xpec_unlock_device(struct flash_bank_s *bank)
|
static int str9xpec_unlock_device(struct flash_bank_s *bank)
|
||||||
{
|
{
|
||||||
u8 status;
|
u8 status;
|
||||||
|
|
||||||
|
|
@ -603,7 +603,7 @@ int str9xpec_unlock_device(struct flash_bank_s *bank)
|
||||||
return status;
|
return status;
|
||||||
}
|
}
|
||||||
|
|
||||||
int str9xpec_protect(struct flash_bank_s *bank, int set, int first, int last)
|
static int str9xpec_protect(struct flash_bank_s *bank, int set, int first, int last)
|
||||||
{
|
{
|
||||||
u8 status;
|
u8 status;
|
||||||
int i;
|
int i;
|
||||||
|
|
@ -649,7 +649,7 @@ int str9xpec_protect(struct flash_bank_s *bank, int set, int first, int last)
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
int str9xpec_set_address(struct flash_bank_s *bank, u8 sector)
|
static int str9xpec_set_address(struct flash_bank_s *bank, u8 sector)
|
||||||
{
|
{
|
||||||
jtag_tap_t *tap;
|
jtag_tap_t *tap;
|
||||||
scan_field_t field;
|
scan_field_t field;
|
||||||
|
|
@ -675,7 +675,7 @@ int str9xpec_set_address(struct flash_bank_s *bank, u8 sector)
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
int str9xpec_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
|
static int str9xpec_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
|
||||||
{
|
{
|
||||||
str9xpec_flash_controller_t *str9xpec_info = bank->driver_priv;
|
str9xpec_flash_controller_t *str9xpec_info = bank->driver_priv;
|
||||||
u32 dwords_remaining = (count / 8);
|
u32 dwords_remaining = (count / 8);
|
||||||
|
|
@ -858,12 +858,12 @@ int str9xpec_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
int str9xpec_probe(struct flash_bank_s *bank)
|
static int str9xpec_probe(struct flash_bank_s *bank)
|
||||||
{
|
{
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
int str9xpec_handle_part_id_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
|
static int str9xpec_handle_part_id_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
|
||||||
{
|
{
|
||||||
flash_bank_t *bank;
|
flash_bank_t *bank;
|
||||||
scan_field_t field;
|
scan_field_t field;
|
||||||
|
|
@ -913,18 +913,18 @@ int str9xpec_handle_part_id_command(struct command_context_s *cmd_ctx, char *cmd
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
int str9xpec_erase_check(struct flash_bank_s *bank)
|
static int str9xpec_erase_check(struct flash_bank_s *bank)
|
||||||
{
|
{
|
||||||
return str9xpec_blank_check(bank, 0, bank->num_sectors - 1);
|
return str9xpec_blank_check(bank, 0, bank->num_sectors - 1);
|
||||||
}
|
}
|
||||||
|
|
||||||
int str9xpec_info(struct flash_bank_s *bank, char *buf, int buf_size)
|
static int str9xpec_info(struct flash_bank_s *bank, char *buf, int buf_size)
|
||||||
{
|
{
|
||||||
snprintf(buf, buf_size, "str9xpec flash driver info" );
|
snprintf(buf, buf_size, "str9xpec flash driver info" );
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
int str9xpec_handle_flash_options_read_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
|
static int str9xpec_handle_flash_options_read_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
|
||||||
{
|
{
|
||||||
flash_bank_t *bank;
|
flash_bank_t *bank;
|
||||||
u8 status;
|
u8 status;
|
||||||
|
|
@ -983,7 +983,7 @@ int str9xpec_handle_flash_options_read_command(struct command_context_s *cmd_ctx
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
int str9xpec_write_options(struct flash_bank_s *bank)
|
static int str9xpec_write_options(struct flash_bank_s *bank)
|
||||||
{
|
{
|
||||||
scan_field_t field;
|
scan_field_t field;
|
||||||
u8 status;
|
u8 status;
|
||||||
|
|
@ -1054,7 +1054,7 @@ int str9xpec_write_options(struct flash_bank_s *bank)
|
||||||
return status;
|
return status;
|
||||||
}
|
}
|
||||||
|
|
||||||
int str9xpec_handle_flash_options_write_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
|
static int str9xpec_handle_flash_options_write_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
|
||||||
{
|
{
|
||||||
flash_bank_t *bank;
|
flash_bank_t *bank;
|
||||||
u8 status;
|
u8 status;
|
||||||
|
|
@ -1080,7 +1080,7 @@ int str9xpec_handle_flash_options_write_command(struct command_context_s *cmd_ct
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
int str9xpec_handle_flash_options_cmap_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
|
static int str9xpec_handle_flash_options_cmap_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
|
||||||
{
|
{
|
||||||
flash_bank_t *bank;
|
flash_bank_t *bank;
|
||||||
str9xpec_flash_controller_t *str9xpec_info = NULL;
|
str9xpec_flash_controller_t *str9xpec_info = NULL;
|
||||||
|
|
@ -1112,7 +1112,7 @@ int str9xpec_handle_flash_options_cmap_command(struct command_context_s *cmd_ctx
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
int str9xpec_handle_flash_options_lvdthd_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
|
static int str9xpec_handle_flash_options_lvdthd_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
|
||||||
{
|
{
|
||||||
flash_bank_t *bank;
|
flash_bank_t *bank;
|
||||||
str9xpec_flash_controller_t *str9xpec_info = NULL;
|
str9xpec_flash_controller_t *str9xpec_info = NULL;
|
||||||
|
|
@ -1176,7 +1176,7 @@ int str9xpec_handle_flash_options_lvdsel_command(struct command_context_s *cmd_c
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
int str9xpec_handle_flash_options_lvdwarn_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
|
static int str9xpec_handle_flash_options_lvdwarn_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
|
||||||
{
|
{
|
||||||
flash_bank_t *bank;
|
flash_bank_t *bank;
|
||||||
str9xpec_flash_controller_t *str9xpec_info = NULL;
|
str9xpec_flash_controller_t *str9xpec_info = NULL;
|
||||||
|
|
@ -1208,7 +1208,7 @@ int str9xpec_handle_flash_options_lvdwarn_command(struct command_context_s *cmd_
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
int str9xpec_handle_flash_lock_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
|
static int str9xpec_handle_flash_lock_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
|
||||||
{
|
{
|
||||||
u8 status;
|
u8 status;
|
||||||
flash_bank_t *bank;
|
flash_bank_t *bank;
|
||||||
|
|
@ -1234,7 +1234,7 @@ int str9xpec_handle_flash_lock_command(struct command_context_s *cmd_ctx, char *
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
int str9xpec_handle_flash_unlock_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
|
static int str9xpec_handle_flash_unlock_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
|
||||||
{
|
{
|
||||||
u8 status;
|
u8 status;
|
||||||
flash_bank_t *bank;
|
flash_bank_t *bank;
|
||||||
|
|
@ -1260,7 +1260,7 @@ int str9xpec_handle_flash_unlock_command(struct command_context_s *cmd_ctx, char
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
int str9xpec_handle_flash_enable_turbo_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
|
static int str9xpec_handle_flash_enable_turbo_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
|
||||||
{
|
{
|
||||||
int retval;
|
int retval;
|
||||||
flash_bank_t *bank;
|
flash_bank_t *bank;
|
||||||
|
|
@ -1313,7 +1313,7 @@ int str9xpec_handle_flash_enable_turbo_command(struct command_context_s *cmd_ctx
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
int str9xpec_handle_flash_disable_turbo_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
|
static int str9xpec_handle_flash_disable_turbo_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
|
||||||
{
|
{
|
||||||
flash_bank_t *bank;
|
flash_bank_t *bank;
|
||||||
jtag_tap_t *tap;
|
jtag_tap_t *tap;
|
||||||
|
|
|
||||||
|
|
@ -26,16 +26,16 @@
|
||||||
#include <string.h>
|
#include <string.h>
|
||||||
#include <unistd.h>
|
#include <unistd.h>
|
||||||
|
|
||||||
int tms470_register_commands(struct command_context_s *cmd_ctx);
|
static int tms470_register_commands(struct command_context_s *cmd_ctx);
|
||||||
int tms470_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank);
|
static int tms470_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank);
|
||||||
int tms470_erase(struct flash_bank_s *bank, int first, int last);
|
static int tms470_erase(struct flash_bank_s *bank, int first, int last);
|
||||||
int tms470_protect(struct flash_bank_s *bank, int set, int first, int last);
|
static int tms470_protect(struct flash_bank_s *bank, int set, int first, int last);
|
||||||
int tms470_write(struct flash_bank_s *bank, u8 * buffer, u32 offset, u32 count);
|
static int tms470_write(struct flash_bank_s *bank, u8 * buffer, u32 offset, u32 count);
|
||||||
int tms470_probe(struct flash_bank_s *bank);
|
static int tms470_probe(struct flash_bank_s *bank);
|
||||||
int tms470_auto_probe(struct flash_bank_s *bank);
|
static int tms470_auto_probe(struct flash_bank_s *bank);
|
||||||
int tms470_erase_check(struct flash_bank_s *bank);
|
static int tms470_erase_check(struct flash_bank_s *bank);
|
||||||
int tms470_protect_check(struct flash_bank_s *bank);
|
static int tms470_protect_check(struct flash_bank_s *bank);
|
||||||
int tms470_info(struct flash_bank_s *bank, char *buf, int buf_size);
|
static int tms470_info(struct flash_bank_s *bank, char *buf, int buf_size);
|
||||||
|
|
||||||
flash_driver_t tms470_flash = {
|
flash_driver_t tms470_flash = {
|
||||||
.name = "tms470",
|
.name = "tms470",
|
||||||
|
|
@ -133,7 +133,7 @@ const flash_sector_t TMS470R1A384_BANK2_SECTORS[] = {
|
||||||
|
|
||||||
/* ---------------------------------------------------------------------- */
|
/* ---------------------------------------------------------------------- */
|
||||||
|
|
||||||
int tms470_read_part_info(struct flash_bank_s *bank)
|
static int tms470_read_part_info(struct flash_bank_s *bank)
|
||||||
{
|
{
|
||||||
tms470_flash_bank_t *tms470_info = bank->driver_priv;
|
tms470_flash_bank_t *tms470_info = bank->driver_priv;
|
||||||
target_t *target = bank->target;
|
target_t *target = bank->target;
|
||||||
|
|
@ -309,10 +309,10 @@ int tms470_read_part_info(struct flash_bank_s *bank)
|
||||||
|
|
||||||
/* ---------------------------------------------------------------------- */
|
/* ---------------------------------------------------------------------- */
|
||||||
|
|
||||||
u32 keysSet = 0;
|
static u32 keysSet = 0;
|
||||||
u32 flashKeys[4];
|
static u32 flashKeys[4];
|
||||||
|
|
||||||
int tms470_handle_flash_keyset_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
|
static int tms470_handle_flash_keyset_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
|
||||||
{
|
{
|
||||||
if (argc > 4)
|
if (argc > 4)
|
||||||
{
|
{
|
||||||
|
|
@ -355,27 +355,27 @@ int tms470_handle_flash_keyset_command(struct command_context_s *cmd_ctx, char *
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
const u32 FLASH_KEYS_ALL_ONES[] = { 0xFFFFFFFF, 0xFFFFFFFF,
|
static const u32 FLASH_KEYS_ALL_ONES[] = { 0xFFFFFFFF, 0xFFFFFFFF,
|
||||||
0xFFFFFFFF, 0xFFFFFFFF,
|
0xFFFFFFFF, 0xFFFFFFFF,
|
||||||
};
|
};
|
||||||
|
|
||||||
const u32 FLASH_KEYS_ALL_ZEROS[] = { 0x00000000, 0x00000000,
|
static const u32 FLASH_KEYS_ALL_ZEROS[] = { 0x00000000, 0x00000000,
|
||||||
0x00000000, 0x00000000,
|
0x00000000, 0x00000000,
|
||||||
};
|
};
|
||||||
|
|
||||||
const u32 FLASH_KEYS_MIX1[] = { 0xf0fff0ff, 0xf0fff0ff,
|
static const u32 FLASH_KEYS_MIX1[] = { 0xf0fff0ff, 0xf0fff0ff,
|
||||||
0xf0fff0ff, 0xf0fff0ff
|
0xf0fff0ff, 0xf0fff0ff
|
||||||
};
|
};
|
||||||
|
|
||||||
const u32 FLASH_KEYS_MIX2[] = { 0x0000ffff, 0x0000ffff,
|
static const u32 FLASH_KEYS_MIX2[] = { 0x0000ffff, 0x0000ffff,
|
||||||
0x0000ffff, 0x0000ffff
|
0x0000ffff, 0x0000ffff
|
||||||
};
|
};
|
||||||
|
|
||||||
/* ---------------------------------------------------------------------- */
|
/* ---------------------------------------------------------------------- */
|
||||||
|
|
||||||
int oscMHz = 12;
|
static int oscMHz = 12;
|
||||||
|
|
||||||
int tms470_handle_osc_megahertz_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
|
static int tms470_handle_osc_megahertz_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
|
||||||
{
|
{
|
||||||
if (argc > 1)
|
if (argc > 1)
|
||||||
{
|
{
|
||||||
|
|
@ -402,9 +402,9 @@ int tms470_handle_osc_megahertz_command(struct command_context_s *cmd_ctx, char
|
||||||
|
|
||||||
/* ---------------------------------------------------------------------- */
|
/* ---------------------------------------------------------------------- */
|
||||||
|
|
||||||
int plldis = 0;
|
static int plldis = 0;
|
||||||
|
|
||||||
int tms470_handle_plldis_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
|
static int tms470_handle_plldis_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
|
||||||
{
|
{
|
||||||
if (argc > 1)
|
if (argc > 1)
|
||||||
{
|
{
|
||||||
|
|
@ -424,7 +424,7 @@ int tms470_handle_plldis_command(struct command_context_s *cmd_ctx, char *cmd, c
|
||||||
|
|
||||||
/* ---------------------------------------------------------------------- */
|
/* ---------------------------------------------------------------------- */
|
||||||
|
|
||||||
int tms470_check_flash_unlocked(target_t * target)
|
static int tms470_check_flash_unlocked(target_t * target)
|
||||||
{
|
{
|
||||||
u32 fmbbusy;
|
u32 fmbbusy;
|
||||||
|
|
||||||
|
|
@ -435,7 +435,7 @@ int tms470_check_flash_unlocked(target_t * target)
|
||||||
|
|
||||||
/* ---------------------------------------------------------------------- */
|
/* ---------------------------------------------------------------------- */
|
||||||
|
|
||||||
int tms470_try_flash_keys(target_t * target, const u32 * key_set)
|
static int tms470_try_flash_keys(target_t * target, const u32 * key_set)
|
||||||
{
|
{
|
||||||
u32 glbctrl, fmmstat;
|
u32 glbctrl, fmmstat;
|
||||||
int retval = ERROR_FLASH_OPERATION_FAILED;
|
int retval = ERROR_FLASH_OPERATION_FAILED;
|
||||||
|
|
@ -513,7 +513,7 @@ int tms470_try_flash_keys(target_t * target, const u32 * key_set)
|
||||||
|
|
||||||
/* ---------------------------------------------------------------------- */
|
/* ---------------------------------------------------------------------- */
|
||||||
|
|
||||||
int tms470_unlock_flash(struct flash_bank_s *bank)
|
static int tms470_unlock_flash(struct flash_bank_s *bank)
|
||||||
{
|
{
|
||||||
target_t *target = bank->target;
|
target_t *target = bank->target;
|
||||||
const u32 *p_key_sets[5];
|
const u32 *p_key_sets[5];
|
||||||
|
|
@ -552,7 +552,7 @@ int tms470_unlock_flash(struct flash_bank_s *bank)
|
||||||
|
|
||||||
/* ---------------------------------------------------------------------- */
|
/* ---------------------------------------------------------------------- */
|
||||||
|
|
||||||
int tms470_flash_initialize_internal_state_machine(struct flash_bank_s *bank)
|
static int tms470_flash_initialize_internal_state_machine(struct flash_bank_s *bank)
|
||||||
{
|
{
|
||||||
u32 fmmac2, fmmac1, fmmaxep, k, delay, glbctrl, sysclk;
|
u32 fmmac2, fmmac1, fmmaxep, k, delay, glbctrl, sysclk;
|
||||||
target_t *target = bank->target;
|
target_t *target = bank->target;
|
||||||
|
|
@ -744,7 +744,7 @@ int tms470_flash_status(struct flash_bank_s *bank)
|
||||||
|
|
||||||
/* ---------------------------------------------------------------------- */
|
/* ---------------------------------------------------------------------- */
|
||||||
|
|
||||||
int tms470_erase_sector(struct flash_bank_s *bank, int sector)
|
static int tms470_erase_sector(struct flash_bank_s *bank, int sector)
|
||||||
{
|
{
|
||||||
u32 glbctrl, orig_fmregopt, fmbsea, fmbseb, fmmstat;
|
u32 glbctrl, orig_fmregopt, fmbsea, fmbseb, fmmstat;
|
||||||
target_t *target = bank->target;
|
target_t *target = bank->target;
|
||||||
|
|
@ -839,7 +839,7 @@ int tms470_erase_sector(struct flash_bank_s *bank, int sector)
|
||||||
Implementation of Flash Driver Interfaces
|
Implementation of Flash Driver Interfaces
|
||||||
---------------------------------------------------------------------- */
|
---------------------------------------------------------------------- */
|
||||||
|
|
||||||
int tms470_register_commands(struct command_context_s *cmd_ctx)
|
static int tms470_register_commands(struct command_context_s *cmd_ctx)
|
||||||
{
|
{
|
||||||
command_t *tms470_cmd = register_command(cmd_ctx, NULL, "tms470", NULL, COMMAND_ANY, "applies to TI tms470 family");
|
command_t *tms470_cmd = register_command(cmd_ctx, NULL, "tms470", NULL, COMMAND_ANY, "applies to TI tms470 family");
|
||||||
|
|
||||||
|
|
@ -852,7 +852,7 @@ int tms470_register_commands(struct command_context_s *cmd_ctx)
|
||||||
|
|
||||||
/* ---------------------------------------------------------------------- */
|
/* ---------------------------------------------------------------------- */
|
||||||
|
|
||||||
int tms470_erase(struct flash_bank_s *bank, int first, int last)
|
static int tms470_erase(struct flash_bank_s *bank, int first, int last)
|
||||||
{
|
{
|
||||||
tms470_flash_bank_t *tms470_info = bank->driver_priv;
|
tms470_flash_bank_t *tms470_info = bank->driver_priv;
|
||||||
int sector, result = ERROR_OK;
|
int sector, result = ERROR_OK;
|
||||||
|
|
@ -899,7 +899,7 @@ int tms470_erase(struct flash_bank_s *bank, int first, int last)
|
||||||
|
|
||||||
/* ---------------------------------------------------------------------- */
|
/* ---------------------------------------------------------------------- */
|
||||||
|
|
||||||
int tms470_protect(struct flash_bank_s *bank, int set, int first, int last)
|
static int tms470_protect(struct flash_bank_s *bank, int set, int first, int last)
|
||||||
{
|
{
|
||||||
tms470_flash_bank_t *tms470_info = bank->driver_priv;
|
tms470_flash_bank_t *tms470_info = bank->driver_priv;
|
||||||
target_t *target = bank->target;
|
target_t *target = bank->target;
|
||||||
|
|
@ -951,7 +951,7 @@ int tms470_protect(struct flash_bank_s *bank, int set, int first, int last)
|
||||||
|
|
||||||
/* ---------------------------------------------------------------------- */
|
/* ---------------------------------------------------------------------- */
|
||||||
|
|
||||||
int tms470_write(struct flash_bank_s *bank, u8 * buffer, u32 offset, u32 count)
|
static int tms470_write(struct flash_bank_s *bank, u8 * buffer, u32 offset, u32 count)
|
||||||
{
|
{
|
||||||
target_t *target = bank->target;
|
target_t *target = bank->target;
|
||||||
u32 glbctrl, fmbac2, orig_fmregopt, fmbsea, fmbseb, fmmaxpp, fmmstat;
|
u32 glbctrl, fmbac2, orig_fmregopt, fmbsea, fmbseb, fmmaxpp, fmmstat;
|
||||||
|
|
@ -1048,7 +1048,7 @@ int tms470_write(struct flash_bank_s *bank, u8 * buffer, u32 offset, u32 count)
|
||||||
|
|
||||||
/* ---------------------------------------------------------------------- */
|
/* ---------------------------------------------------------------------- */
|
||||||
|
|
||||||
int tms470_probe(struct flash_bank_s *bank)
|
static int tms470_probe(struct flash_bank_s *bank)
|
||||||
{
|
{
|
||||||
if (bank->target->state != TARGET_HALTED)
|
if (bank->target->state != TARGET_HALTED)
|
||||||
{
|
{
|
||||||
|
|
@ -1059,7 +1059,7 @@ int tms470_probe(struct flash_bank_s *bank)
|
||||||
return tms470_read_part_info(bank);
|
return tms470_read_part_info(bank);
|
||||||
}
|
}
|
||||||
|
|
||||||
int tms470_auto_probe(struct flash_bank_s *bank)
|
static int tms470_auto_probe(struct flash_bank_s *bank)
|
||||||
{
|
{
|
||||||
tms470_flash_bank_t *tms470_info = bank->driver_priv;
|
tms470_flash_bank_t *tms470_info = bank->driver_priv;
|
||||||
|
|
||||||
|
|
@ -1070,7 +1070,7 @@ int tms470_auto_probe(struct flash_bank_s *bank)
|
||||||
|
|
||||||
/* ---------------------------------------------------------------------- */
|
/* ---------------------------------------------------------------------- */
|
||||||
|
|
||||||
int tms470_erase_check(struct flash_bank_s *bank)
|
static int tms470_erase_check(struct flash_bank_s *bank)
|
||||||
{
|
{
|
||||||
target_t *target = bank->target;
|
target_t *target = bank->target;
|
||||||
tms470_flash_bank_t *tms470_info = bank->driver_priv;
|
tms470_flash_bank_t *tms470_info = bank->driver_priv;
|
||||||
|
|
@ -1161,7 +1161,7 @@ int tms470_erase_check(struct flash_bank_s *bank)
|
||||||
|
|
||||||
/* ---------------------------------------------------------------------- */
|
/* ---------------------------------------------------------------------- */
|
||||||
|
|
||||||
int tms470_protect_check(struct flash_bank_s *bank)
|
static int tms470_protect_check(struct flash_bank_s *bank)
|
||||||
{
|
{
|
||||||
target_t *target = bank->target;
|
target_t *target = bank->target;
|
||||||
tms470_flash_bank_t *tms470_info = bank->driver_priv;
|
tms470_flash_bank_t *tms470_info = bank->driver_priv;
|
||||||
|
|
@ -1209,7 +1209,7 @@ int tms470_protect_check(struct flash_bank_s *bank)
|
||||||
|
|
||||||
/* ---------------------------------------------------------------------- */
|
/* ---------------------------------------------------------------------- */
|
||||||
|
|
||||||
int tms470_info(struct flash_bank_s *bank, char *buf, int buf_size)
|
static int tms470_info(struct flash_bank_s *bank, char *buf, int buf_size)
|
||||||
{
|
{
|
||||||
int used = 0;
|
int used = 0;
|
||||||
tms470_flash_bank_t *tms470_info = bank->driver_priv;
|
tms470_flash_bank_t *tms470_info = bank->driver_priv;
|
||||||
|
|
@ -1243,7 +1243,7 @@ int tms470_info(struct flash_bank_s *bank, char *buf, int buf_size)
|
||||||
* [options...]
|
* [options...]
|
||||||
*/
|
*/
|
||||||
|
|
||||||
int tms470_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank)
|
static int tms470_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank)
|
||||||
{
|
{
|
||||||
bank->driver_priv = malloc(sizeof(tms470_flash_bank_t));
|
bank->driver_priv = malloc(sizeof(tms470_flash_bank_t));
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -455,7 +455,7 @@ int Jim_Command_drscan(Jim_Interp *interp, int argc, Jim_Obj *const *args)
|
||||||
fields[field_count++].in_handler_priv = NULL;
|
fields[field_count++].in_handler_priv = NULL;
|
||||||
}
|
}
|
||||||
|
|
||||||
jtag_add_dr_scan(num_fields, fields, -1);
|
jtag_add_dr_scan(num_fields, fields, TAP_INVALID);
|
||||||
retval = jtag_execute_queue();
|
retval = jtag_execute_queue();
|
||||||
if (retval != ERROR_OK)
|
if (retval != ERROR_OK)
|
||||||
{
|
{
|
||||||
|
|
|
||||||
|
|
@ -346,7 +346,7 @@ int amt_jtagaccel_execute_queue(void)
|
||||||
#ifdef _DEBUG_JTAG_IO_
|
#ifdef _DEBUG_JTAG_IO_
|
||||||
LOG_DEBUG("end_state: %i", cmd->cmd.end_state->end_state);
|
LOG_DEBUG("end_state: %i", cmd->cmd.end_state->end_state);
|
||||||
#endif
|
#endif
|
||||||
if (cmd->cmd.end_state->end_state != -1)
|
if (cmd->cmd.end_state->end_state != TAP_INVALID)
|
||||||
amt_jtagaccel_end_state(cmd->cmd.end_state->end_state);
|
amt_jtagaccel_end_state(cmd->cmd.end_state->end_state);
|
||||||
break;
|
break;
|
||||||
case JTAG_RESET:
|
case JTAG_RESET:
|
||||||
|
|
@ -363,7 +363,7 @@ int amt_jtagaccel_execute_queue(void)
|
||||||
#ifdef _DEBUG_JTAG_IO_
|
#ifdef _DEBUG_JTAG_IO_
|
||||||
LOG_DEBUG("runtest %i cycles, end in %i", cmd->cmd.runtest->num_cycles, cmd->cmd.runtest->end_state);
|
LOG_DEBUG("runtest %i cycles, end in %i", cmd->cmd.runtest->num_cycles, cmd->cmd.runtest->end_state);
|
||||||
#endif
|
#endif
|
||||||
if (cmd->cmd.runtest->end_state != -1)
|
if (cmd->cmd.runtest->end_state != TAP_INVALID)
|
||||||
amt_jtagaccel_end_state(cmd->cmd.runtest->end_state);
|
amt_jtagaccel_end_state(cmd->cmd.runtest->end_state);
|
||||||
amt_jtagaccel_runtest(cmd->cmd.runtest->num_cycles);
|
amt_jtagaccel_runtest(cmd->cmd.runtest->num_cycles);
|
||||||
break;
|
break;
|
||||||
|
|
@ -371,7 +371,7 @@ int amt_jtagaccel_execute_queue(void)
|
||||||
#ifdef _DEBUG_JTAG_IO_
|
#ifdef _DEBUG_JTAG_IO_
|
||||||
LOG_DEBUG("statemove end in %i", cmd->cmd.statemove->end_state);
|
LOG_DEBUG("statemove end in %i", cmd->cmd.statemove->end_state);
|
||||||
#endif
|
#endif
|
||||||
if (cmd->cmd.statemove->end_state != -1)
|
if (cmd->cmd.statemove->end_state != TAP_INVALID)
|
||||||
amt_jtagaccel_end_state(cmd->cmd.statemove->end_state);
|
amt_jtagaccel_end_state(cmd->cmd.statemove->end_state);
|
||||||
amt_jtagaccel_state_move();
|
amt_jtagaccel_state_move();
|
||||||
break;
|
break;
|
||||||
|
|
@ -379,7 +379,7 @@ int amt_jtagaccel_execute_queue(void)
|
||||||
#ifdef _DEBUG_JTAG_IO_
|
#ifdef _DEBUG_JTAG_IO_
|
||||||
LOG_DEBUG("scan end in %i", cmd->cmd.scan->end_state);
|
LOG_DEBUG("scan end in %i", cmd->cmd.scan->end_state);
|
||||||
#endif
|
#endif
|
||||||
if (cmd->cmd.scan->end_state != -1)
|
if (cmd->cmd.scan->end_state != TAP_INVALID)
|
||||||
amt_jtagaccel_end_state(cmd->cmd.scan->end_state);
|
amt_jtagaccel_end_state(cmd->cmd.scan->end_state);
|
||||||
scan_size = jtag_build_buffer(cmd->cmd.scan, &buffer);
|
scan_size = jtag_build_buffer(cmd->cmd.scan, &buffer);
|
||||||
type = jtag_scan_type(cmd->cmd.scan);
|
type = jtag_scan_type(cmd->cmd.scan);
|
||||||
|
|
|
||||||
|
|
@ -156,7 +156,7 @@ int armjtagew_execute_queue(void)
|
||||||
case JTAG_END_STATE:
|
case JTAG_END_STATE:
|
||||||
DEBUG_JTAG_IO("end_state: %i", cmd->cmd.end_state->end_state);
|
DEBUG_JTAG_IO("end_state: %i", cmd->cmd.end_state->end_state);
|
||||||
|
|
||||||
if (cmd->cmd.end_state->end_state != -1)
|
if (cmd->cmd.end_state->end_state != TAP_INVALID)
|
||||||
{
|
{
|
||||||
armjtagew_end_state(cmd->cmd.end_state->end_state);
|
armjtagew_end_state(cmd->cmd.end_state->end_state);
|
||||||
}
|
}
|
||||||
|
|
@ -166,7 +166,7 @@ int armjtagew_execute_queue(void)
|
||||||
DEBUG_JTAG_IO( "runtest %i cycles, end in %i", cmd->cmd.runtest->num_cycles, \
|
DEBUG_JTAG_IO( "runtest %i cycles, end in %i", cmd->cmd.runtest->num_cycles, \
|
||||||
cmd->cmd.runtest->end_state);
|
cmd->cmd.runtest->end_state);
|
||||||
|
|
||||||
if (cmd->cmd.runtest->end_state != -1)
|
if (cmd->cmd.runtest->end_state != TAP_INVALID)
|
||||||
{
|
{
|
||||||
armjtagew_end_state(cmd->cmd.runtest->end_state);
|
armjtagew_end_state(cmd->cmd.runtest->end_state);
|
||||||
}
|
}
|
||||||
|
|
@ -176,7 +176,7 @@ int armjtagew_execute_queue(void)
|
||||||
case JTAG_STATEMOVE:
|
case JTAG_STATEMOVE:
|
||||||
DEBUG_JTAG_IO("statemove end in %i", cmd->cmd.statemove->end_state);
|
DEBUG_JTAG_IO("statemove end in %i", cmd->cmd.statemove->end_state);
|
||||||
|
|
||||||
if (cmd->cmd.statemove->end_state != -1)
|
if (cmd->cmd.statemove->end_state != TAP_INVALID)
|
||||||
{
|
{
|
||||||
armjtagew_end_state(cmd->cmd.statemove->end_state);
|
armjtagew_end_state(cmd->cmd.statemove->end_state);
|
||||||
}
|
}
|
||||||
|
|
@ -194,7 +194,7 @@ int armjtagew_execute_queue(void)
|
||||||
case JTAG_SCAN:
|
case JTAG_SCAN:
|
||||||
DEBUG_JTAG_IO("scan end in %i", cmd->cmd.scan->end_state);
|
DEBUG_JTAG_IO("scan end in %i", cmd->cmd.scan->end_state);
|
||||||
|
|
||||||
if (cmd->cmd.scan->end_state != -1)
|
if (cmd->cmd.scan->end_state != TAP_INVALID)
|
||||||
{
|
{
|
||||||
armjtagew_end_state(cmd->cmd.scan->end_state);
|
armjtagew_end_state(cmd->cmd.scan->end_state);
|
||||||
}
|
}
|
||||||
|
|
|
||||||
|
|
@ -278,7 +278,7 @@ int bitbang_execute_queue(void)
|
||||||
#ifdef _DEBUG_JTAG_IO_
|
#ifdef _DEBUG_JTAG_IO_
|
||||||
LOG_DEBUG("end_state: %s", tap_state_name(cmd->cmd.end_state->end_state) );
|
LOG_DEBUG("end_state: %s", tap_state_name(cmd->cmd.end_state->end_state) );
|
||||||
#endif
|
#endif
|
||||||
if (cmd->cmd.end_state->end_state != -1)
|
if (cmd->cmd.end_state->end_state != TAP_INVALID)
|
||||||
bitbang_end_state(cmd->cmd.end_state->end_state);
|
bitbang_end_state(cmd->cmd.end_state->end_state);
|
||||||
break;
|
break;
|
||||||
case JTAG_RESET:
|
case JTAG_RESET:
|
||||||
|
|
@ -295,7 +295,7 @@ int bitbang_execute_queue(void)
|
||||||
#ifdef _DEBUG_JTAG_IO_
|
#ifdef _DEBUG_JTAG_IO_
|
||||||
LOG_DEBUG("runtest %i cycles, end in %s", cmd->cmd.runtest->num_cycles, tap_state_name(cmd->cmd.runtest->end_state) );
|
LOG_DEBUG("runtest %i cycles, end in %s", cmd->cmd.runtest->num_cycles, tap_state_name(cmd->cmd.runtest->end_state) );
|
||||||
#endif
|
#endif
|
||||||
if (cmd->cmd.runtest->end_state != -1)
|
if (cmd->cmd.runtest->end_state != TAP_INVALID)
|
||||||
bitbang_end_state(cmd->cmd.runtest->end_state);
|
bitbang_end_state(cmd->cmd.runtest->end_state);
|
||||||
bitbang_runtest(cmd->cmd.runtest->num_cycles);
|
bitbang_runtest(cmd->cmd.runtest->num_cycles);
|
||||||
break;
|
break;
|
||||||
|
|
@ -311,7 +311,7 @@ int bitbang_execute_queue(void)
|
||||||
#ifdef _DEBUG_JTAG_IO_
|
#ifdef _DEBUG_JTAG_IO_
|
||||||
LOG_DEBUG("statemove end in %s", tap_state_name(cmd->cmd.statemove->end_state));
|
LOG_DEBUG("statemove end in %s", tap_state_name(cmd->cmd.statemove->end_state));
|
||||||
#endif
|
#endif
|
||||||
if (cmd->cmd.statemove->end_state != -1)
|
if (cmd->cmd.statemove->end_state != TAP_INVALID)
|
||||||
bitbang_end_state(cmd->cmd.statemove->end_state);
|
bitbang_end_state(cmd->cmd.statemove->end_state);
|
||||||
bitbang_state_move();
|
bitbang_state_move();
|
||||||
break;
|
break;
|
||||||
|
|
@ -326,7 +326,7 @@ int bitbang_execute_queue(void)
|
||||||
#ifdef _DEBUG_JTAG_IO_
|
#ifdef _DEBUG_JTAG_IO_
|
||||||
LOG_DEBUG("%s scan end in %s", (cmd->cmd.scan->ir_scan) ? "IR" : "DR", tap_state_name(cmd->cmd.scan->end_state) );
|
LOG_DEBUG("%s scan end in %s", (cmd->cmd.scan->ir_scan) ? "IR" : "DR", tap_state_name(cmd->cmd.scan->end_state) );
|
||||||
#endif
|
#endif
|
||||||
if (cmd->cmd.scan->end_state != -1)
|
if (cmd->cmd.scan->end_state != TAP_INVALID)
|
||||||
bitbang_end_state(cmd->cmd.scan->end_state);
|
bitbang_end_state(cmd->cmd.scan->end_state);
|
||||||
scan_size = jtag_build_buffer(cmd->cmd.scan, &buffer);
|
scan_size = jtag_build_buffer(cmd->cmd.scan, &buffer);
|
||||||
type = jtag_scan_type(cmd->cmd.scan);
|
type = jtag_scan_type(cmd->cmd.scan);
|
||||||
|
|
|
||||||
|
|
@ -153,7 +153,7 @@ void bitq_io(int tms, int tdi, int tdo_req)
|
||||||
|
|
||||||
void bitq_end_state(tap_state_t state)
|
void bitq_end_state(tap_state_t state)
|
||||||
{
|
{
|
||||||
if (state==-1)
|
if (state==TAP_INVALID)
|
||||||
return;
|
return;
|
||||||
|
|
||||||
if (!tap_is_state_stable(state))
|
if (!tap_is_state_stable(state))
|
||||||
|
|
|
||||||
|
|
@ -1308,7 +1308,7 @@ int ft2232_execute_queue()
|
||||||
switch (cmd->type)
|
switch (cmd->type)
|
||||||
{
|
{
|
||||||
case JTAG_END_STATE:
|
case JTAG_END_STATE:
|
||||||
if (cmd->cmd.end_state->end_state != -1)
|
if (cmd->cmd.end_state->end_state != TAP_INVALID)
|
||||||
ft2232_end_state(cmd->cmd.end_state->end_state);
|
ft2232_end_state(cmd->cmd.end_state->end_state);
|
||||||
break;
|
break;
|
||||||
|
|
||||||
|
|
@ -1341,9 +1341,9 @@ int ft2232_execute_queue()
|
||||||
if (tap_get_state() != TAP_IDLE)
|
if (tap_get_state() != TAP_IDLE)
|
||||||
predicted_size += 3;
|
predicted_size += 3;
|
||||||
predicted_size += 3 * CEIL(cmd->cmd.runtest->num_cycles, 7);
|
predicted_size += 3 * CEIL(cmd->cmd.runtest->num_cycles, 7);
|
||||||
if ( (cmd->cmd.runtest->end_state != -1) && (cmd->cmd.runtest->end_state != TAP_IDLE) )
|
if ( (cmd->cmd.runtest->end_state != TAP_INVALID) && (cmd->cmd.runtest->end_state != TAP_IDLE) )
|
||||||
predicted_size += 3;
|
predicted_size += 3;
|
||||||
if ( (cmd->cmd.runtest->end_state == -1) && (tap_get_end_state() != TAP_IDLE) )
|
if ( (cmd->cmd.runtest->end_state == TAP_INVALID) && (tap_get_end_state() != TAP_IDLE) )
|
||||||
predicted_size += 3;
|
predicted_size += 3;
|
||||||
if (ft2232_buffer_size + predicted_size + 1 > FT2232_BUFFER_SIZE)
|
if (ft2232_buffer_size + predicted_size + 1 > FT2232_BUFFER_SIZE)
|
||||||
{
|
{
|
||||||
|
|
@ -1379,7 +1379,7 @@ int ft2232_execute_queue()
|
||||||
/* LOG_DEBUG("added TMS scan (no read)"); */
|
/* LOG_DEBUG("added TMS scan (no read)"); */
|
||||||
}
|
}
|
||||||
|
|
||||||
if (cmd->cmd.runtest->end_state != -1)
|
if (cmd->cmd.runtest->end_state != TAP_INVALID)
|
||||||
ft2232_end_state(cmd->cmd.runtest->end_state);
|
ft2232_end_state(cmd->cmd.runtest->end_state);
|
||||||
|
|
||||||
if ( tap_get_state() != tap_get_end_state() )
|
if ( tap_get_state() != tap_get_end_state() )
|
||||||
|
|
@ -1409,7 +1409,7 @@ int ft2232_execute_queue()
|
||||||
require_send = 0;
|
require_send = 0;
|
||||||
first_unsent = cmd;
|
first_unsent = cmd;
|
||||||
}
|
}
|
||||||
if (cmd->cmd.statemove->end_state != -1)
|
if (cmd->cmd.statemove->end_state != TAP_INVALID)
|
||||||
ft2232_end_state(cmd->cmd.statemove->end_state);
|
ft2232_end_state(cmd->cmd.statemove->end_state);
|
||||||
|
|
||||||
/* command "Clock Data to TMS/CS Pin (no Read)" */
|
/* command "Clock Data to TMS/CS Pin (no Read)" */
|
||||||
|
|
@ -1458,7 +1458,7 @@ int ft2232_execute_queue()
|
||||||
retval = ERROR_JTAG_QUEUE_FAILED;
|
retval = ERROR_JTAG_QUEUE_FAILED;
|
||||||
|
|
||||||
/* current command */
|
/* current command */
|
||||||
if (cmd->cmd.scan->end_state != -1)
|
if (cmd->cmd.scan->end_state != TAP_INVALID)
|
||||||
ft2232_end_state(cmd->cmd.scan->end_state);
|
ft2232_end_state(cmd->cmd.scan->end_state);
|
||||||
ft2232_large_scan(cmd->cmd.scan, type, buffer, scan_size);
|
ft2232_large_scan(cmd->cmd.scan, type, buffer, scan_size);
|
||||||
require_send = 0;
|
require_send = 0;
|
||||||
|
|
@ -1479,7 +1479,7 @@ int ft2232_execute_queue()
|
||||||
}
|
}
|
||||||
ft2232_expect_read += ft2232_predict_scan_in(scan_size, type);
|
ft2232_expect_read += ft2232_predict_scan_in(scan_size, type);
|
||||||
/* LOG_DEBUG("new read size: %i", ft2232_expect_read); */
|
/* LOG_DEBUG("new read size: %i", ft2232_expect_read); */
|
||||||
if (cmd->cmd.scan->end_state != -1)
|
if (cmd->cmd.scan->end_state != TAP_INVALID)
|
||||||
ft2232_end_state(cmd->cmd.scan->end_state);
|
ft2232_end_state(cmd->cmd.scan->end_state);
|
||||||
ft2232_add_scan(cmd->cmd.scan->ir_scan, type, buffer, scan_size);
|
ft2232_add_scan(cmd->cmd.scan->ir_scan, type, buffer, scan_size);
|
||||||
require_send = 1;
|
require_send = 1;
|
||||||
|
|
|
||||||
|
|
@ -369,7 +369,7 @@ int gw16012_execute_queue(void)
|
||||||
#ifdef _DEBUG_JTAG_IO_
|
#ifdef _DEBUG_JTAG_IO_
|
||||||
LOG_DEBUG("end_state: %i", cmd->cmd.end_state->end_state);
|
LOG_DEBUG("end_state: %i", cmd->cmd.end_state->end_state);
|
||||||
#endif
|
#endif
|
||||||
if (cmd->cmd.end_state->end_state != -1)
|
if (cmd->cmd.end_state->end_state != TAP_INVALID)
|
||||||
gw16012_end_state(cmd->cmd.end_state->end_state);
|
gw16012_end_state(cmd->cmd.end_state->end_state);
|
||||||
break;
|
break;
|
||||||
case JTAG_RESET:
|
case JTAG_RESET:
|
||||||
|
|
@ -386,7 +386,7 @@ int gw16012_execute_queue(void)
|
||||||
#ifdef _DEBUG_JTAG_IO_
|
#ifdef _DEBUG_JTAG_IO_
|
||||||
LOG_DEBUG("runtest %i cycles, end in %i", cmd->cmd.runtest->num_cycles, cmd->cmd.runtest->end_state);
|
LOG_DEBUG("runtest %i cycles, end in %i", cmd->cmd.runtest->num_cycles, cmd->cmd.runtest->end_state);
|
||||||
#endif
|
#endif
|
||||||
if (cmd->cmd.runtest->end_state != -1)
|
if (cmd->cmd.runtest->end_state != TAP_INVALID)
|
||||||
gw16012_end_state(cmd->cmd.runtest->end_state);
|
gw16012_end_state(cmd->cmd.runtest->end_state);
|
||||||
gw16012_runtest(cmd->cmd.runtest->num_cycles);
|
gw16012_runtest(cmd->cmd.runtest->num_cycles);
|
||||||
break;
|
break;
|
||||||
|
|
@ -394,7 +394,7 @@ int gw16012_execute_queue(void)
|
||||||
#ifdef _DEBUG_JTAG_IO_
|
#ifdef _DEBUG_JTAG_IO_
|
||||||
LOG_DEBUG("statemove end in %i", cmd->cmd.statemove->end_state);
|
LOG_DEBUG("statemove end in %i", cmd->cmd.statemove->end_state);
|
||||||
#endif
|
#endif
|
||||||
if (cmd->cmd.statemove->end_state != -1)
|
if (cmd->cmd.statemove->end_state != TAP_INVALID)
|
||||||
gw16012_end_state(cmd->cmd.statemove->end_state);
|
gw16012_end_state(cmd->cmd.statemove->end_state);
|
||||||
gw16012_state_move();
|
gw16012_state_move();
|
||||||
break;
|
break;
|
||||||
|
|
@ -405,7 +405,7 @@ int gw16012_execute_queue(void)
|
||||||
gw16012_path_move(cmd->cmd.pathmove);
|
gw16012_path_move(cmd->cmd.pathmove);
|
||||||
break;
|
break;
|
||||||
case JTAG_SCAN:
|
case JTAG_SCAN:
|
||||||
if (cmd->cmd.scan->end_state != -1)
|
if (cmd->cmd.scan->end_state != TAP_INVALID)
|
||||||
gw16012_end_state(cmd->cmd.scan->end_state);
|
gw16012_end_state(cmd->cmd.scan->end_state);
|
||||||
scan_size = jtag_build_buffer(cmd->cmd.scan, &buffer);
|
scan_size = jtag_build_buffer(cmd->cmd.scan, &buffer);
|
||||||
type = jtag_scan_type(cmd->cmd.scan);
|
type = jtag_scan_type(cmd->cmd.scan);
|
||||||
|
|
|
||||||
|
|
@ -154,7 +154,7 @@ int jlink_execute_queue(void)
|
||||||
case JTAG_END_STATE:
|
case JTAG_END_STATE:
|
||||||
DEBUG_JTAG_IO("end_state: %i", cmd->cmd.end_state->end_state);
|
DEBUG_JTAG_IO("end_state: %i", cmd->cmd.end_state->end_state);
|
||||||
|
|
||||||
if (cmd->cmd.end_state->end_state != -1)
|
if (cmd->cmd.end_state->end_state != TAP_INVALID)
|
||||||
{
|
{
|
||||||
jlink_end_state(cmd->cmd.end_state->end_state);
|
jlink_end_state(cmd->cmd.end_state->end_state);
|
||||||
}
|
}
|
||||||
|
|
@ -164,7 +164,7 @@ int jlink_execute_queue(void)
|
||||||
DEBUG_JTAG_IO( "runtest %i cycles, end in %i", cmd->cmd.runtest->num_cycles, \
|
DEBUG_JTAG_IO( "runtest %i cycles, end in %i", cmd->cmd.runtest->num_cycles, \
|
||||||
cmd->cmd.runtest->end_state);
|
cmd->cmd.runtest->end_state);
|
||||||
|
|
||||||
if (cmd->cmd.runtest->end_state != -1)
|
if (cmd->cmd.runtest->end_state != TAP_INVALID)
|
||||||
{
|
{
|
||||||
jlink_end_state(cmd->cmd.runtest->end_state);
|
jlink_end_state(cmd->cmd.runtest->end_state);
|
||||||
}
|
}
|
||||||
|
|
@ -174,7 +174,7 @@ int jlink_execute_queue(void)
|
||||||
case JTAG_STATEMOVE:
|
case JTAG_STATEMOVE:
|
||||||
DEBUG_JTAG_IO("statemove end in %i", cmd->cmd.statemove->end_state);
|
DEBUG_JTAG_IO("statemove end in %i", cmd->cmd.statemove->end_state);
|
||||||
|
|
||||||
if (cmd->cmd.statemove->end_state != -1)
|
if (cmd->cmd.statemove->end_state != TAP_INVALID)
|
||||||
{
|
{
|
||||||
jlink_end_state(cmd->cmd.statemove->end_state);
|
jlink_end_state(cmd->cmd.statemove->end_state);
|
||||||
}
|
}
|
||||||
|
|
@ -192,7 +192,7 @@ int jlink_execute_queue(void)
|
||||||
case JTAG_SCAN:
|
case JTAG_SCAN:
|
||||||
DEBUG_JTAG_IO("scan end in %i", cmd->cmd.scan->end_state);
|
DEBUG_JTAG_IO("scan end in %i", cmd->cmd.scan->end_state);
|
||||||
|
|
||||||
if (cmd->cmd.scan->end_state != -1)
|
if (cmd->cmd.scan->end_state != TAP_INVALID)
|
||||||
{
|
{
|
||||||
jlink_end_state(cmd->cmd.scan->end_state);
|
jlink_end_state(cmd->cmd.scan->end_state);
|
||||||
}
|
}
|
||||||
|
|
@ -525,7 +525,7 @@ int jlink_get_version_info(void)
|
||||||
if (result == len)
|
if (result == len)
|
||||||
{
|
{
|
||||||
usb_in_buffer[result] = 0;
|
usb_in_buffer[result] = 0;
|
||||||
LOG_INFO(usb_in_buffer);
|
LOG_INFO((char *)usb_in_buffer);
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
@ -858,8 +858,8 @@ int jlink_usb_write(jlink_jtag_t *jlink_jtag, int out_length)
|
||||||
return -1;
|
return -1;
|
||||||
}
|
}
|
||||||
|
|
||||||
result = usb_bulk_write(jlink_jtag->usb_handle, JLINK_WRITE_ENDPOINT, \
|
result = usb_bulk_write(jlink_jtag->usb_handle, JLINK_WRITE_ENDPOINT,
|
||||||
usb_out_buffer, out_length, JLINK_USB_TIMEOUT);
|
(char *)usb_out_buffer, out_length, JLINK_USB_TIMEOUT);
|
||||||
|
|
||||||
DEBUG_JTAG_IO("jlink_usb_write, out_length = %d, result = %d", out_length, result);
|
DEBUG_JTAG_IO("jlink_usb_write, out_length = %d, result = %d", out_length, result);
|
||||||
|
|
||||||
|
|
@ -872,8 +872,8 @@ int jlink_usb_write(jlink_jtag_t *jlink_jtag, int out_length)
|
||||||
/* Read data from USB into in_buffer. */
|
/* Read data from USB into in_buffer. */
|
||||||
int jlink_usb_read(jlink_jtag_t *jlink_jtag)
|
int jlink_usb_read(jlink_jtag_t *jlink_jtag)
|
||||||
{
|
{
|
||||||
int result = usb_bulk_read(jlink_jtag->usb_handle, JLINK_READ_ENDPOINT, \
|
int result = usb_bulk_read(jlink_jtag->usb_handle, JLINK_READ_ENDPOINT,
|
||||||
usb_in_buffer, JLINK_IN_BUFFER_SIZE, JLINK_USB_TIMEOUT);
|
(char *)usb_in_buffer, JLINK_IN_BUFFER_SIZE, JLINK_USB_TIMEOUT);
|
||||||
|
|
||||||
DEBUG_JTAG_IO("jlink_usb_read, result = %d", result);
|
DEBUG_JTAG_IO("jlink_usb_read, result = %d", result);
|
||||||
|
|
||||||
|
|
@ -886,8 +886,9 @@ int jlink_usb_read(jlink_jtag_t *jlink_jtag)
|
||||||
/* Read the result from the previous EMU cmd into result_buffer. */
|
/* Read the result from the previous EMU cmd into result_buffer. */
|
||||||
int jlink_usb_read_emu_result(jlink_jtag_t *jlink_jtag)
|
int jlink_usb_read_emu_result(jlink_jtag_t *jlink_jtag)
|
||||||
{
|
{
|
||||||
int result = usb_bulk_read(jlink_jtag->usb_handle, JLINK_READ_ENDPOINT, \
|
int result = usb_bulk_read(jlink_jtag->usb_handle, JLINK_READ_ENDPOINT,
|
||||||
usb_emu_result_buffer, JLINK_EMU_RESULT_BUFFER_SIZE, JLINK_USB_TIMEOUT);
|
(char *)usb_emu_result_buffer, JLINK_EMU_RESULT_BUFFER_SIZE,
|
||||||
|
JLINK_USB_TIMEOUT);
|
||||||
|
|
||||||
DEBUG_JTAG_IO("jlink_usb_read_result, result = %d", result);
|
DEBUG_JTAG_IO("jlink_usb_read_result, result = %d", result);
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -510,7 +510,7 @@ static void jtag_prelude(tap_state_t state)
|
||||||
{
|
{
|
||||||
jtag_prelude1();
|
jtag_prelude1();
|
||||||
|
|
||||||
if (state != -1)
|
if (state != TAP_INVALID)
|
||||||
jtag_add_end_state(state);
|
jtag_add_end_state(state);
|
||||||
|
|
||||||
cmd_queue_cur_state = cmd_queue_end_state;
|
cmd_queue_cur_state = cmd_queue_end_state;
|
||||||
|
|
@ -2717,7 +2717,7 @@ int handle_runtest_command(struct command_context_s *cmd_ctx, char *cmd, char **
|
||||||
return ERROR_COMMAND_SYNTAX_ERROR;
|
return ERROR_COMMAND_SYNTAX_ERROR;
|
||||||
}
|
}
|
||||||
|
|
||||||
jtag_add_runtest(strtol(args[0], NULL, 0), -1);
|
jtag_add_runtest(strtol(args[0], NULL, 0), TAP_INVALID);
|
||||||
jtag_execute_queue();
|
jtag_execute_queue();
|
||||||
|
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
|
|
@ -2740,7 +2740,7 @@ int handle_irscan_command(struct command_context_s *cmd_ctx, char *cmd, char **a
|
||||||
/* "statename" */
|
/* "statename" */
|
||||||
/* at the end of the arguments. */
|
/* at the end of the arguments. */
|
||||||
/* assume none. */
|
/* assume none. */
|
||||||
endstate = -1;
|
endstate = TAP_INVALID;
|
||||||
if( argc >= 4 ){
|
if( argc >= 4 ){
|
||||||
/* have at least one pair of numbers. */
|
/* have at least one pair of numbers. */
|
||||||
/* is last pair the magic text? */
|
/* is last pair the magic text? */
|
||||||
|
|
@ -2748,13 +2748,13 @@ int handle_irscan_command(struct command_context_s *cmd_ctx, char *cmd, char **a
|
||||||
const char *cpA;
|
const char *cpA;
|
||||||
const char *cpS;
|
const char *cpS;
|
||||||
cpA = args[ argc-1 ];
|
cpA = args[ argc-1 ];
|
||||||
for( endstate = 0 ; endstate < 16 ; endstate++ ){
|
for( endstate = 0 ; endstate < TAP_NUM_STATES ; endstate++ ){
|
||||||
cpS = tap_state_name( endstate );
|
cpS = tap_state_name( endstate );
|
||||||
if( 0 == strcmp( cpA, cpS ) ){
|
if( 0 == strcmp( cpA, cpS ) ){
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
if( endstate >= 16 ){
|
if( endstate >= TAP_NUM_STATES ){
|
||||||
return ERROR_COMMAND_SYNTAX_ERROR;
|
return ERROR_COMMAND_SYNTAX_ERROR;
|
||||||
} else {
|
} else {
|
||||||
/* found - remove the last 2 args */
|
/* found - remove the last 2 args */
|
||||||
|
|
@ -2784,11 +2784,11 @@ int handle_irscan_command(struct command_context_s *cmd_ctx, char *cmd, char **a
|
||||||
fields[i].in_handler_priv = NULL;
|
fields[i].in_handler_priv = NULL;
|
||||||
}
|
}
|
||||||
|
|
||||||
jtag_add_ir_scan(argc / 2, fields, -1);
|
jtag_add_ir_scan(argc / 2, fields, TAP_INVALID);
|
||||||
/* did we have an endstate? */
|
/* did we have an endstate? */
|
||||||
if( endstate >= 0 ){
|
if (endstate != TAP_INVALID)
|
||||||
jtag_add_end_state(endstate);
|
jtag_add_end_state(endstate);
|
||||||
}
|
|
||||||
jtag_execute_queue();
|
jtag_execute_queue();
|
||||||
|
|
||||||
for (i = 0; i < argc / 2; i++)
|
for (i = 0; i < argc / 2; i++)
|
||||||
|
|
@ -2825,7 +2825,7 @@ int Jim_Command_drscan(Jim_Interp *interp, int argc, Jim_Obj *const *args)
|
||||||
}
|
}
|
||||||
|
|
||||||
/* assume no endstate */
|
/* assume no endstate */
|
||||||
endstate = -1;
|
endstate = TAP_INVALID;
|
||||||
/* validate arguments as numbers */
|
/* validate arguments as numbers */
|
||||||
e = JIM_OK;
|
e = JIM_OK;
|
||||||
for (i = 2; i < argc; i+=2)
|
for (i = 2; i < argc; i+=2)
|
||||||
|
|
@ -2901,11 +2901,11 @@ int Jim_Command_drscan(Jim_Interp *interp, int argc, Jim_Obj *const *args)
|
||||||
fields[field_count++].in_handler_priv = NULL;
|
fields[field_count++].in_handler_priv = NULL;
|
||||||
}
|
}
|
||||||
|
|
||||||
jtag_add_dr_scan(num_fields, fields, -1);
|
jtag_add_dr_scan(num_fields, fields, TAP_INVALID);
|
||||||
/* did we get an end state? */
|
/* did we get an end state? */
|
||||||
if( endstate >= 0 ){
|
if (endstate != TAP_INVALID)
|
||||||
jtag_add_end_state( (tap_state_t)endstate );
|
jtag_add_end_state(endstate);
|
||||||
}
|
|
||||||
retval = jtag_execute_queue();
|
retval = jtag_execute_queue();
|
||||||
if (retval != ERROR_OK)
|
if (retval != ERROR_OK)
|
||||||
{
|
{
|
||||||
|
|
@ -3089,7 +3089,7 @@ int tap_get_tms_path( tap_state_t from, tap_state_t to )
|
||||||
*
|
*
|
||||||
* DRSHIFT->DRSHIFT and IRSHIFT->IRSHIFT have to be caught in interface specific code
|
* DRSHIFT->DRSHIFT and IRSHIFT->IRSHIFT have to be caught in interface specific code
|
||||||
*/
|
*/
|
||||||
const static u8 tms_seqs[6][6] =
|
static const u8 tms_seqs[6][6] =
|
||||||
{
|
{
|
||||||
/* value clocked to TMS to move from one of six stable states to another */
|
/* value clocked to TMS to move from one of six stable states to another */
|
||||||
|
|
||||||
|
|
@ -3273,14 +3273,14 @@ int tap_state_by_name( const char *name )
|
||||||
{
|
{
|
||||||
int x;
|
int x;
|
||||||
|
|
||||||
for( x = 0 ; x < 16 ; x++ ){
|
for( x = 0 ; x < TAP_NUM_STATES ; x++ ){
|
||||||
/* be nice to the human */
|
/* be nice to the human */
|
||||||
if( 0 == strcasecmp( name, tap_state_name(x) ) ){
|
if( 0 == strcasecmp( name, tap_state_name(x) ) ){
|
||||||
return x;
|
return x;
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
/* not found */
|
/* not found */
|
||||||
return -1;
|
return TAP_INVALID;
|
||||||
}
|
}
|
||||||
|
|
||||||
/*-----</Cable Helper API>--------------------------------------*/
|
/*-----</Cable Helper API>--------------------------------------*/
|
||||||
|
|
|
||||||
|
|
@ -46,7 +46,9 @@ enum tap_state {
|
||||||
TAP_DRSELECT = 1, TAP_DRCAPTURE = 2, TAP_DRSHIFT = 3, TAP_DREXIT1 = 4,
|
TAP_DRSELECT = 1, TAP_DRCAPTURE = 2, TAP_DRSHIFT = 3, TAP_DREXIT1 = 4,
|
||||||
TAP_DRPAUSE = 5, TAP_DREXIT2 = 6, TAP_DRUPDATE = 7,
|
TAP_DRPAUSE = 5, TAP_DREXIT2 = 6, TAP_DRUPDATE = 7,
|
||||||
TAP_IRSELECT = 9, TAP_IRCAPTURE = 10, TAP_IRSHIFT = 11, TAP_IREXIT1 = 12,
|
TAP_IRSELECT = 9, TAP_IRCAPTURE = 10, TAP_IRSHIFT = 11, TAP_IREXIT1 = 12,
|
||||||
TAP_IRPAUSE = 13, TAP_IREXIT2 = 14, TAP_IRUPDATE = 15
|
TAP_IRPAUSE = 13, TAP_IREXIT2 = 14, TAP_IRUPDATE = 15,
|
||||||
|
|
||||||
|
TAP_NUM_STATES = 16, TAP_INVALID = -1,
|
||||||
};
|
};
|
||||||
|
|
||||||
typedef enum tap_state tap_state_t;
|
typedef enum tap_state tap_state_t;
|
||||||
|
|
@ -643,7 +645,7 @@ void jtag_tap_handle_event(jtag_tap_t* tap, enum jtag_tap_event e);
|
||||||
|
|
||||||
/* jtag_add_dr_out() is a faster version of jtag_add_dr_scan()
|
/* jtag_add_dr_out() is a faster version of jtag_add_dr_scan()
|
||||||
*
|
*
|
||||||
* Current or end_state can not be TAP_RESET. end_state can be -1
|
* Current or end_state can not be TAP_RESET. end_state can be TAP_INVALID
|
||||||
*
|
*
|
||||||
* num_bits[i] is the number of bits to clock out from value[i] LSB first.
|
* num_bits[i] is the number of bits to clock out from value[i] LSB first.
|
||||||
*
|
*
|
||||||
|
|
@ -666,7 +668,7 @@ extern void interface_jtag_add_dr_out(jtag_tap_t* tap, int num_fields, const int
|
||||||
static __inline__ void jtag_add_dr_out(jtag_tap_t* tap, int num_fields, const int* num_bits, const u32* value,
|
static __inline__ void jtag_add_dr_out(jtag_tap_t* tap, int num_fields, const int* num_bits, const u32* value,
|
||||||
tap_state_t end_state)
|
tap_state_t end_state)
|
||||||
{
|
{
|
||||||
if (end_state != -1)
|
if (end_state != TAP_INVALID)
|
||||||
cmd_queue_end_state = end_state;
|
cmd_queue_end_state = end_state;
|
||||||
cmd_queue_cur_state = cmd_queue_end_state;
|
cmd_queue_cur_state = cmd_queue_end_state;
|
||||||
interface_jtag_add_dr_out(tap, num_fields, num_bits, value, cmd_queue_end_state);
|
interface_jtag_add_dr_out(tap, num_fields, num_bits, value, cmd_queue_end_state);
|
||||||
|
|
|
||||||
|
|
@ -142,7 +142,7 @@ int usbprog_execute_queue(void)
|
||||||
#ifdef _DEBUG_JTAG_IO_
|
#ifdef _DEBUG_JTAG_IO_
|
||||||
LOG_DEBUG("end_state: %i", cmd->cmd.end_state->end_state);
|
LOG_DEBUG("end_state: %i", cmd->cmd.end_state->end_state);
|
||||||
#endif
|
#endif
|
||||||
if (cmd->cmd.end_state->end_state != -1)
|
if (cmd->cmd.end_state->end_state != TAP_INVALID)
|
||||||
usbprog_end_state(cmd->cmd.end_state->end_state);
|
usbprog_end_state(cmd->cmd.end_state->end_state);
|
||||||
break;
|
break;
|
||||||
case JTAG_RESET:
|
case JTAG_RESET:
|
||||||
|
|
@ -159,7 +159,7 @@ int usbprog_execute_queue(void)
|
||||||
#ifdef _DEBUG_JTAG_IO_
|
#ifdef _DEBUG_JTAG_IO_
|
||||||
LOG_DEBUG("runtest %i cycles, end in %i", cmd->cmd.runtest->num_cycles, cmd->cmd.runtest->end_state);
|
LOG_DEBUG("runtest %i cycles, end in %i", cmd->cmd.runtest->num_cycles, cmd->cmd.runtest->end_state);
|
||||||
#endif
|
#endif
|
||||||
if (cmd->cmd.runtest->end_state != -1)
|
if (cmd->cmd.runtest->end_state != TAP_INVALID)
|
||||||
usbprog_end_state(cmd->cmd.runtest->end_state);
|
usbprog_end_state(cmd->cmd.runtest->end_state);
|
||||||
usbprog_runtest(cmd->cmd.runtest->num_cycles);
|
usbprog_runtest(cmd->cmd.runtest->num_cycles);
|
||||||
break;
|
break;
|
||||||
|
|
@ -167,7 +167,7 @@ int usbprog_execute_queue(void)
|
||||||
#ifdef _DEBUG_JTAG_IO_
|
#ifdef _DEBUG_JTAG_IO_
|
||||||
LOG_DEBUG("statemove end in %i", cmd->cmd.statemove->end_state);
|
LOG_DEBUG("statemove end in %i", cmd->cmd.statemove->end_state);
|
||||||
#endif
|
#endif
|
||||||
if (cmd->cmd.statemove->end_state != -1)
|
if (cmd->cmd.statemove->end_state != TAP_INVALID)
|
||||||
usbprog_end_state(cmd->cmd.statemove->end_state);
|
usbprog_end_state(cmd->cmd.statemove->end_state);
|
||||||
usbprog_state_move();
|
usbprog_state_move();
|
||||||
break;
|
break;
|
||||||
|
|
@ -182,7 +182,7 @@ int usbprog_execute_queue(void)
|
||||||
#ifdef _DEBUG_JTAG_IO_
|
#ifdef _DEBUG_JTAG_IO_
|
||||||
LOG_DEBUG("scan end in %i", cmd->cmd.scan->end_state);
|
LOG_DEBUG("scan end in %i", cmd->cmd.scan->end_state);
|
||||||
#endif
|
#endif
|
||||||
if (cmd->cmd.scan->end_state != -1)
|
if (cmd->cmd.scan->end_state != TAP_INVALID)
|
||||||
usbprog_end_state(cmd->cmd.scan->end_state);
|
usbprog_end_state(cmd->cmd.scan->end_state);
|
||||||
scan_size = jtag_build_buffer(cmd->cmd.scan, &buffer);
|
scan_size = jtag_build_buffer(cmd->cmd.scan, &buffer);
|
||||||
type = jtag_scan_type(cmd->cmd.scan);
|
type = jtag_scan_type(cmd->cmd.scan);
|
||||||
|
|
|
||||||
|
|
@ -269,7 +269,7 @@ int vsllink_execute_queue(void)
|
||||||
case JTAG_END_STATE:
|
case JTAG_END_STATE:
|
||||||
DEBUG_JTAG_IO("end_state: %s", tap_state_name(cmd->cmd.end_state->end_state));
|
DEBUG_JTAG_IO("end_state: %s", tap_state_name(cmd->cmd.end_state->end_state));
|
||||||
|
|
||||||
if (cmd->cmd.end_state->end_state != -1)
|
if (cmd->cmd.end_state->end_state != TAP_INVALID)
|
||||||
{
|
{
|
||||||
vsllink_end_state(cmd->cmd.end_state->end_state);
|
vsllink_end_state(cmd->cmd.end_state->end_state);
|
||||||
}
|
}
|
||||||
|
|
@ -279,7 +279,7 @@ int vsllink_execute_queue(void)
|
||||||
DEBUG_JTAG_IO( "runtest %i cycles, end in %s", cmd->cmd.runtest->num_cycles, \
|
DEBUG_JTAG_IO( "runtest %i cycles, end in %s", cmd->cmd.runtest->num_cycles, \
|
||||||
tap_state_name(cmd->cmd.runtest->end_state));
|
tap_state_name(cmd->cmd.runtest->end_state));
|
||||||
|
|
||||||
if (cmd->cmd.runtest->end_state != -1)
|
if (cmd->cmd.runtest->end_state != TAP_INVALID)
|
||||||
{
|
{
|
||||||
vsllink_end_state(cmd->cmd.runtest->end_state);
|
vsllink_end_state(cmd->cmd.runtest->end_state);
|
||||||
}
|
}
|
||||||
|
|
@ -289,7 +289,7 @@ int vsllink_execute_queue(void)
|
||||||
case JTAG_STATEMOVE:
|
case JTAG_STATEMOVE:
|
||||||
DEBUG_JTAG_IO("statemove end in %s", tap_state_name(cmd->cmd.statemove->end_state));
|
DEBUG_JTAG_IO("statemove end in %s", tap_state_name(cmd->cmd.statemove->end_state));
|
||||||
|
|
||||||
if (cmd->cmd.statemove->end_state != -1)
|
if (cmd->cmd.statemove->end_state != TAP_INVALID)
|
||||||
{
|
{
|
||||||
vsllink_end_state(cmd->cmd.statemove->end_state);
|
vsllink_end_state(cmd->cmd.statemove->end_state);
|
||||||
}
|
}
|
||||||
|
|
@ -305,7 +305,7 @@ int vsllink_execute_queue(void)
|
||||||
break;
|
break;
|
||||||
|
|
||||||
case JTAG_SCAN:
|
case JTAG_SCAN:
|
||||||
if (cmd->cmd.scan->end_state != -1)
|
if (cmd->cmd.scan->end_state != TAP_INVALID)
|
||||||
{
|
{
|
||||||
vsllink_end_state(cmd->cmd.scan->end_state);
|
vsllink_end_state(cmd->cmd.scan->end_state);
|
||||||
}
|
}
|
||||||
|
|
|
||||||
|
|
@ -383,9 +383,9 @@ static void arm11_on_enter_debug_state(arm11_common_t * arm11)
|
||||||
|
|
||||||
if (R(DSCR) & ARM11_DSCR_WDTR_FULL)
|
if (R(DSCR) & ARM11_DSCR_WDTR_FULL)
|
||||||
{
|
{
|
||||||
arm11_add_debug_SCAN_N(arm11, 0x05, -1);
|
arm11_add_debug_SCAN_N(arm11, 0x05, TAP_INVALID);
|
||||||
|
|
||||||
arm11_add_IR(arm11, ARM11_INTEST, -1);
|
arm11_add_IR(arm11, ARM11_INTEST, TAP_INVALID);
|
||||||
|
|
||||||
scan_field_t chain5_fields[3];
|
scan_field_t chain5_fields[3];
|
||||||
|
|
||||||
|
|
@ -614,9 +614,9 @@ void arm11_leave_debug_state(arm11_common_t * arm11)
|
||||||
|
|
||||||
if (R(DSCR) & ARM11_DSCR_RDTR_FULL || arm11->reg_list[ARM11_RC_RDTR].dirty)
|
if (R(DSCR) & ARM11_DSCR_RDTR_FULL || arm11->reg_list[ARM11_RC_RDTR].dirty)
|
||||||
{
|
{
|
||||||
arm11_add_debug_SCAN_N(arm11, 0x05, -1);
|
arm11_add_debug_SCAN_N(arm11, 0x05, TAP_INVALID);
|
||||||
|
|
||||||
arm11_add_IR(arm11, ARM11_EXTEST, -1);
|
arm11_add_IR(arm11, ARM11_EXTEST, TAP_INVALID);
|
||||||
|
|
||||||
scan_field_t chain5_fields[3];
|
scan_field_t chain5_fields[3];
|
||||||
|
|
||||||
|
|
@ -1565,7 +1565,7 @@ int arm11_examine(struct target_s *target)
|
||||||
|
|
||||||
/* check IDCODE */
|
/* check IDCODE */
|
||||||
|
|
||||||
arm11_add_IR(arm11, ARM11_IDCODE, -1);
|
arm11_add_IR(arm11, ARM11_IDCODE, TAP_INVALID);
|
||||||
|
|
||||||
scan_field_t idcode_field;
|
scan_field_t idcode_field;
|
||||||
|
|
||||||
|
|
@ -1575,9 +1575,9 @@ int arm11_examine(struct target_s *target)
|
||||||
|
|
||||||
/* check DIDR */
|
/* check DIDR */
|
||||||
|
|
||||||
arm11_add_debug_SCAN_N(arm11, 0x00, -1);
|
arm11_add_debug_SCAN_N(arm11, 0x00, TAP_INVALID);
|
||||||
|
|
||||||
arm11_add_IR(arm11, ARM11_INTEST, -1);
|
arm11_add_IR(arm11, ARM11_INTEST, TAP_INVALID);
|
||||||
|
|
||||||
scan_field_t chain0_fields[2];
|
scan_field_t chain0_fields[2];
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -95,7 +95,7 @@ void arm11_setup_field(arm11_common_t * arm11, int num_bits, void * out_data, vo
|
||||||
*
|
*
|
||||||
* \param arm11 Target state variable.
|
* \param arm11 Target state variable.
|
||||||
* \param instr An ARM11 DBGTAP instruction. Use enum #arm11_instructions.
|
* \param instr An ARM11 DBGTAP instruction. Use enum #arm11_instructions.
|
||||||
* \param state Pass the final TAP state or -1 for the default value (Pause-IR).
|
* \param state Pass the final TAP state or TAP_INVALID for the default value (Pause-IR).
|
||||||
*
|
*
|
||||||
* \remarks This adds to the JTAG command queue but does \em not execute it.
|
* \remarks This adds to the JTAG command queue but does \em not execute it.
|
||||||
*/
|
*/
|
||||||
|
|
@ -120,7 +120,7 @@ void arm11_add_IR(arm11_common_t * arm11, u8 instr, tap_state_t state)
|
||||||
|
|
||||||
arm11_setup_field(arm11, 5, &instr, NULL, &field);
|
arm11_setup_field(arm11, 5, &instr, NULL, &field);
|
||||||
|
|
||||||
arm11_add_ir_scan_vc(1, &field, state == -1 ? TAP_IRPAUSE : state);
|
arm11_add_ir_scan_vc(1, &field, state == TAP_INVALID ? TAP_IRPAUSE : state);
|
||||||
}
|
}
|
||||||
|
|
||||||
/** Verify shifted out data from Scan Chain Register (SCREG)
|
/** Verify shifted out data from Scan Chain Register (SCREG)
|
||||||
|
|
@ -152,7 +152,7 @@ static int arm11_in_handler_SCAN_N(u8 *in_value, void *priv, struct scan_field_s
|
||||||
*
|
*
|
||||||
* \param arm11 Target state variable.
|
* \param arm11 Target state variable.
|
||||||
* \param chain Scan chain that will be selected.
|
* \param chain Scan chain that will be selected.
|
||||||
* \param state Pass the final TAP state or -1 for the default
|
* \param state Pass the final TAP state or TAP_INVALID for the default
|
||||||
* value (Pause-DR).
|
* value (Pause-DR).
|
||||||
*
|
*
|
||||||
* The chain takes effect when Update-DR is passed (usually when subsequently
|
* The chain takes effect when Update-DR is passed (usually when subsequently
|
||||||
|
|
@ -171,7 +171,7 @@ void arm11_add_debug_SCAN_N(arm11_common_t * arm11, u8 chain, tap_state_t state)
|
||||||
{
|
{
|
||||||
JTAG_DEBUG("SCREG <= 0x%02x", chain);
|
JTAG_DEBUG("SCREG <= 0x%02x", chain);
|
||||||
|
|
||||||
arm11_add_IR(arm11, ARM11_SCAN_N, -1);
|
arm11_add_IR(arm11, ARM11_SCAN_N, TAP_INVALID);
|
||||||
|
|
||||||
scan_field_t field;
|
scan_field_t field;
|
||||||
|
|
||||||
|
|
@ -179,7 +179,7 @@ void arm11_add_debug_SCAN_N(arm11_common_t * arm11, u8 chain, tap_state_t state)
|
||||||
|
|
||||||
field.in_handler = arm11_in_handler_SCAN_N;
|
field.in_handler = arm11_in_handler_SCAN_N;
|
||||||
|
|
||||||
arm11_add_dr_scan_vc(1, &field, state == -1 ? TAP_DRPAUSE : state);
|
arm11_add_dr_scan_vc(1, &field, state == TAP_INVALID ? TAP_DRPAUSE : state);
|
||||||
}
|
}
|
||||||
|
|
||||||
/** Write an instruction into the ITR register
|
/** Write an instruction into the ITR register
|
||||||
|
|
@ -188,7 +188,7 @@ void arm11_add_debug_SCAN_N(arm11_common_t * arm11, u8 chain, tap_state_t state)
|
||||||
* \param inst An ARM11 processor instruction/opcode.
|
* \param inst An ARM11 processor instruction/opcode.
|
||||||
* \param flag Optional parameter to retrieve the InstCompl flag
|
* \param flag Optional parameter to retrieve the InstCompl flag
|
||||||
* (this will be written when the JTAG chain is executed).
|
* (this will be written when the JTAG chain is executed).
|
||||||
* \param state Pass the final TAP state or -1 for the default
|
* \param state Pass the final TAP state or TAP_INVALID for the default
|
||||||
* value (Run-Test/Idle).
|
* value (Run-Test/Idle).
|
||||||
*
|
*
|
||||||
* \remarks By default this ends with Run-Test/Idle state
|
* \remarks By default this ends with Run-Test/Idle state
|
||||||
|
|
@ -208,7 +208,7 @@ void arm11_add_debug_INST(arm11_common_t * arm11, u32 inst, u8 * flag, tap_state
|
||||||
arm11_setup_field(arm11, 32, &inst, NULL, itr + 0);
|
arm11_setup_field(arm11, 32, &inst, NULL, itr + 0);
|
||||||
arm11_setup_field(arm11, 1, NULL, flag, itr + 1);
|
arm11_setup_field(arm11, 1, NULL, flag, itr + 1);
|
||||||
|
|
||||||
arm11_add_dr_scan_vc(asizeof(itr), itr, state == -1 ? TAP_IDLE : state);
|
arm11_add_dr_scan_vc(asizeof(itr), itr, state == TAP_INVALID ? TAP_IDLE : state);
|
||||||
}
|
}
|
||||||
|
|
||||||
/** Read the Debug Status and Control Register (DSCR)
|
/** Read the Debug Status and Control Register (DSCR)
|
||||||
|
|
@ -222,9 +222,9 @@ void arm11_add_debug_INST(arm11_common_t * arm11, u32 inst, u8 * flag, tap_state
|
||||||
*/
|
*/
|
||||||
u32 arm11_read_DSCR(arm11_common_t * arm11)
|
u32 arm11_read_DSCR(arm11_common_t * arm11)
|
||||||
{
|
{
|
||||||
arm11_add_debug_SCAN_N(arm11, 0x01, -1);
|
arm11_add_debug_SCAN_N(arm11, 0x01, TAP_INVALID);
|
||||||
|
|
||||||
arm11_add_IR(arm11, ARM11_INTEST, -1);
|
arm11_add_IR(arm11, ARM11_INTEST, TAP_INVALID);
|
||||||
|
|
||||||
u32 dscr;
|
u32 dscr;
|
||||||
scan_field_t chain1_field;
|
scan_field_t chain1_field;
|
||||||
|
|
@ -254,9 +254,9 @@ u32 arm11_read_DSCR(arm11_common_t * arm11)
|
||||||
*/
|
*/
|
||||||
void arm11_write_DSCR(arm11_common_t * arm11, u32 dscr)
|
void arm11_write_DSCR(arm11_common_t * arm11, u32 dscr)
|
||||||
{
|
{
|
||||||
arm11_add_debug_SCAN_N(arm11, 0x01, -1);
|
arm11_add_debug_SCAN_N(arm11, 0x01, TAP_INVALID);
|
||||||
|
|
||||||
arm11_add_IR(arm11, ARM11_EXTEST, -1);
|
arm11_add_IR(arm11, ARM11_EXTEST, TAP_INVALID);
|
||||||
|
|
||||||
scan_field_t chain1_field;
|
scan_field_t chain1_field;
|
||||||
|
|
||||||
|
|
@ -331,7 +331,7 @@ enum target_debug_reason arm11_get_DSCR_debug_reason(u32 dscr)
|
||||||
*/
|
*/
|
||||||
void arm11_run_instr_data_prepare(arm11_common_t * arm11)
|
void arm11_run_instr_data_prepare(arm11_common_t * arm11)
|
||||||
{
|
{
|
||||||
arm11_add_debug_SCAN_N(arm11, 0x05, -1);
|
arm11_add_debug_SCAN_N(arm11, 0x05, TAP_INVALID);
|
||||||
}
|
}
|
||||||
|
|
||||||
/** Cleanup after ITR/DTR operations
|
/** Cleanup after ITR/DTR operations
|
||||||
|
|
@ -350,7 +350,7 @@ void arm11_run_instr_data_prepare(arm11_common_t * arm11)
|
||||||
*/
|
*/
|
||||||
void arm11_run_instr_data_finish(arm11_common_t * arm11)
|
void arm11_run_instr_data_finish(arm11_common_t * arm11)
|
||||||
{
|
{
|
||||||
arm11_add_debug_SCAN_N(arm11, 0x00, -1);
|
arm11_add_debug_SCAN_N(arm11, 0x00, TAP_INVALID);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
|
|
@ -365,7 +365,7 @@ void arm11_run_instr_data_finish(arm11_common_t * arm11)
|
||||||
*/
|
*/
|
||||||
void arm11_run_instr_no_data(arm11_common_t * arm11, u32 * opcode, size_t count)
|
void arm11_run_instr_no_data(arm11_common_t * arm11, u32 * opcode, size_t count)
|
||||||
{
|
{
|
||||||
arm11_add_IR(arm11, ARM11_ITRSEL, -1);
|
arm11_add_IR(arm11, ARM11_ITRSEL, TAP_INVALID);
|
||||||
|
|
||||||
while (count--)
|
while (count--)
|
||||||
{
|
{
|
||||||
|
|
@ -414,11 +414,11 @@ void arm11_run_instr_no_data1(arm11_common_t * arm11, u32 opcode)
|
||||||
*/
|
*/
|
||||||
void arm11_run_instr_data_to_core(arm11_common_t * arm11, u32 opcode, u32 * data, size_t count)
|
void arm11_run_instr_data_to_core(arm11_common_t * arm11, u32 opcode, u32 * data, size_t count)
|
||||||
{
|
{
|
||||||
arm11_add_IR(arm11, ARM11_ITRSEL, -1);
|
arm11_add_IR(arm11, ARM11_ITRSEL, TAP_INVALID);
|
||||||
|
|
||||||
arm11_add_debug_INST(arm11, opcode, NULL, TAP_DRPAUSE);
|
arm11_add_debug_INST(arm11, opcode, NULL, TAP_DRPAUSE);
|
||||||
|
|
||||||
arm11_add_IR(arm11, ARM11_EXTEST, -1);
|
arm11_add_IR(arm11, ARM11_EXTEST, TAP_INVALID);
|
||||||
|
|
||||||
scan_field_t chain5_fields[3];
|
scan_field_t chain5_fields[3];
|
||||||
|
|
||||||
|
|
@ -446,7 +446,7 @@ void arm11_run_instr_data_to_core(arm11_common_t * arm11, u32 opcode, u32 * data
|
||||||
data++;
|
data++;
|
||||||
}
|
}
|
||||||
|
|
||||||
arm11_add_IR(arm11, ARM11_INTEST, -1);
|
arm11_add_IR(arm11, ARM11_INTEST, TAP_INVALID);
|
||||||
|
|
||||||
do
|
do
|
||||||
{
|
{
|
||||||
|
|
@ -495,11 +495,11 @@ tap_state_t arm11_MOVE_DRPAUSE_IDLE_DRPAUSE_with_delay[] =
|
||||||
*/
|
*/
|
||||||
void arm11_run_instr_data_to_core_noack(arm11_common_t * arm11, u32 opcode, u32 * data, size_t count)
|
void arm11_run_instr_data_to_core_noack(arm11_common_t * arm11, u32 opcode, u32 * data, size_t count)
|
||||||
{
|
{
|
||||||
arm11_add_IR(arm11, ARM11_ITRSEL, -1);
|
arm11_add_IR(arm11, ARM11_ITRSEL, TAP_INVALID);
|
||||||
|
|
||||||
arm11_add_debug_INST(arm11, opcode, NULL, TAP_DRPAUSE);
|
arm11_add_debug_INST(arm11, opcode, NULL, TAP_DRPAUSE);
|
||||||
|
|
||||||
arm11_add_IR(arm11, ARM11_EXTEST, -1);
|
arm11_add_IR(arm11, ARM11_EXTEST, TAP_INVALID);
|
||||||
|
|
||||||
scan_field_t chain5_fields[3];
|
scan_field_t chain5_fields[3];
|
||||||
|
|
||||||
|
|
@ -527,7 +527,7 @@ void arm11_run_instr_data_to_core_noack(arm11_common_t * arm11, u32 opcode, u32
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
arm11_add_IR(arm11, ARM11_INTEST, -1);
|
arm11_add_IR(arm11, ARM11_INTEST, TAP_INVALID);
|
||||||
|
|
||||||
chain5_fields[0].out_value = 0;
|
chain5_fields[0].out_value = 0;
|
||||||
chain5_fields[1].in_value = ReadyPos++;
|
chain5_fields[1].in_value = ReadyPos++;
|
||||||
|
|
@ -584,11 +584,11 @@ void arm11_run_instr_data_to_core1(arm11_common_t * arm11, u32 opcode, u32 data)
|
||||||
*/
|
*/
|
||||||
void arm11_run_instr_data_from_core(arm11_common_t * arm11, u32 opcode, u32 * data, size_t count)
|
void arm11_run_instr_data_from_core(arm11_common_t * arm11, u32 opcode, u32 * data, size_t count)
|
||||||
{
|
{
|
||||||
arm11_add_IR(arm11, ARM11_ITRSEL, -1);
|
arm11_add_IR(arm11, ARM11_ITRSEL, TAP_INVALID);
|
||||||
|
|
||||||
arm11_add_debug_INST(arm11, opcode, NULL, TAP_IDLE);
|
arm11_add_debug_INST(arm11, opcode, NULL, TAP_IDLE);
|
||||||
|
|
||||||
arm11_add_IR(arm11, ARM11_INTEST, -1);
|
arm11_add_IR(arm11, ARM11_INTEST, TAP_INVALID);
|
||||||
|
|
||||||
scan_field_t chain5_fields[3];
|
scan_field_t chain5_fields[3];
|
||||||
|
|
||||||
|
|
@ -666,9 +666,9 @@ void arm11_run_instr_data_to_core_via_r0(arm11_common_t * arm11, u32 opcode, u32
|
||||||
*/
|
*/
|
||||||
void arm11_sc7_run(arm11_common_t * arm11, arm11_sc7_action_t * actions, size_t count)
|
void arm11_sc7_run(arm11_common_t * arm11, arm11_sc7_action_t * actions, size_t count)
|
||||||
{
|
{
|
||||||
arm11_add_debug_SCAN_N(arm11, 0x07, -1);
|
arm11_add_debug_SCAN_N(arm11, 0x07, TAP_INVALID);
|
||||||
|
|
||||||
arm11_add_IR(arm11, ARM11_EXTEST, -1);
|
arm11_add_IR(arm11, ARM11_EXTEST, TAP_INVALID);
|
||||||
|
|
||||||
scan_field_t chain7_fields[3];
|
scan_field_t chain7_fields[3];
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -136,10 +136,10 @@ int arm720t_scan_cp15(target_t *target, u32 out, u32 *in, int instruction, int c
|
||||||
fields[1].in_check_value = NULL;
|
fields[1].in_check_value = NULL;
|
||||||
fields[1].in_check_mask = NULL;
|
fields[1].in_check_mask = NULL;
|
||||||
|
|
||||||
jtag_add_dr_scan(2, fields, -1);
|
jtag_add_dr_scan(2, fields, TAP_INVALID);
|
||||||
|
|
||||||
if (clock)
|
if (clock)
|
||||||
jtag_add_runtest(0, -1);
|
jtag_add_runtest(0, TAP_INVALID);
|
||||||
|
|
||||||
#ifdef _DEBUG_INSTRUCTION_EXECUTION_
|
#ifdef _DEBUG_INSTRUCTION_EXECUTION_
|
||||||
if((retval = jtag_execute_queue()) != ERROR_OK)
|
if((retval = jtag_execute_queue()) != ERROR_OK)
|
||||||
|
|
|
||||||
|
|
@ -169,9 +169,9 @@ static __inline int arm7tdmi_clock_out_inner(arm_jtag_t *jtag_info, u32 out, int
|
||||||
2,
|
2,
|
||||||
arm7tdmi_num_bits,
|
arm7tdmi_num_bits,
|
||||||
values,
|
values,
|
||||||
-1);
|
TAP_INVALID);
|
||||||
|
|
||||||
jtag_add_runtest(0, -1);
|
jtag_add_runtest(0, TAP_INVALID);
|
||||||
|
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
@ -219,9 +219,9 @@ int arm7tdmi_clock_data_in(arm_jtag_t *jtag_info, u32 *in)
|
||||||
fields[1].in_check_value = NULL;
|
fields[1].in_check_value = NULL;
|
||||||
fields[1].in_check_mask = NULL;
|
fields[1].in_check_mask = NULL;
|
||||||
|
|
||||||
jtag_add_dr_scan(2, fields, -1);
|
jtag_add_dr_scan(2, fields, TAP_INVALID);
|
||||||
|
|
||||||
jtag_add_runtest(0, -1);
|
jtag_add_runtest(0, TAP_INVALID);
|
||||||
|
|
||||||
#ifdef _DEBUG_INSTRUCTION_EXECUTION_
|
#ifdef _DEBUG_INSTRUCTION_EXECUTION_
|
||||||
{
|
{
|
||||||
|
|
@ -291,9 +291,9 @@ int arm7tdmi_clock_data_in_endianness(arm_jtag_t *jtag_info, void *in, int size,
|
||||||
fields[1].in_check_value = NULL;
|
fields[1].in_check_value = NULL;
|
||||||
fields[1].in_check_mask = NULL;
|
fields[1].in_check_mask = NULL;
|
||||||
|
|
||||||
jtag_add_dr_scan(2, fields, -1);
|
jtag_add_dr_scan(2, fields, TAP_INVALID);
|
||||||
|
|
||||||
jtag_add_runtest(0, -1);
|
jtag_add_runtest(0, TAP_INVALID);
|
||||||
|
|
||||||
#ifdef _DEBUG_INSTRUCTION_EXECUTION_
|
#ifdef _DEBUG_INSTRUCTION_EXECUTION_
|
||||||
{
|
{
|
||||||
|
|
|
||||||
|
|
@ -150,12 +150,12 @@ int arm920t_read_cp15_physical(target_t *target, int reg_addr, u32 *value)
|
||||||
fields[3].in_handler = NULL;
|
fields[3].in_handler = NULL;
|
||||||
fields[3].in_handler_priv = NULL;
|
fields[3].in_handler_priv = NULL;
|
||||||
|
|
||||||
jtag_add_dr_scan(4, fields, -1);
|
jtag_add_dr_scan(4, fields, TAP_INVALID);
|
||||||
|
|
||||||
fields[1].in_handler_priv = value;
|
fields[1].in_handler_priv = value;
|
||||||
fields[1].in_handler = arm_jtag_buf_to_u32;
|
fields[1].in_handler = arm_jtag_buf_to_u32;
|
||||||
|
|
||||||
jtag_add_dr_scan(4, fields, -1);
|
jtag_add_dr_scan(4, fields, TAP_INVALID);
|
||||||
|
|
||||||
#ifdef _DEBUG_INSTRUCTION_EXECUTION_
|
#ifdef _DEBUG_INSTRUCTION_EXECUTION_
|
||||||
jtag_execute_queue();
|
jtag_execute_queue();
|
||||||
|
|
@ -222,7 +222,7 @@ int arm920t_write_cp15_physical(target_t *target, int reg_addr, u32 value)
|
||||||
fields[3].in_handler = NULL;
|
fields[3].in_handler = NULL;
|
||||||
fields[3].in_handler_priv = NULL;
|
fields[3].in_handler_priv = NULL;
|
||||||
|
|
||||||
jtag_add_dr_scan(4, fields, -1);
|
jtag_add_dr_scan(4, fields, TAP_INVALID);
|
||||||
|
|
||||||
#ifdef _DEBUG_INSTRUCTION_EXECUTION_
|
#ifdef _DEBUG_INSTRUCTION_EXECUTION_
|
||||||
LOG_DEBUG("addr: 0x%x value: %8.8x", reg_addr, value);
|
LOG_DEBUG("addr: 0x%x value: %8.8x", reg_addr, value);
|
||||||
|
|
@ -289,7 +289,7 @@ int arm920t_execute_cp15(target_t *target, u32 cp15_opcode, u32 arm_opcode)
|
||||||
fields[3].in_handler = NULL;
|
fields[3].in_handler = NULL;
|
||||||
fields[3].in_handler_priv = NULL;
|
fields[3].in_handler_priv = NULL;
|
||||||
|
|
||||||
jtag_add_dr_scan(4, fields, -1);
|
jtag_add_dr_scan(4, fields, TAP_INVALID);
|
||||||
|
|
||||||
arm9tdmi_clock_out(jtag_info, arm_opcode, 0, NULL, 0);
|
arm9tdmi_clock_out(jtag_info, arm_opcode, 0, NULL, 0);
|
||||||
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
|
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
|
||||||
|
|
|
||||||
|
|
@ -178,7 +178,7 @@ int arm926ejs_cp15_read(target_t *target, u32 op1, u32 op2, u32 CRn, u32 CRm, u3
|
||||||
fields[3].in_handler = NULL;
|
fields[3].in_handler = NULL;
|
||||||
fields[3].in_handler_priv = NULL;
|
fields[3].in_handler_priv = NULL;
|
||||||
|
|
||||||
jtag_add_dr_scan(4, fields, -1);
|
jtag_add_dr_scan(4, fields, TAP_INVALID);
|
||||||
|
|
||||||
fields[0].in_handler_priv = value;
|
fields[0].in_handler_priv = value;
|
||||||
fields[0].in_handler = arm_jtag_buf_to_u32;
|
fields[0].in_handler = arm_jtag_buf_to_u32;
|
||||||
|
|
@ -189,7 +189,7 @@ int arm926ejs_cp15_read(target_t *target, u32 op1, u32 op2, u32 CRn, u32 CRm, u3
|
||||||
/* rescan with NOP, to wait for the access to complete */
|
/* rescan with NOP, to wait for the access to complete */
|
||||||
access = 0;
|
access = 0;
|
||||||
nr_w_buf = 0;
|
nr_w_buf = 0;
|
||||||
jtag_add_dr_scan(4, fields, -1);
|
jtag_add_dr_scan(4, fields, TAP_INVALID);
|
||||||
if((retval = jtag_execute_queue()) != ERROR_OK)
|
if((retval = jtag_execute_queue()) != ERROR_OK)
|
||||||
{
|
{
|
||||||
return retval;
|
return retval;
|
||||||
|
|
@ -268,14 +268,14 @@ int arm926ejs_cp15_write(target_t *target, u32 op1, u32 op2, u32 CRn, u32 CRm, u
|
||||||
fields[3].in_handler = NULL;
|
fields[3].in_handler = NULL;
|
||||||
fields[3].in_handler_priv = NULL;
|
fields[3].in_handler_priv = NULL;
|
||||||
|
|
||||||
jtag_add_dr_scan(4, fields, -1);
|
jtag_add_dr_scan(4, fields, TAP_INVALID);
|
||||||
/*TODO: add timeout*/
|
/*TODO: add timeout*/
|
||||||
do
|
do
|
||||||
{
|
{
|
||||||
/* rescan with NOP, to wait for the access to complete */
|
/* rescan with NOP, to wait for the access to complete */
|
||||||
access = 0;
|
access = 0;
|
||||||
nr_w_buf = 0;
|
nr_w_buf = 0;
|
||||||
jtag_add_dr_scan(4, fields, -1);
|
jtag_add_dr_scan(4, fields, TAP_INVALID);
|
||||||
if((retval = jtag_execute_queue()) != ERROR_OK)
|
if((retval = jtag_execute_queue()) != ERROR_OK)
|
||||||
{
|
{
|
||||||
return retval;
|
return retval;
|
||||||
|
|
|
||||||
|
|
@ -214,12 +214,12 @@ int arm966e_read_cp15(target_t *target, int reg_addr, u32 *value)
|
||||||
fields[2].in_handler = NULL;
|
fields[2].in_handler = NULL;
|
||||||
fields[2].in_handler_priv = NULL;
|
fields[2].in_handler_priv = NULL;
|
||||||
|
|
||||||
jtag_add_dr_scan(3, fields, -1);
|
jtag_add_dr_scan(3, fields, TAP_INVALID);
|
||||||
|
|
||||||
fields[0].in_handler_priv = value;
|
fields[0].in_handler_priv = value;
|
||||||
fields[0].in_handler = arm_jtag_buf_to_u32;
|
fields[0].in_handler = arm_jtag_buf_to_u32;
|
||||||
|
|
||||||
jtag_add_dr_scan(3, fields, -1);
|
jtag_add_dr_scan(3, fields, TAP_INVALID);
|
||||||
|
|
||||||
#ifdef _DEBUG_INSTRUCTION_EXECUTION_
|
#ifdef _DEBUG_INSTRUCTION_EXECUTION_
|
||||||
if((retval = jtag_execute_queue()) != ERROR_OK)
|
if((retval = jtag_execute_queue()) != ERROR_OK)
|
||||||
|
|
@ -282,7 +282,7 @@ int arm966e_write_cp15(target_t *target, int reg_addr, u32 value)
|
||||||
fields[2].in_handler = NULL;
|
fields[2].in_handler = NULL;
|
||||||
fields[2].in_handler_priv = NULL;
|
fields[2].in_handler_priv = NULL;
|
||||||
|
|
||||||
jtag_add_dr_scan(3, fields, -1);
|
jtag_add_dr_scan(3, fields, TAP_INVALID);
|
||||||
|
|
||||||
#ifdef _DEBUG_INSTRUCTION_EXECUTION_
|
#ifdef _DEBUG_INSTRUCTION_EXECUTION_
|
||||||
LOG_DEBUG("addr: 0x%x value: %8.8x", reg_addr, value);
|
LOG_DEBUG("addr: 0x%x value: %8.8x", reg_addr, value);
|
||||||
|
|
|
||||||
|
|
@ -253,9 +253,9 @@ int arm9tdmi_clock_out(arm_jtag_t *jtag_info, u32 instr, u32 out, u32 *in, int s
|
||||||
fields[2].in_handler = NULL;
|
fields[2].in_handler = NULL;
|
||||||
fields[2].in_handler_priv = NULL;
|
fields[2].in_handler_priv = NULL;
|
||||||
|
|
||||||
jtag_add_dr_scan(3, fields, -1);
|
jtag_add_dr_scan(3, fields, TAP_INVALID);
|
||||||
|
|
||||||
jtag_add_runtest(0, -1);
|
jtag_add_runtest(0, TAP_INVALID);
|
||||||
|
|
||||||
#ifdef _DEBUG_INSTRUCTION_EXECUTION_
|
#ifdef _DEBUG_INSTRUCTION_EXECUTION_
|
||||||
{
|
{
|
||||||
|
|
@ -320,9 +320,9 @@ int arm9tdmi_clock_data_in(arm_jtag_t *jtag_info, u32 *in)
|
||||||
fields[2].in_handler = NULL;
|
fields[2].in_handler = NULL;
|
||||||
fields[2].in_handler_priv = NULL;
|
fields[2].in_handler_priv = NULL;
|
||||||
|
|
||||||
jtag_add_dr_scan(3, fields, -1);
|
jtag_add_dr_scan(3, fields, TAP_INVALID);
|
||||||
|
|
||||||
jtag_add_runtest(0, -1);
|
jtag_add_runtest(0, TAP_INVALID);
|
||||||
|
|
||||||
#ifdef _DEBUG_INSTRUCTION_EXECUTION_
|
#ifdef _DEBUG_INSTRUCTION_EXECUTION_
|
||||||
{
|
{
|
||||||
|
|
@ -403,9 +403,9 @@ int arm9tdmi_clock_data_in_endianness(arm_jtag_t *jtag_info, void *in, int size,
|
||||||
fields[2].in_handler = NULL;
|
fields[2].in_handler = NULL;
|
||||||
fields[2].in_handler_priv = NULL;
|
fields[2].in_handler_priv = NULL;
|
||||||
|
|
||||||
jtag_add_dr_scan(3, fields, -1);
|
jtag_add_dr_scan(3, fields, TAP_INVALID);
|
||||||
|
|
||||||
jtag_add_runtest(0, -1);
|
jtag_add_runtest(0, TAP_INVALID);
|
||||||
|
|
||||||
#ifdef _DEBUG_INSTRUCTION_EXECUTION_
|
#ifdef _DEBUG_INSTRUCTION_EXECUTION_
|
||||||
{
|
{
|
||||||
|
|
|
||||||
|
|
@ -58,7 +58,7 @@ int arm_jtag_set_instr(arm_jtag_t *jtag_info, u32 new_instr, in_handler_t handl
|
||||||
field.in_check_mask = NULL;
|
field.in_check_mask = NULL;
|
||||||
field.in_handler = handler;
|
field.in_handler = handler;
|
||||||
field.in_handler_priv = NULL;
|
field.in_handler_priv = NULL;
|
||||||
jtag_add_ir_scan(1, &field, -1);
|
jtag_add_ir_scan(1, &field, TAP_INVALID);
|
||||||
}
|
}
|
||||||
|
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
|
|
@ -84,7 +84,7 @@ int arm_jtag_scann(arm_jtag_t *jtag_info, u32 new_scan_chain)
|
||||||
1,
|
1,
|
||||||
num_bits,
|
num_bits,
|
||||||
values,
|
values,
|
||||||
-1);
|
TAP_INVALID);
|
||||||
|
|
||||||
jtag_info->cur_scan_chain = new_scan_chain;
|
jtag_info->cur_scan_chain = new_scan_chain;
|
||||||
}
|
}
|
||||||
|
|
|
||||||
|
|
@ -91,7 +91,7 @@ int swjdp_scan(arm_jtag_t *jtag_info, u8 instr, u8 reg_addr, u8 RnW, u8 *outvalu
|
||||||
fields[1].in_check_value = NULL;
|
fields[1].in_check_value = NULL;
|
||||||
fields[1].in_check_mask = NULL;
|
fields[1].in_check_mask = NULL;
|
||||||
|
|
||||||
jtag_add_dr_scan(2, fields, -1);
|
jtag_add_dr_scan(2, fields, TAP_INVALID);
|
||||||
|
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
@ -136,7 +136,7 @@ int swjdp_scan_u32(arm_jtag_t *jtag_info, u8 instr, u8 reg_addr, u8 RnW, u32 out
|
||||||
fields[1].in_check_value = NULL;
|
fields[1].in_check_value = NULL;
|
||||||
fields[1].in_check_mask = NULL;
|
fields[1].in_check_mask = NULL;
|
||||||
|
|
||||||
jtag_add_dr_scan(2, fields, -1);
|
jtag_add_dr_scan(2, fields, TAP_INVALID);
|
||||||
|
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
|
||||||
|
|
@ -283,7 +283,7 @@ int embeddedice_read_reg_w_check(reg_t *reg, u8* check_value, u8* check_mask)
|
||||||
fields[2].in_handler = NULL;
|
fields[2].in_handler = NULL;
|
||||||
fields[2].in_handler_priv = NULL;
|
fields[2].in_handler_priv = NULL;
|
||||||
|
|
||||||
jtag_add_dr_scan(3, fields, -1);
|
jtag_add_dr_scan(3, fields, TAP_INVALID);
|
||||||
|
|
||||||
fields[0].in_value = reg->value;
|
fields[0].in_value = reg->value;
|
||||||
jtag_set_check_value(fields+0, check_value, check_mask, NULL);
|
jtag_set_check_value(fields+0, check_value, check_mask, NULL);
|
||||||
|
|
@ -294,7 +294,7 @@ int embeddedice_read_reg_w_check(reg_t *reg, u8* check_value, u8* check_mask)
|
||||||
*/
|
*/
|
||||||
buf_set_u32(fields[1].out_value, 0, 5, embeddedice_reg_arch_info[EICE_COMMS_CTRL]);
|
buf_set_u32(fields[1].out_value, 0, 5, embeddedice_reg_arch_info[EICE_COMMS_CTRL]);
|
||||||
|
|
||||||
jtag_add_dr_scan(3, fields, -1);
|
jtag_add_dr_scan(3, fields, TAP_INVALID);
|
||||||
|
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
@ -345,7 +345,7 @@ int embeddedice_receive(arm_jtag_t *jtag_info, u32 *data, u32 size)
|
||||||
fields[2].in_handler = NULL;
|
fields[2].in_handler = NULL;
|
||||||
fields[2].in_handler_priv = NULL;
|
fields[2].in_handler_priv = NULL;
|
||||||
|
|
||||||
jtag_add_dr_scan(3, fields, -1);
|
jtag_add_dr_scan(3, fields, TAP_INVALID);
|
||||||
|
|
||||||
while (size > 0)
|
while (size > 0)
|
||||||
{
|
{
|
||||||
|
|
@ -357,7 +357,7 @@ int embeddedice_receive(arm_jtag_t *jtag_info, u32 *data, u32 size)
|
||||||
|
|
||||||
fields[0].in_handler = arm_jtag_buf_to_u32;
|
fields[0].in_handler = arm_jtag_buf_to_u32;
|
||||||
fields[0].in_handler_priv = data;
|
fields[0].in_handler_priv = data;
|
||||||
jtag_add_dr_scan(3, fields, -1);
|
jtag_add_dr_scan(3, fields, TAP_INVALID);
|
||||||
|
|
||||||
data++;
|
data++;
|
||||||
size--;
|
size--;
|
||||||
|
|
@ -465,7 +465,7 @@ int embeddedice_send(arm_jtag_t *jtag_info, u32 *data, u32 size)
|
||||||
while (size > 0)
|
while (size > 0)
|
||||||
{
|
{
|
||||||
buf_set_u32(fields[0].out_value, 0, 32, *data);
|
buf_set_u32(fields[0].out_value, 0, 32, *data);
|
||||||
jtag_add_dr_scan(3, fields, -1);
|
jtag_add_dr_scan(3, fields, TAP_INVALID);
|
||||||
|
|
||||||
data++;
|
data++;
|
||||||
size--;
|
size--;
|
||||||
|
|
@ -531,11 +531,11 @@ int embeddedice_handshake(arm_jtag_t *jtag_info, int hsbit, u32 timeout)
|
||||||
fields[2].in_handler = NULL;
|
fields[2].in_handler = NULL;
|
||||||
fields[2].in_handler_priv = NULL;
|
fields[2].in_handler_priv = NULL;
|
||||||
|
|
||||||
jtag_add_dr_scan(3, fields, -1);
|
jtag_add_dr_scan(3, fields, TAP_INVALID);
|
||||||
gettimeofday(&lap, NULL);
|
gettimeofday(&lap, NULL);
|
||||||
do
|
do
|
||||||
{
|
{
|
||||||
jtag_add_dr_scan(3, fields, -1);
|
jtag_add_dr_scan(3, fields, TAP_INVALID);
|
||||||
if ((retval = jtag_execute_queue()) != ERROR_OK)
|
if ((retval = jtag_execute_queue()) != ERROR_OK)
|
||||||
return retval;
|
return retval;
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -124,7 +124,7 @@ static __inline__ void embeddedice_write_reg_inner( jtag_tap_t *tap, int reg_add
|
||||||
3,
|
3,
|
||||||
embeddedice_num_bits,
|
embeddedice_num_bits,
|
||||||
values,
|
values,
|
||||||
-1);
|
TAP_INVALID);
|
||||||
}
|
}
|
||||||
|
|
||||||
void embeddedice_write_dcc(jtag_tap_t *tap, int reg_addr, u8 *buffer, int little, int count);
|
void embeddedice_write_dcc(jtag_tap_t *tap, int reg_addr, u8 *buffer, int little, int count);
|
||||||
|
|
|
||||||
|
|
@ -82,7 +82,7 @@ int etb_set_instr(etb_t *etb, u32 new_instr)
|
||||||
field.in_handler = NULL;
|
field.in_handler = NULL;
|
||||||
field.in_handler_priv = NULL;
|
field.in_handler_priv = NULL;
|
||||||
|
|
||||||
jtag_add_ir_scan(1, &field, -1);
|
jtag_add_ir_scan(1, &field, TAP_INVALID);
|
||||||
|
|
||||||
free(field.out_value);
|
free(field.out_value);
|
||||||
}
|
}
|
||||||
|
|
@ -109,7 +109,7 @@ int etb_scann(etb_t *etb, u32 new_scan_chain)
|
||||||
|
|
||||||
/* select INTEST instruction */
|
/* select INTEST instruction */
|
||||||
etb_set_instr(etb, 0x2);
|
etb_set_instr(etb, 0x2);
|
||||||
jtag_add_dr_scan(1, &field, -1);
|
jtag_add_dr_scan(1, &field, TAP_INVALID);
|
||||||
|
|
||||||
etb->cur_scan_chain = new_scan_chain;
|
etb->cur_scan_chain = new_scan_chain;
|
||||||
|
|
||||||
|
|
@ -220,7 +220,7 @@ int etb_read_ram(etb_t *etb, u32 *data, int num_frames)
|
||||||
fields[2].in_handler = NULL;
|
fields[2].in_handler = NULL;
|
||||||
fields[2].in_handler_priv = NULL;
|
fields[2].in_handler_priv = NULL;
|
||||||
|
|
||||||
jtag_add_dr_scan(3, fields, -1);
|
jtag_add_dr_scan(3, fields, TAP_INVALID);
|
||||||
|
|
||||||
fields[0].in_handler = buf_to_u32_handler;
|
fields[0].in_handler = buf_to_u32_handler;
|
||||||
|
|
||||||
|
|
@ -236,7 +236,7 @@ int etb_read_ram(etb_t *etb, u32 *data, int num_frames)
|
||||||
buf_set_u32(fields[1].out_value, 0, 7, 0);
|
buf_set_u32(fields[1].out_value, 0, 7, 0);
|
||||||
|
|
||||||
fields[0].in_handler_priv = &data[i];
|
fields[0].in_handler_priv = &data[i];
|
||||||
jtag_add_dr_scan(3, fields, -1);
|
jtag_add_dr_scan(3, fields, TAP_INVALID);
|
||||||
}
|
}
|
||||||
|
|
||||||
jtag_execute_queue();
|
jtag_execute_queue();
|
||||||
|
|
@ -291,7 +291,7 @@ int etb_read_reg_w_check(reg_t *reg, u8* check_value, u8* check_mask)
|
||||||
fields[2].in_handler = NULL;
|
fields[2].in_handler = NULL;
|
||||||
fields[2].in_handler_priv = NULL;
|
fields[2].in_handler_priv = NULL;
|
||||||
|
|
||||||
jtag_add_dr_scan(3, fields, -1);
|
jtag_add_dr_scan(3, fields, TAP_INVALID);
|
||||||
|
|
||||||
/* read the identification register in the second run, to make sure we
|
/* read the identification register in the second run, to make sure we
|
||||||
* don't read the ETB data register twice, skipping every second entry
|
* don't read the ETB data register twice, skipping every second entry
|
||||||
|
|
@ -301,7 +301,7 @@ int etb_read_reg_w_check(reg_t *reg, u8* check_value, u8* check_mask)
|
||||||
|
|
||||||
jtag_set_check_value(fields+0, check_value, check_mask, NULL);
|
jtag_set_check_value(fields+0, check_value, check_mask, NULL);
|
||||||
|
|
||||||
jtag_add_dr_scan(3, fields, -1);
|
jtag_add_dr_scan(3, fields, TAP_INVALID);
|
||||||
|
|
||||||
free(fields[1].out_value);
|
free(fields[1].out_value);
|
||||||
free(fields[2].out_value);
|
free(fields[2].out_value);
|
||||||
|
|
@ -388,7 +388,7 @@ int etb_write_reg(reg_t *reg, u32 value)
|
||||||
fields[2].in_handler = NULL;
|
fields[2].in_handler = NULL;
|
||||||
fields[2].in_handler_priv = NULL;
|
fields[2].in_handler_priv = NULL;
|
||||||
|
|
||||||
jtag_add_dr_scan(3, fields, -1);
|
jtag_add_dr_scan(3, fields, TAP_INVALID);
|
||||||
|
|
||||||
free(fields[0].out_value);
|
free(fields[0].out_value);
|
||||||
free(fields[1].out_value);
|
free(fields[1].out_value);
|
||||||
|
|
|
||||||
|
|
@ -371,12 +371,12 @@ int etm_read_reg_w_check(reg_t *reg, u8* check_value, u8* check_mask)
|
||||||
fields[2].in_handler = NULL;
|
fields[2].in_handler = NULL;
|
||||||
fields[2].in_handler_priv = NULL;
|
fields[2].in_handler_priv = NULL;
|
||||||
|
|
||||||
jtag_add_dr_scan(3, fields, -1);
|
jtag_add_dr_scan(3, fields, TAP_INVALID);
|
||||||
|
|
||||||
fields[0].in_value = reg->value;
|
fields[0].in_value = reg->value;
|
||||||
jtag_set_check_value(fields+0, check_value, check_mask, NULL);
|
jtag_set_check_value(fields+0, check_value, check_mask, NULL);
|
||||||
|
|
||||||
jtag_add_dr_scan(3, fields, -1);
|
jtag_add_dr_scan(3, fields, TAP_INVALID);
|
||||||
|
|
||||||
free(fields[1].out_value);
|
free(fields[1].out_value);
|
||||||
free(fields[2].out_value);
|
free(fields[2].out_value);
|
||||||
|
|
@ -463,7 +463,7 @@ int etm_write_reg(reg_t *reg, u32 value)
|
||||||
fields[2].in_handler = NULL;
|
fields[2].in_handler = NULL;
|
||||||
fields[2].in_handler_priv = NULL;
|
fields[2].in_handler_priv = NULL;
|
||||||
|
|
||||||
jtag_add_dr_scan(3, fields, -1);
|
jtag_add_dr_scan(3, fields, TAP_INVALID);
|
||||||
|
|
||||||
free(fields[0].out_value);
|
free(fields[0].out_value);
|
||||||
free(fields[1].out_value);
|
free(fields[1].out_value);
|
||||||
|
|
@ -883,7 +883,7 @@ int etmv1_analyze_trace(etm_context_t *ctx, struct command_context_s *cmd_ctx)
|
||||||
continue;
|
continue;
|
||||||
|
|
||||||
/* indirect branch to the exception vector means an exception occured */
|
/* indirect branch to the exception vector means an exception occured */
|
||||||
if (((ctx->last_branch >= 0x0) && (ctx->last_branch <= 0x20))
|
if ((ctx->last_branch <= 0x20)
|
||||||
|| ((ctx->last_branch >= 0xffff0000) && (ctx->last_branch <= 0xffff0020)))
|
|| ((ctx->last_branch >= 0xffff0000) && (ctx->last_branch <= 0xffff0020)))
|
||||||
{
|
{
|
||||||
if ((ctx->last_branch & 0xff) == 0x10)
|
if ((ctx->last_branch & 0xff) == 0x10)
|
||||||
|
|
|
||||||
|
|
@ -162,9 +162,9 @@ int feroceon_dummy_clock_out(arm_jtag_t *jtag_info, u32 instr)
|
||||||
fields[2].in_handler = NULL;
|
fields[2].in_handler = NULL;
|
||||||
fields[2].in_handler_priv = NULL;
|
fields[2].in_handler_priv = NULL;
|
||||||
|
|
||||||
jtag_add_dr_scan(3, fields, -1);
|
jtag_add_dr_scan(3, fields, TAP_INVALID);
|
||||||
|
|
||||||
/* no jtag_add_runtest(0, -1) here */
|
/* no jtag_add_runtest(0, TAP_INVALID) here */
|
||||||
|
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
|
||||||
|
|
@ -55,7 +55,7 @@ int mips_ejtag_set_instr(mips_ejtag_t *ejtag_info, int new_instr, in_handler_t h
|
||||||
field.in_check_mask = NULL;
|
field.in_check_mask = NULL;
|
||||||
field.in_handler = handler;
|
field.in_handler = handler;
|
||||||
field.in_handler_priv = NULL;
|
field.in_handler_priv = NULL;
|
||||||
jtag_add_ir_scan(1, &field, -1);
|
jtag_add_ir_scan(1, &field, TAP_INVALID);
|
||||||
}
|
}
|
||||||
|
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
|
|
@ -78,7 +78,7 @@ int mips_ejtag_get_idcode(mips_ejtag_t *ejtag_info, u32 *idcode, in_handler_t ha
|
||||||
field.in_check_mask = NULL;
|
field.in_check_mask = NULL;
|
||||||
field.in_handler = NULL;
|
field.in_handler = NULL;
|
||||||
field.in_handler_priv = NULL;
|
field.in_handler_priv = NULL;
|
||||||
jtag_add_dr_scan(1, &field, -1);
|
jtag_add_dr_scan(1, &field, TAP_INVALID);
|
||||||
|
|
||||||
if (jtag_execute_queue() != ERROR_OK)
|
if (jtag_execute_queue() != ERROR_OK)
|
||||||
{
|
{
|
||||||
|
|
@ -105,7 +105,7 @@ int mips_ejtag_get_impcode(mips_ejtag_t *ejtag_info, u32 *impcode, in_handler_t
|
||||||
field.in_check_mask = NULL;
|
field.in_check_mask = NULL;
|
||||||
field.in_handler = NULL;
|
field.in_handler = NULL;
|
||||||
field.in_handler_priv = NULL;
|
field.in_handler_priv = NULL;
|
||||||
jtag_add_dr_scan(1, &field, -1);
|
jtag_add_dr_scan(1, &field, TAP_INVALID);
|
||||||
|
|
||||||
if (jtag_execute_queue() != ERROR_OK)
|
if (jtag_execute_queue() != ERROR_OK)
|
||||||
{
|
{
|
||||||
|
|
@ -136,7 +136,7 @@ int mips_ejtag_drscan_32(mips_ejtag_t *ejtag_info, u32 *data)
|
||||||
field.in_check_mask = NULL;
|
field.in_check_mask = NULL;
|
||||||
field.in_handler = NULL;
|
field.in_handler = NULL;
|
||||||
field.in_handler_priv = NULL;
|
field.in_handler_priv = NULL;
|
||||||
jtag_add_dr_scan(1, &field, -1);
|
jtag_add_dr_scan(1, &field, TAP_INVALID);
|
||||||
|
|
||||||
if ((retval = jtag_execute_queue()) != ERROR_OK)
|
if ((retval = jtag_execute_queue()) != ERROR_OK)
|
||||||
{
|
{
|
||||||
|
|
|
||||||
|
|
@ -229,7 +229,7 @@ int xscale_jtag_set_instr(jtag_tap_t *tap, u32 new_instr)
|
||||||
field.in_value = NULL;
|
field.in_value = NULL;
|
||||||
jtag_set_check_value(&field, tap->expected, tap->expected_mask, NULL);
|
jtag_set_check_value(&field, tap->expected, tap->expected_mask, NULL);
|
||||||
|
|
||||||
jtag_add_ir_scan(1, &field, -1);
|
jtag_add_ir_scan(1, &field, TAP_INVALID);
|
||||||
|
|
||||||
free(field.out_value);
|
free(field.out_value);
|
||||||
}
|
}
|
||||||
|
|
@ -282,7 +282,7 @@ int xscale_read_dcsr(target_t *target)
|
||||||
fields[2].in_value = NULL;
|
fields[2].in_value = NULL;
|
||||||
jtag_set_check_value(fields+2, &field2_check_value, &field2_check_mask, NULL);
|
jtag_set_check_value(fields+2, &field2_check_value, &field2_check_mask, NULL);
|
||||||
|
|
||||||
jtag_add_dr_scan(3, fields, -1);
|
jtag_add_dr_scan(3, fields, TAP_INVALID);
|
||||||
|
|
||||||
if ((retval = jtag_execute_queue()) != ERROR_OK)
|
if ((retval = jtag_execute_queue()) != ERROR_OK)
|
||||||
{
|
{
|
||||||
|
|
@ -302,7 +302,7 @@ int xscale_read_dcsr(target_t *target)
|
||||||
|
|
||||||
jtag_add_end_state(TAP_IDLE);
|
jtag_add_end_state(TAP_IDLE);
|
||||||
|
|
||||||
jtag_add_dr_scan(3, fields, -1);
|
jtag_add_dr_scan(3, fields, TAP_INVALID);
|
||||||
|
|
||||||
/* DANGER!!! this must be here. It will make sure that the arguments
|
/* DANGER!!! this must be here. It will make sure that the arguments
|
||||||
* to jtag_set_check_value() does not go out of scope! */
|
* to jtag_set_check_value() does not go out of scope! */
|
||||||
|
|
@ -362,7 +362,7 @@ int xscale_receive(target_t *target, u32 *buffer, int num_words)
|
||||||
|
|
||||||
jtag_add_end_state(TAP_IDLE);
|
jtag_add_end_state(TAP_IDLE);
|
||||||
xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.dbgtx);
|
xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.dbgtx);
|
||||||
jtag_add_runtest(1, -1); /* ensures that we're in the TAP_IDLE state as the above could be a no-op */
|
jtag_add_runtest(1, TAP_INVALID); /* ensures that we're in the TAP_IDLE state as the above could be a no-op */
|
||||||
|
|
||||||
/* repeat until all words have been collected */
|
/* repeat until all words have been collected */
|
||||||
int attempts=0;
|
int attempts=0;
|
||||||
|
|
@ -750,7 +750,7 @@ int xscale_write_dcsr(target_t *target, int hold_rst, int ext_dbg_brk)
|
||||||
fields[2].in_value = NULL;
|
fields[2].in_value = NULL;
|
||||||
jtag_set_check_value(fields+2, &field2_check_value, &field2_check_mask, NULL);
|
jtag_set_check_value(fields+2, &field2_check_value, &field2_check_mask, NULL);
|
||||||
|
|
||||||
jtag_add_dr_scan(3, fields, -1);
|
jtag_add_dr_scan(3, fields, TAP_INVALID);
|
||||||
|
|
||||||
if ((retval = jtag_execute_queue()) != ERROR_OK)
|
if ((retval = jtag_execute_queue()) != ERROR_OK)
|
||||||
{
|
{
|
||||||
|
|
@ -822,7 +822,7 @@ int xscale_load_ic(target_t *target, int mini, u32 va, u32 buffer[8])
|
||||||
fields[1].in_handler = NULL;
|
fields[1].in_handler = NULL;
|
||||||
fields[1].in_handler_priv = NULL;
|
fields[1].in_handler_priv = NULL;
|
||||||
|
|
||||||
jtag_add_dr_scan(2, fields, -1);
|
jtag_add_dr_scan(2, fields, TAP_INVALID);
|
||||||
|
|
||||||
fields[0].num_bits = 32;
|
fields[0].num_bits = 32;
|
||||||
fields[0].out_value = packet;
|
fields[0].out_value = packet;
|
||||||
|
|
@ -834,7 +834,7 @@ int xscale_load_ic(target_t *target, int mini, u32 va, u32 buffer[8])
|
||||||
{
|
{
|
||||||
buf_set_u32(packet, 0, 32, buffer[word]);
|
buf_set_u32(packet, 0, 32, buffer[word]);
|
||||||
cmd = parity(*((u32*)packet));
|
cmd = parity(*((u32*)packet));
|
||||||
jtag_add_dr_scan(2, fields, -1);
|
jtag_add_dr_scan(2, fields, TAP_INVALID);
|
||||||
}
|
}
|
||||||
|
|
||||||
jtag_execute_queue();
|
jtag_execute_queue();
|
||||||
|
|
@ -880,7 +880,7 @@ int xscale_invalidate_ic_line(target_t *target, u32 va)
|
||||||
fields[1].in_handler = NULL;
|
fields[1].in_handler = NULL;
|
||||||
fields[1].in_handler_priv = NULL;
|
fields[1].in_handler_priv = NULL;
|
||||||
|
|
||||||
jtag_add_dr_scan(2, fields, -1);
|
jtag_add_dr_scan(2, fields, TAP_INVALID);
|
||||||
|
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue