Code cleanup. Bump debug_defines.h version
parent
bf0ffff1db
commit
0b027a2854
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@ -57,12 +57,6 @@ static void riscv013_fill_dmi_write_u64(struct target *target, char *buf, int a,
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static void riscv013_fill_dmi_read_u64(struct target *target, char *buf, int a);
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static int riscv013_dmi_write_u64_bits(struct target *target);
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static void riscv013_fill_dmi_nop_u64(struct target *target, char *buf);
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static int riscv013_test_sba_config_reg(struct target *target, target_addr_t legal_address,
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uint32_t num_words, target_addr_t illegal_address, bool run_sbbusyerror_test);
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void write_memory_sba_simple(struct target *target, target_addr_t addr, uint32_t* write_data,
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uint32_t write_size, uint32_t sbcs);
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void read_memory_sba_simple(struct target *target, target_addr_t addr,
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uint32_t *rd_buf, uint32_t read_size, uint32_t sbcs);
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static int register_read_direct(struct target *target, uint64_t *value, uint32_t number);
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static int register_write_direct(struct target *target, unsigned number,
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uint64_t value);
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@ -70,6 +64,12 @@ static int read_memory(struct target *target, target_addr_t address,
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uint32_t size, uint32_t count, uint8_t *buffer);
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static int write_memory(struct target *target, target_addr_t address,
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uint32_t size, uint32_t count, const uint8_t *buffer);
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static int riscv013_test_sba_config_reg(struct target *target, target_addr_t legal_address,
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uint32_t num_words, target_addr_t illegal_address, bool run_sbbusyerror_test);
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void write_memory_sba_simple(struct target *target, target_addr_t addr, uint32_t* write_data,
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uint32_t write_size, uint32_t sbcs);
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void read_memory_sba_simple(struct target *target, target_addr_t addr,
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uint32_t *rd_buf, uint32_t read_size, uint32_t sbcs);
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/**
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* Since almost everything can be accomplish by scanning the dbus register, all
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@ -269,7 +269,7 @@ static dm013_info_t *get_dm(struct target *target)
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static uint32_t hartsel_mask(const struct target *target)
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{
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RISCV013_INFO(info);
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return ((1L<<info->hartsellen)-1) << DMI_DMCONTROL_HARTSEL_OFFSET;
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return ((1L<<info->hartsellen)-1) << DMI_DMCONTROL_HARTSELLO_OFFSET;
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}
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static void decode_dmi(char *text, unsigned address, unsigned data)
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@ -283,7 +283,7 @@ static void decode_dmi(char *text, unsigned address, unsigned data)
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{ DMI_DMCONTROL, DMI_DMCONTROL_RESUMEREQ, "resumereq" },
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{ DMI_DMCONTROL, DMI_DMCONTROL_HARTRESET, "hartreset" },
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{ DMI_DMCONTROL, DMI_DMCONTROL_HASEL, "hasel" },
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{ DMI_DMCONTROL, ((1L<<10)-1) << DMI_DMCONTROL_HARTSEL_OFFSET, "hartsel" },
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{ DMI_DMCONTROL, ((1L<<10)-1) << DMI_DMCONTROL_HARTSELLO_OFFSET, "hartsel" },
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{ DMI_DMCONTROL, DMI_DMCONTROL_NDMRESET, "ndmreset" },
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{ DMI_DMCONTROL, DMI_DMCONTROL_DMACTIVE, "dmactive" },
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@ -1288,7 +1288,7 @@ static int examine(struct target *target)
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dm->was_reset = true;
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}
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uint32_t max_hartsel_mask = ((1L<<10)-1) << DMI_DMCONTROL_HARTSEL_OFFSET;
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uint32_t max_hartsel_mask = ((1L<<10)-1) << DMI_DMCONTROL_HARTSELLO_OFFSET;
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dmi_write(target, DMI_DMCONTROL, max_hartsel_mask | DMI_DMCONTROL_DMACTIVE);
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uint32_t dmcontrol;
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if (dmi_read(target, &dmcontrol, DMI_DMCONTROL) != ERROR_OK)
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@ -1494,11 +1494,11 @@ static int init_target(struct command_context *cmd_ctx,
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generic_info->fill_dmi_read_u64 = &riscv013_fill_dmi_read_u64;
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generic_info->fill_dmi_nop_u64 = &riscv013_fill_dmi_nop_u64;
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generic_info->dmi_write_u64_bits = &riscv013_dmi_write_u64_bits;
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generic_info->test_sba_config_reg = &riscv013_test_sba_config_reg;
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generic_info->authdata_read = &riscv013_authdata_read;
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generic_info->authdata_write = &riscv013_authdata_write;
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generic_info->dmi_read = &dmi_read;
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generic_info->dmi_write = &dmi_write;
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generic_info->test_sba_config_reg = &riscv013_test_sba_config_reg;
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generic_info->version_specific = calloc(1, sizeof(riscv013_info_t));
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if (!generic_info->version_specific)
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return ERROR_FAIL;
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@ -2818,6 +2818,7 @@ void riscv013_fill_dmi_nop_u64(struct target *target, char *buf)
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buf_set_u64((unsigned char *)buf, DTM_DMI_ADDRESS_OFFSET, info->abits, 0);
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}
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/* Helper function for riscv013_test_sba_config_reg */
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static int get_max_sbaccess(struct target *target)
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{
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RISCV013_INFO(info);
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@ -2847,7 +2848,7 @@ static uint32_t get_num_sbdata_regs(struct target *target)
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RISCV013_INFO(info);
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uint32_t sbaccess128 = get_field(info->sbcs, DMI_SBCS_SBACCESS128);
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uint32_t sbaccess64 = get_field(info->sbcs, DMI_SBCS_SBACCESS64);
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uint32_t sbaccess64 = get_field(info->sbcs, DMI_SBCS_SBACCESS64);
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if (sbaccess128)
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return 4;
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@ -2939,7 +2940,7 @@ static int riscv013_test_sba_config_reg(struct target *target,
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prev_addr = curr_addr;
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read_sbcs_nonbusy(target, &sbcs);
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curr_addr = sb_read_address(target);
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if ((curr_addr - prev_addr != (uint32_t)(1 << sbaccess)) && i != 0) {
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if ((curr_addr - prev_addr != (uint32_t)(1 << sbaccess)) && (i != 0)) {
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LOG_ERROR("System Bus Access Test 2: Error with address auto-increment, sbaccess = %x", sbaccess);
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test_passed = false;
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}
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@ -2959,7 +2960,7 @@ static int riscv013_test_sba_config_reg(struct target *target,
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prev_addr = curr_addr;
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read_sbcs_nonbusy(target, &sbcs);
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curr_addr = sb_read_address(target);
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if ((curr_addr - prev_addr != (uint32_t)(1 << sbaccess)) && i != 0) {
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if ((curr_addr - prev_addr != (uint32_t)(1 << sbaccess)) && (i != 0)) {
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LOG_ERROR("System Bus Access Test 2: Error with address auto-increment, sbaccess = %x", sbaccess);
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test_passed = false;
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}
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@ -3010,7 +3011,7 @@ static int riscv013_test_sba_config_reg(struct target *target,
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write_memory_sba_simple(target, legal_address, test_patterns, 1, sbcs);
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dmi_read(target, &rd_val, DMI_SBCS);
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if (get_field(rd_val, DMI_SBCS_SBERROR) == 3) {
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if (get_field(rd_val, DMI_SBCS_SBERROR) == 4) {
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sbcs = set_field(sbcs_orig, DMI_SBCS_SBERROR, 1);
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dmi_write(target, DMI_SBCS, sbcs);
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dmi_read(target, &rd_val, DMI_SBCS);
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