zcy
/
tinyriscv-openocd
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

bitrot: fix numerous syntax errors 

added correct jtag device id

git-svn-id: svn://svn.berlios.de/openocd/trunk@2467 b42882b7-edfa-0310-969c-e2dbd0fdcd60
__archive__
oharboe 2009-07-06 08:05:58 +00:00
parent e2dd1dbab9
commit 0ab8e710db
1 changed files with 6 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

14
tcl/board/digi_connectcore_wi-9c.cfg
View File

@ -26,7 +26,7 @@ jtag_rclk 1000
if { [info exists CPUTAPID ] } {
set _CPUTAPID $CPUTAPID
} else {
set _CPUTAPID 0xFFFFFFFF
set _CPUTAPID 0x07926031
}
set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
@ -41,6 +41,7 @@ jtag_ntrst_delay 0
######################
target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm926ejs
$_TARGETNAME configure -event reset-init {
mww 0x90600104 0x33313333
mww 0xA0700000 0x00000001 # Enable the memory controller.
@ -99,12 +100,12 @@ $_TARGETNAME configure -event reset-init {
mww 0xA0700160 0x00084280 # Enable buffer access
#Set byte lane state (static mem 1)"
mww 0xA0700220, 0x00000082
mww 0xA0700220 0x00000082
#Flash Start
mww 0xA09001F8, 0x50000000
mww 0xA09001F8 0x50000000
#Flash Mask Reg
mww 0xA09001FC, 0xFF000001
mww 0xA0700028, 0x00000001
mww 0xA09001FC 0xFF000001
mww 0xA0700028 0x00000001
# RAMAddr = 0x00020000
# RAMSize = 0x00004000
@ -122,6 +123,3 @@ $_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x00000000 -work-area-s
#M29DW323DB - not working
#flash bank cfi <base> <size> <chip width> <bus width> <target#>
flash bank cfi 0x50000000 0x0400000 2 2 0