mips32, drop unnecessary code in mips32_pracc.c
Struct mips32_pracc_context no more in use. In current code cp0 reg/sel do not requires special handling. In sync mode ctx.store_count not used, drop check. In fasdata transfer function use mips32_pracc_read_ctrl_addr() to reduce code. Change-Id: Ibd4cfa5a44ebc106ed0db042f4e54a2e0b3d43cb Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es> Reviewed-on: http://openocd.zylin.com/4007 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>gitignore-build
parent
7ccd53bdde
commit
09ebc1afad
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@ -73,16 +73,6 @@
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#include "mips32.h"
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#include "mips32_pracc.h"
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struct mips32_pracc_context {
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uint32_t *local_oparam;
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int num_oparam;
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const uint32_t *code;
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int code_len;
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uint32_t stack[32];
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int stack_offset;
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struct mips_ejtag *ejtag_info;
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};
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static int wait_for_pracc_rw(struct mips_ejtag *ejtag_info, uint32_t *ctrl)
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{
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uint32_t ejtag_ctrl;
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@ -564,10 +554,10 @@ int mips32_cp0_read(struct mips_ejtag *ejtag_info, uint32_t *val, uint32_t cp0_r
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goto exit;
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pracc_add(&ctx, 0, MIPS32_LUI(15, PRACC_UPPER_BASE_ADDR)); /* $15 = MIPS32_PRACC_BASE_ADDR */
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pracc_add(&ctx, 0, MIPS32_MFC0(8, 0, 0) | (cp0_reg << 11) | cp0_sel); /* move COP0 [cp0_reg select] to $8 */
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pracc_add(&ctx, 0, MIPS32_MFC0(8, cp0_reg, cp0_sel)); /* move cp0 reg / sel to $8 */
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pracc_add(&ctx, MIPS32_PRACC_PARAM_OUT,
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MIPS32_SW(8, PRACC_OUT_OFFSET, 15)); /* store $8 to pracc_out */
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pracc_add(&ctx, 0, MIPS32_MFC0(15, 31, 0)); /* move COP0 DeSave to $15 */
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pracc_add(&ctx, 0, MIPS32_MFC0(15, 31, 0)); /* restore $15 from DeSave */
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pracc_add(&ctx, 0, MIPS32_LUI(8, UPPER16(ejtag_info->reg8))); /* restore upper 16 bits of $8 */
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pracc_add(&ctx, 0, MIPS32_B(NEG16(ctx.code_count + 1))); /* jump to start */
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pracc_add(&ctx, 0, MIPS32_ORI(8, 8, LOWER16(ejtag_info->reg8))); /* restore lower 16 bits of $8 */
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@ -576,23 +566,6 @@ int mips32_cp0_read(struct mips_ejtag *ejtag_info, uint32_t *val, uint32_t cp0_r
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exit:
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pracc_queue_free(&ctx);
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return ctx.retval;
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/**
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* Note that our input parametes cp0_reg and cp0_sel
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* are numbers (not gprs) which make part of mfc0 instruction opcode.
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*
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* These are not fix, but can be different for each mips32_cp0_read() function call,
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* and that is why we must insert them directly into opcode,
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* i.e. we can not pass it on EJTAG microprogram stack (via param_in),
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* and put them into the gprs later from MIPS32_PRACC_STACK
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* because mfc0 do not use gpr as a parameter for the cp0_reg and select part,
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* but plain (immediate) number.
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*
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* MIPS32_MTC0 is implemented via MIPS32_R_INST macro.
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* In order to insert our parameters, we must change rd and funct fields.
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*
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* code[2] |= (cp0_reg << 11) | cp0_sel; change rd and funct of MIPS32_R_INST macro
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**/
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}
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int mips32_cp0_write(struct mips_ejtag *ejtag_info, uint32_t val, uint32_t cp0_reg, uint32_t cp0_sel)
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@ -602,24 +575,18 @@ int mips32_cp0_write(struct mips_ejtag *ejtag_info, uint32_t val, uint32_t cp0_r
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if (ctx.retval != ERROR_OK)
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goto exit;
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pracc_add(&ctx, 0, MIPS32_LUI(15, UPPER16(val))); /* Load val to $15 */
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pracc_add(&ctx, 0, MIPS32_LUI(15, UPPER16(val))); /* Load val to $15 */
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pracc_add(&ctx, 0, MIPS32_ORI(15, 15, LOWER16(val)));
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pracc_add(&ctx, 0, MIPS32_MTC0(15, 0, 0) | (cp0_reg << 11) | cp0_sel); /* write cp0 reg / sel */
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pracc_add(&ctx, 0, MIPS32_MTC0(15, cp0_reg, cp0_sel)); /* write $15 to cp0 reg / sel */
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pracc_add(&ctx, 0, MIPS32_B(NEG16(ctx.code_count + 1))); /* jump to start */
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pracc_add(&ctx, 0, MIPS32_MFC0(15, 31, 0)); /* move COP0 DeSave to $15 */
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pracc_add(&ctx, 0, MIPS32_B(NEG16(ctx.code_count + 1))); /* jump to start */
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pracc_add(&ctx, 0, MIPS32_MFC0(15, 31, 0)); /* restore $15 from DeSave */
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ctx.retval = mips32_pracc_queue_exec(ejtag_info, &ctx, NULL);
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exit:
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pracc_queue_free(&ctx);
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return ctx.retval;
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/**
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* Note that MIPS32_MTC0 macro is implemented via MIPS32_R_INST macro.
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* In order to insert our parameters, we must change rd and funct fields.
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* code[3] |= (cp0_reg << 11) | cp0_sel; change rd and funct fields of MIPS32_R_INST macro
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**/
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}
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/**
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@ -956,9 +923,6 @@ int mips32_pracc_read_regs(struct mips_ejtag *ejtag_info, uint32_t *regs)
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pracc_add(&ctx, 0, MIPS32_B(NEG16(ctx.code_count + 1))); /* jump to start */
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pracc_add(&ctx, 0, MIPS32_MTC0(15, 31, 0)); /* load $15 in DeSave */
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if (ejtag_info->mode == 0)
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ctx.store_count++; /* Needed by legacy code, due to offset from reg0 */
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ctx.retval = mips32_pracc_queue_exec(ejtag_info, &ctx, regs);
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ejtag_info->reg8 = regs[8]; /* reg8 is saved but not restored, next called function should restore it */
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@ -1015,7 +979,7 @@ int mips32_pracc_fastdata_xfer(struct mips_ejtag *ejtag_info, struct working_are
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};
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int retval, i;
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uint32_t val, ejtag_ctrl, address;
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uint32_t val, ejtag_ctrl;
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if (source->size < MIPS32_FASTDATA_HANDLER_SIZE)
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return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
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@ -1054,19 +1018,13 @@ int mips32_pracc_fastdata_xfer(struct mips_ejtag *ejtag_info, struct working_are
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mips_ejtag_drscan_32_out(ejtag_info, ejtag_ctrl);
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}
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/* wait PrAcc pending bit for FASTDATA write */
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retval = wait_for_pracc_rw(ejtag_info, &ejtag_ctrl);
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/* wait PrAcc pending bit for FASTDATA write, read address */
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retval = mips32_pracc_read_ctrl_addr(ejtag_info);
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if (retval != ERROR_OK)
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return retval;
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/* next fetch to dmseg should be in FASTDATA_AREA, check */
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address = 0;
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mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS);
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retval = mips_ejtag_drscan_32(ejtag_info, &address);
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if (retval != ERROR_OK)
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return retval;
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if (address != MIPS32_PRACC_FASTDATA_AREA)
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if (ejtag_info->pa_addr != MIPS32_PRACC_FASTDATA_AREA)
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return ERROR_FAIL;
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/* Send the load start address */
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@ -1100,17 +1058,11 @@ int mips32_pracc_fastdata_xfer(struct mips_ejtag *ejtag_info, struct working_are
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return retval;
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}
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retval = wait_for_pracc_rw(ejtag_info, &ejtag_ctrl);
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retval = mips32_pracc_read_ctrl_addr(ejtag_info);
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if (retval != ERROR_OK)
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return retval;
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address = 0;
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mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS);
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retval = mips_ejtag_drscan_32(ejtag_info, &address);
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if (retval != ERROR_OK)
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return retval;
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if (address != MIPS32_PRACC_TEXT)
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if (ejtag_info->pa_addr != MIPS32_PRACC_TEXT)
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LOG_ERROR("mini program did not return to start");
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return retval;
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