flash/nor, contrib/loaders: add stm32 loaders Makefile and generated .inc
Flash loaders refactored to the new style - use generated .inc instead of hexadecimal machine code in the flash driver source. Change-Id: If65a2099589e210f9450819b467d67819fd841fc Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/4439 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>riscv-compliance-dev^2
Tomas Vanek
Tim Newsome
parent
ef88d58b7c
commit
0861923cdc
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@ -0,0 +1,28 @@
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BIN2C = ../../../../src/helper/bin2char.sh
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CROSS_COMPILE ?= arm-none-eabi-
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CC=$(CROSS_COMPILE)gcc
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OBJCOPY=$(CROSS_COMPILE)objcopy
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OBJDUMP=$(CROSS_COMPILE)objdump
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CFLAGS = -static -nostartfiles -mlittle-endian -Wa,-EL
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all: stm32f1x.inc stm32f2x.inc stm32h7x.inc stm32l4x.inc stm32lx.inc
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.PHONY: clean
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%.elf: %.S
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$(CC) $(CFLAGS) $< -o $@
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%.lst: %.elf
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$(OBJDUMP) -S $< > $@
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%.bin: %.elf
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$(OBJCOPY) -Obinary $< $@
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%.inc: %.bin
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$(BIN2C) < $< > $@
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clean:
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-rm -f *.elf *.lst *.bin *.inc
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@ -22,8 +22,6 @@
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.syntax unified
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.cpu cortex-m0
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.thumb
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.thumb_func
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.global write
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/* Params:
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* r0 - flash base (in), status (out)
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@ -39,6 +37,9 @@
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#define STM32_FLASH_SR_OFFSET 0x0c /* offset of SR register from flash reg base */
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.thumb_func
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.global _start
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_start:
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wait_fifo:
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ldr r6, [r2, #0] /* read wp */
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cmp r6, #0 /* abort if wp == 0 */
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@ -0,0 +1,5 @@
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/* Autogenerated with ../../../../src/helper/bin2char.sh */
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0x16,0x68,0x00,0x2e,0x18,0xd0,0x55,0x68,0xb5,0x42,0xf9,0xd0,0x2e,0x88,0x26,0x80,
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0x02,0x35,0x02,0x34,0xc6,0x68,0x01,0x27,0x3e,0x42,0xfb,0xd1,0x14,0x27,0x3e,0x42,
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0x08,0xd1,0x9d,0x42,0x01,0xd3,0x15,0x46,0x08,0x35,0x55,0x60,0x01,0x39,0x00,0x29,
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0x02,0xd0,0xe5,0xe7,0x00,0x20,0x50,0x60,0x30,0x46,0x00,0xbe,
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@ -25,7 +25,6 @@
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.syntax unified
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.cpu cortex-m3
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.thumb
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.thumb_func
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/*
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* Params :
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@ -44,6 +43,11 @@
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#define STM32_FLASH_CR_OFFSET 0x10 /* offset of CR register in FLASH struct */
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#define STM32_FLASH_SR_OFFSET 0x0c /* offset of SR register in FLASH struct */
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#define STM32_PROG16 0x101 /* PG | PSIZE_16*/
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.thumb_func
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.global _start
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_start:
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wait_fifo:
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ldr r8, [r0, #0] /* read wp */
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cmp r8, #0 /* abort if wp == 0 */
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@ -52,7 +56,7 @@ wait_fifo:
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cmp r7, r8 /* wait until rp != wp */
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beq wait_fifo
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ldr r6, STM32_PROG16
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ldr r6, =STM32_PROG16
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str r6, [r4, #STM32_FLASH_CR_OFFSET]
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ldrh r6, [r7], #0x02 /* read one half-word from src, increment ptr */
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strh r6, [r2], #0x02 /* write one half-word from src, increment ptr */
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@ -78,4 +82,4 @@ exit:
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mov r0, r6 /* return status in r0 */
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bkpt #0x00
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STM32_PROG16: .word 0x101 /* PG | PSIZE_16*/
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.pool
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@ -0,0 +1,6 @@
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/* Autogenerated with ../../../../src/helper/bin2char.sh */
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0xd0,0xf8,0x00,0x80,0xb8,0xf1,0x00,0x0f,0x1b,0xd0,0x47,0x68,0x47,0x45,0xf7,0xd0,
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0x0d,0x4e,0x26,0x61,0x37,0xf8,0x02,0x6b,0x22,0xf8,0x02,0x6b,0xbf,0xf3,0x4f,0x8f,
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0xe6,0x68,0x16,0xf4,0x80,0x3f,0xfb,0xd1,0x16,0xf0,0xf0,0x0f,0x07,0xd1,0x8f,0x42,
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0x28,0xbf,0x00,0xf1,0x08,0x07,0x47,0x60,0x01,0x3b,0x13,0xb1,0xe0,0xe7,0x00,0x21,
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0x41,0x60,0x30,0x46,0x00,0xbe,0x00,0x00,0x01,0x01,0x00,0x00,
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@ -20,21 +20,6 @@
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.syntax unified
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.cpu cortex-m7
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.thumb
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.thumb_func
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/*
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* To assemble:
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* arm-none-eabi-gcc -c stm32h7x.S
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*
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* To disassemble:
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* arm-none-eabi-objdump -d stm32h7x.o
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*
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* To generate binary file:
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* arm-none-eabi-objcopy -O binary stm32h7x.o stm32h7_flash_write_code.bin
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*
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* To generate include file:
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* xxd -i stm32h7_flash_write_code.bin
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*/
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/*
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* Code limitations:
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@ -67,7 +52,9 @@
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#define STM32_SR_ERROR_MASK 0x03ee0000 /* DBECCERR | SNECCERR | RDSERR | RDPERR | OPERR
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| INCERR | STRBERR | PGSERR | WRPERR */
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code:
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.thumb_func
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.global _start
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_start:
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ldr r5, [r0, #4] /* read rp */
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wait_fifo:
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@ -100,7 +87,7 @@ busy:
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tst r6, #STM32_SR_BUSY_MASK
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bne busy /* operation in progress, wait ... */
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ldr r7, stm32_sr_error_mask
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ldr r7, =STM32_SR_ERROR_MASK
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tst r6, r7
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bne error /* fail... */
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@ -117,5 +104,5 @@ exit:
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mov r0, r6 /* return status in r0 */
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bkpt #0x00
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stm32_sr_error_mask:
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.word STM32_SR_ERROR_MASK
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.pool
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@ -0,0 +1,7 @@
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/* Autogenerated with ../../../../src/helper/bin2char.sh */
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0x45,0x68,0x06,0x68,0x26,0xb3,0x76,0x1b,0x42,0xbf,0x76,0x18,0x36,0x1a,0x08,0x3e,
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0x20,0x2e,0xf6,0xd3,0x4f,0xf0,0x32,0x06,0xe6,0x60,0x4f,0xf0,0x08,0x07,0x55,0xf8,
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0x04,0x6b,0x42,0xf8,0x04,0x6b,0xbf,0xf3,0x4f,0x8f,0x8d,0x42,0x28,0xbf,0x00,0xf1,
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0x08,0x05,0x01,0x3f,0xf3,0xd1,0x26,0x69,0x16,0xf0,0x01,0x0f,0xfb,0xd1,0x05,0x4f,
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0x3e,0x42,0x03,0xd1,0x45,0x60,0x01,0x3b,0xdb,0xd1,0x01,0xe0,0x00,0x27,0x47,0x60,
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0x30,0x46,0x00,0xbe,0x00,0x00,0xee,0x03,
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@ -27,20 +27,6 @@
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.syntax unified
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.cpu cortex-m4
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.thumb
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.thumb_func
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/* To assemble:
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* arm-none-eabi-gcc -c stm32l4x.S
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*
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* To disassemble:
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* arm-none-eabi-objdump -o stm32l4x.o
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*
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* To generate binary file:
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* arm-none-eabi-objcopy -O binary stm32l4x.o stm32l4_flash_write_code.bin
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*
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* To generate include file:
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* xxd -i stm32l4_flash_write_code.bin
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*/
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/*
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* Params :
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@ -59,6 +45,11 @@
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#define STM32_FLASH_CR_OFFSET 0x14 /* offset of CR register in FLASH struct */
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#define STM32_FLASH_SR_OFFSET 0x10 /* offset of SR register in FLASH struct */
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#define STM32_PROG 0x1 /* PG */
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.thumb_func
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.global _start
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_start:
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wait_fifo:
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ldr r8, [r0, #0] /* read wp */
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cmp r8, #0 /* abort if wp == 0 */
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@ -71,7 +62,7 @@ wait_fifo:
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cmp r6, #8 /* wait until 8 bytes are available */
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bcc wait_fifo
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ldr r6, STM32_PROG
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ldr r6, =STM32_PROG
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str r6, [r4, #STM32_FLASH_CR_OFFSET]
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ldrd r6, [r5], #0x08 /* read one word from src, increment ptr */
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strd r6, [r2], #0x08 /* write one word to dst, increment ptr */
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@ -97,4 +88,5 @@ exit:
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mov r0, r6 /* return status in r0 */
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bkpt #0x00
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STM32_PROG: .word 0x1 /* PG */
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.pool
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@ -0,0 +1,7 @@
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/* Autogenerated with ../../../../src/helper/bin2char.sh */
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0xd0,0xf8,0x00,0x80,0xb8,0xf1,0x00,0x0f,0x20,0xd0,0x45,0x68,0xb8,0xeb,0x05,0x06,
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0x44,0xbf,0x76,0x18,0x36,0x1a,0x08,0x2e,0xf2,0xd3,0x0d,0x4e,0x66,0x61,0xf5,0xe8,
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0x02,0x67,0xe2,0xe8,0x02,0x67,0xbf,0xf3,0x4f,0x8f,0x26,0x69,0x16,0xf4,0x80,0x3f,
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0xfb,0xd1,0x16,0xf0,0xfa,0x0f,0x07,0xd1,0x8d,0x42,0x28,0xbf,0x00,0xf1,0x08,0x05,
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0x45,0x60,0x01,0x3b,0x13,0xb1,0xdb,0xe7,0x00,0x21,0x41,0x60,0x30,0x46,0x00,0xbe,
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0x01,0x00,0x00,0x00,
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@ -28,13 +28,10 @@
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***************************************************************************/
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// Build : arm-eabi-gcc -c stm32lx.S
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.text
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.syntax unified
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.cpu cortex-m0
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.thumb
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.thumb_func
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.global write
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/*
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r0 - destination address
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@ -42,6 +39,9 @@
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r2 - count
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*/
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.thumb_func
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.global _start
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_start:
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// r2 = source + count * 4
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lsls r2, r2, #2
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adds r2, r1, r2
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@ -0,0 +1,2 @@
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/* Autogenerated with ../../../../src/helper/bin2char.sh */
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0x92,0x00,0x8a,0x18,0x01,0xe0,0x08,0xc9,0x08,0xc0,0x91,0x42,0xfb,0xd1,0x00,0xbe,
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@ -572,45 +572,8 @@ static int stm32x_write_block(struct flash_bank *bank, const uint8_t *buffer,
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struct armv7m_algorithm armv7m_info;
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int retval = ERROR_OK;
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/* see contrib/loaders/flash/stm32f1x.S for src */
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static const uint8_t stm32x_flash_write_code[] = {
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/* #define STM32_FLASH_SR_OFFSET 0x0C */
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/* wait_fifo: */
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0x16, 0x68, /* ldr r6, [r2, #0] */
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0x00, 0x2e, /* cmp r6, #0 */
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0x18, 0xd0, /* beq exit */
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0x55, 0x68, /* ldr r5, [r2, #4] */
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0xb5, 0x42, /* cmp r5, r6 */
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0xf9, 0xd0, /* beq wait_fifo */
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0x2e, 0x88, /* ldrh r6, [r5, #0] */
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0x26, 0x80, /* strh r6, [r4, #0] */
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0x02, 0x35, /* adds r5, #2 */
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0x02, 0x34, /* adds r4, #2 */
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/* busy: */
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0xc6, 0x68, /* ldr r6, [r0, #STM32_FLASH_SR_OFFSET] */
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0x01, 0x27, /* movs r7, #1 */
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0x3e, 0x42, /* tst r6, r7 */
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0xfb, 0xd1, /* bne busy */
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0x14, 0x27, /* movs r7, #0x14 */
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0x3e, 0x42, /* tst r6, r7 */
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0x08, 0xd1, /* bne error */
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0x9d, 0x42, /* cmp r5, r3 */
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0x01, 0xd3, /* bcc no_wrap */
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0x15, 0x46, /* mov r5, r2 */
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0x08, 0x35, /* adds r5, #8 */
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/* no_wrap: */
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0x55, 0x60, /* str r5, [r2, #4] */
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0x01, 0x39, /* subs r1, r1, #1 */
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0x00, 0x29, /* cmp r1, #0 */
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0x02, 0xd0, /* beq exit */
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0xe5, 0xe7, /* b wait_fifo */
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/* error: */
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0x00, 0x20, /* movs r0, #0 */
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0x50, 0x60, /* str r0, [r2, #4] */
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/* exit: */
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0x30, 0x46, /* mov r0, r6 */
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0x00, 0xbe, /* bkpt #0 */
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#include "../../../contrib/loaders/flash/stm32/stm32f1x.inc"
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};
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/* flash write code */
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@ -584,45 +584,8 @@ static int stm32x_write_block(struct flash_bank *bank, const uint8_t *buffer,
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struct armv7m_algorithm armv7m_info;
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int retval = ERROR_OK;
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/* see contrib/loaders/flash/stm32f2x.S for src */
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static const uint8_t stm32x_flash_write_code[] = {
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/* wait_fifo: */
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0xD0, 0xF8, 0x00, 0x80, /* ldr r8, [r0, #0] */
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0xB8, 0xF1, 0x00, 0x0F, /* cmp r8, #0 */
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0x1A, 0xD0, /* beq exit */
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0x47, 0x68, /* ldr r7, [r0, #4] */
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0x47, 0x45, /* cmp r7, r8 */
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0xF7, 0xD0, /* beq wait_fifo */
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0xDF, 0xF8, 0x34, 0x60, /* ldr r6, STM32_PROG16 */
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0x26, 0x61, /* str r6, [r4, #STM32_FLASH_CR_OFFSET] */
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0x37, 0xF8, 0x02, 0x6B, /* ldrh r6, [r7], #0x02 */
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0x22, 0xF8, 0x02, 0x6B, /* strh r6, [r2], #0x02 */
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0xBF, 0xF3, 0x4F, 0x8F, /* dsb sy */
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/* busy: */
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0xE6, 0x68, /* ldr r6, [r4, #STM32_FLASH_SR_OFFSET] */
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0x16, 0xF4, 0x80, 0x3F, /* tst r6, #0x10000 */
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0xFB, 0xD1, /* bne busy */
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0x16, 0xF0, 0xF0, 0x0F, /* tst r6, #0xf0 */
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0x07, 0xD1, /* bne error */
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0x8F, 0x42, /* cmp r7, r1 */
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0x28, 0xBF, /* it cs */
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0x00, 0xF1, 0x08, 0x07, /* addcs r7, r0, #8 */
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0x47, 0x60, /* str r7, [r0, #4] */
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0x01, 0x3B, /* subs r3, r3, #1 */
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0x13, 0xB1, /* cbz r3, exit */
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0xDF, 0xE7, /* b wait_fifo */
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/* error: */
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0x00, 0x21, /* movs r1, #0 */
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0x41, 0x60, /* str r1, [r0, #4] */
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/* exit: */
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0x30, 0x46, /* mov r0, r6 */
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0x00, 0xBE, /* bkpt #0x00 */
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/* <STM32_PROG16>: */
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0x01, 0x01, 0x00, 0x00, /* .word 0x00000101 */
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#include "../../../contrib/loaders/flash/stm32/stm32f2x.inc"
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};
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if (target_alloc_working_area(target, sizeof(stm32x_flash_write_code),
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@ -568,51 +568,8 @@ static int stm32x_write_block(struct flash_bank *bank, const uint8_t *buffer,
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struct stm32h7x_flash_bank *stm32x_info = bank->driver_priv;
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int retval = ERROR_OK;
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/* see contrib/loaders/flash/smt32h7x.S for src */
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static const uint8_t stm32x_flash_write_code[] = {
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/* <code>: */
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0x45, 0x68, /* ldr r5, [r0, #4] */
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/* <wait_fifo>: */
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0x06, 0x68, /* ldr r6, [r0, #0] */
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0x26, 0xb3, /* cbz r6, <exit> */
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0x76, 0x1b, /* subs r6, r6, r5 */
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0x42, 0xbf, /* ittt mi */
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0x76, 0x18, /* addmi r6, r6, r1 */
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0x36, 0x1a, /* submi r6, r6, r0 */
|
||||
0x08, 0x3e, /* submi r6, #8 */
|
||||
0x20, 0x2e, /* cmp r6, #32 */
|
||||
0xf6, 0xd3, /* bcc.n <wait_fifo> */
|
||||
0x4f, 0xf0, 0x32, 0x06, /* mov.w r6, #STM32_PROG */
|
||||
0xe6, 0x60, /* str r6, [r4, #STM32_FLASH_CR_OFFSET] */
|
||||
0x4f, 0xf0, 0x08, 0x07, /* mov.w r7, #8 */
|
||||
/* <write_flash>: */
|
||||
0x55, 0xf8, 0x04, 0x6b, /* ldr.w r6, [r5], #4 */
|
||||
0x42, 0xf8, 0x04, 0x6b, /* str.w r6, [r2], #4 */
|
||||
0xbf, 0xf3, 0x4f, 0x8f, /* dsb sy */
|
||||
0x8d, 0x42, /* cmp r5, r1 */
|
||||
0x28, 0xbf, /* it cs */
|
||||
0x00, 0xf1, 0x08, 0x05, /* addcs.w r5, r0, #8 */
|
||||
0x01, 0x3f, /* subs r7, #1 */
|
||||
0xf3, 0xd1, /* bne.n <write_flash> */
|
||||
/* <busy>: */
|
||||
0x26, 0x69, /* ldr r6, [r4, #STM32_FLASH_SR_OFFSET] */
|
||||
0x16, 0xf0, 0x01, 0x0f, /* tst.w r6, #STM32_SR_BUSY_MASK */
|
||||
0xfb, 0xd1, /* bne.n <busy> */
|
||||
0x05, 0x4f, /* ldr r7, [pc, #20] ; (<stm32_sr_error_mask>) */
|
||||
0x3e, 0x42, /* tst r6, r7 */
|
||||
0x03, 0xd1, /* bne.n <error> */
|
||||
0x45, 0x60, /* str r5, [r0, #4] */
|
||||
0x01, 0x3b, /* subs r3, #1 */
|
||||
0xdb, 0xd1, /* bne.n <wait_fifo> */
|
||||
0x01, 0xe0, /* b.n <exit> */
|
||||
/* <error>: */
|
||||
0x00, 0x27, /* movs r7, #0 */
|
||||
0x47, 0x60, /* str r7, [r0, #4] */
|
||||
/* <exit>: */
|
||||
0x30, 0x46, /* mov r0, r6 */
|
||||
0x00, 0xbe, /* bkpt 0x0000 */
|
||||
/* <stm32_sr_error_mask>: */
|
||||
0x00, 0x00, 0xee, 0x03 /* .word 0x03ee0000 ; (STM32_SR_ERROR_MASK) */
|
||||
#include "../../../contrib/loaders/flash/stm32/stm32h7x.inc"
|
||||
};
|
||||
|
||||
if (target_alloc_working_area(target, sizeof(stm32x_flash_write_code),
|
||||
|
|
|
|||
|
|
@ -461,19 +461,8 @@ static int stm32l4_write_block(struct flash_bank *bank, const uint8_t *buffer,
|
|||
struct armv7m_algorithm armv7m_info;
|
||||
int retval = ERROR_OK;
|
||||
|
||||
/* See contrib/loaders/flash/stm32l4x.S for source and
|
||||
* hints how to generate the data!
|
||||
*/
|
||||
|
||||
static const uint8_t stm32l4_flash_write_code[] = {
|
||||
0xd0, 0xf8, 0x00, 0x80, 0xb8, 0xf1, 0x00, 0x0f, 0x21, 0xd0, 0x45, 0x68,
|
||||
0xb8, 0xeb, 0x05, 0x06, 0x44, 0xbf, 0x76, 0x18, 0x36, 0x1a, 0x08, 0x2e,
|
||||
0xf2, 0xd3, 0xdf, 0xf8, 0x36, 0x60, 0x66, 0x61, 0xf5, 0xe8, 0x02, 0x67,
|
||||
0xe2, 0xe8, 0x02, 0x67, 0xbf, 0xf3, 0x4f, 0x8f, 0x26, 0x69, 0x16, 0xf4,
|
||||
0x80, 0x3f, 0xfb, 0xd1, 0x16, 0xf0, 0xfa, 0x0f, 0x07, 0xd1, 0x8d, 0x42,
|
||||
0x28, 0xbf, 0x00, 0xf1, 0x08, 0x05, 0x45, 0x60, 0x01, 0x3b, 0x13, 0xb1,
|
||||
0xda, 0xe7, 0x00, 0x21, 0x41, 0x60, 0x30, 0x46, 0x00, 0xbe, 0x01, 0x00,
|
||||
0x00, 0x00
|
||||
#include "../../../contrib/loaders/flash/stm32/stm32l4x.inc"
|
||||
};
|
||||
|
||||
if (target_alloc_working_area(target, sizeof(stm32l4_flash_write_code),
|
||||
|
|
|
|||
|
|
@ -448,10 +448,8 @@ static int stm32lx_write_half_pages(struct flash_bank *bank, const uint8_t *buff
|
|||
|
||||
int retval = ERROR_OK;
|
||||
|
||||
/* see contib/loaders/flash/stm32lx.S for src */
|
||||
|
||||
static const uint8_t stm32lx_flash_write_code[] = {
|
||||
0x92, 0x00, 0x8A, 0x18, 0x01, 0xE0, 0x08, 0xC9, 0x08, 0xC0, 0x91, 0x42, 0xFB, 0xD1, 0x00, 0xBE
|
||||
#include "../../../contrib/loaders/flash/stm32/stm32lx.inc"
|
||||
};
|
||||
|
||||
/* Make sure we're performing a half-page aligned write. */
|
||||
|
|
|
|||
Loading…
Reference in New Issue