Support v0 system bus access
This code was submitted at https://github.com/riscv/riscv-openocd/pull/214. This change incorporates that code, makes it build, and fixes the style to fit the OpenOCD style guide. I have not tested the new code because I don't have a target. It does not cause any regressions. Change-Id: Ic3639d822c887bd4a5517f044855fdd9d4e5a46dsba_tests
Tim Newsome
parent
fd9de02fac
commit
075610d495
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@ -1758,10 +1758,80 @@ static int read_sbcs_nonbusy(struct target *target, uint32_t *sbcs)
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}
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}
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static int read_memory_bus_v0(struct target *target, target_addr_t address,
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uint32_t size, uint32_t count, uint8_t *buffer)
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{
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LOG_DEBUG("System Bus Access: size: %d\tcount:%d\tstart address: 0x%08"
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TARGET_PRIxADDR, size, count, address);
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uint8_t *t_buffer = buffer;
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riscv_addr_t cur_addr = address;
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riscv_addr_t fin_addr = address + (count * size);
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uint64_t access = 0;
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const int DMI_SBCS_SBSINGLEREAD_OFFSET = 20;
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const uint32_t DMI_SBCS_SBSINGLEREAD = (0x1U << DMI_SBCS_SBSINGLEREAD_OFFSET);
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const int DMI_SBCS_SBAUTOREAD_OFFSET = 15;
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const uint32_t DMI_SBCS_SBAUTOREAD = (0x1U << DMI_SBCS_SBAUTOREAD_OFFSET);
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/* ww favorise one off reading if there is an issu */
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if (count == 1) {
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for (uint32_t i = 0; i < count; i++) {
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access = dmi_read(target, DMI_SBCS);
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dmi_write(target, DMI_SBADDRESS0, cur_addr);
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/* size/2 matching the bit access of the spec 0.13 */
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access = set_field(access, DMI_SBCS_SBACCESS, size/2);
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access = set_field(access, DMI_SBCS_SBSINGLEREAD, 1);
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LOG_DEBUG("\r\nread_memory: sab: access: 0x%08" PRIx64, access);
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dmi_write(target, DMI_SBCS, access);
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/* 3) read */
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uint32_t value = dmi_read(target, DMI_SBDATA0);
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LOG_DEBUG("\r\nread_memory: sab: value: 0x%08x", value);
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write_to_buf(t_buffer, value, size);
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t_buffer += size;
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cur_addr += size;
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}
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return ERROR_OK;
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}
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/* has to be the same size if we want to read a block */
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LOG_DEBUG("reading block until final address 0x%" PRIx64, fin_addr);
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access = dmi_read(target, DMI_SBCS);
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/* set current address */
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dmi_write(target, DMI_SBADDRESS0, cur_addr);
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/* 2) write sbaccess=2, sbsingleread,sbautoread,sbautoincrement
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* size/2 matching the bit access of the spec 0.13 */
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access = set_field(access, DMI_SBCS_SBACCESS, size/2);
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access = set_field(access, DMI_SBCS_SBAUTOREAD, 1);
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access = set_field(access, DMI_SBCS_SBSINGLEREAD, 1);
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access = set_field(access, DMI_SBCS_SBAUTOINCREMENT, 1);
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LOG_DEBUG("\r\naccess: 0x%08" PRIx64, access);
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dmi_write(target, DMI_SBCS, access);
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while (cur_addr < fin_addr) {
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LOG_DEBUG("\r\nsab:autoincrement: \r\n size: %d\tcount:%d\taddress: 0x%08"
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PRIx64, size, count, cur_addr);
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/* read */
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uint32_t value = dmi_read(target, DMI_SBDATA0);
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write_to_buf(t_buffer, value, size);
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cur_addr += size;
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t_buffer += size;
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/* if we are reaching last address, we must clear autoread */
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if (cur_addr == fin_addr && count != 1) {
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dmi_write(target, DMI_SBCS, 0);
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value = dmi_read(target, DMI_SBDATA0);
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write_to_buf(t_buffer, value, size);
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}
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}
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return ERROR_OK;
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}
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/**
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* Read the requested memory using the system bus interface.
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*/
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static int read_memory_bus(struct target *target, target_addr_t address,
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static int read_memory_bus_v1(struct target *target, target_addr_t address,
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uint32_t size, uint32_t count, uint8_t *buffer)
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{
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RISCV013_INFO(info);
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@ -2065,22 +2135,113 @@ static int read_memory(struct target *target, target_addr_t address,
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uint32_t size, uint32_t count, uint8_t *buffer)
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{
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RISCV013_INFO(info);
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if (info->progbufsize >= 2) {
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if (info->progbufsize >= 2)
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return read_memory_progbuf(target, address, size, count, buffer);
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} else if ((get_field(info->sbcs, DMI_SBCS_SBVERSION) == 1) && (
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(get_field(info->sbcs, DMI_SBCS_SBACCESS8) && size == 1) ||
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if ((get_field(info->sbcs, DMI_SBCS_SBACCESS8) && size == 1) ||
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(get_field(info->sbcs, DMI_SBCS_SBACCESS16) && size == 2) ||
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(get_field(info->sbcs, DMI_SBCS_SBACCESS32) && size == 4) ||
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(get_field(info->sbcs, DMI_SBCS_SBACCESS64) && size == 8) ||
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(get_field(info->sbcs, DMI_SBCS_SBACCESS128) && size == 16))) {
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return read_memory_bus(target, address, size, count, buffer);
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} else {
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(get_field(info->sbcs, DMI_SBCS_SBACCESS128) && size == 16)) {
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if (get_field(info->sbcs, DMI_SBCS_SBVERSION) == 0)
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return read_memory_bus_v0(target, address, size, count, buffer);
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else if (get_field(info->sbcs, DMI_SBCS_SBVERSION) == 1)
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return read_memory_bus_v1(target, address, size, count, buffer);
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}
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LOG_ERROR("Don't know how to read memory on this target.");
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return ERROR_FAIL;
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}
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static int write_memory_bus_v0(struct target *target, target_addr_t address,
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uint32_t size, uint32_t count, const uint8_t *buffer)
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{
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/*1) write sbaddress: for singlewrite and autoincrement, we need to write the address once*/
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LOG_DEBUG("System Bus Access: size: %d\tcount:%d\tstart address: 0x%08"
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PRIx64, size, count, address);
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dmi_write(target, DMI_SBADDRESS0, address);
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int64_t value = 0;
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int64_t access = 0;
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riscv_addr_t offset = 0;
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riscv_addr_t t_addr = 0;
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const uint8_t *t_buffer = buffer + offset;
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/* B.8 Writing Memory, single write check if we write in one go */
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if (count == 1) { /* count is in bytes here */
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/* check the size */
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switch (size) {
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case 1:
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value = t_buffer[0];
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break;
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case 2:
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value = t_buffer[0]
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| ((uint32_t) t_buffer[1] << 8);
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break;
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case 4:
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value = t_buffer[0]
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| ((uint32_t) t_buffer[1] << 8)
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| ((uint32_t) t_buffer[2] << 16)
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| ((uint32_t) t_buffer[3] << 24);
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break;
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default:
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LOG_ERROR("unsupported access size: %d", size);
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return ERROR_FAIL;
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}
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static int write_memory_bus(struct target *target, target_addr_t address,
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access = 0;
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access = set_field(access, DMI_SBCS_SBACCESS, size/2);
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dmi_write(target, DMI_SBCS, access);
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LOG_DEBUG("\r\naccess: 0x%08" PRIx64, access);
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LOG_DEBUG("\r\nwrite_memory:SAB: ONE OFF: value 0x%08" PRIx64, value);
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dmi_write(target, DMI_SBDATA0, value);
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return ERROR_OK;
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}
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/*B.8 Writing Memory, using autoincrement*/
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access = 0;
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access = set_field(access, DMI_SBCS_SBACCESS, size/2);
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access = set_field(access, DMI_SBCS_SBAUTOINCREMENT, 1);
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LOG_DEBUG("\r\naccess: 0x%08" PRIx64, access);
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dmi_write(target, DMI_SBCS, access);
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/*2)set the value according to the size required and write*/
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for (riscv_addr_t i = 0; i < count; ++i) {
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offset = size*i;
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/* for monitoring only */
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t_addr = address + offset;
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t_buffer = buffer + offset;
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switch (size) {
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case 1:
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value = t_buffer[0];
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break;
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case 2:
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value = t_buffer[0]
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| ((uint32_t) t_buffer[1] << 8);
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break;
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case 4:
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value = t_buffer[0]
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| ((uint32_t) t_buffer[1] << 8)
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| ((uint32_t) t_buffer[2] << 16)
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| ((uint32_t) t_buffer[3] << 24);
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break;
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default:
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LOG_ERROR("unsupported access size: %d", size);
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return ERROR_FAIL;
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}
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LOG_DEBUG("SAB:autoincrement: expected address: 0x%08x value: 0x%08x"
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PRIx64, (uint32_t)t_addr, (uint32_t)value);
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dmi_write(target, DMI_SBDATA0, value);
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}
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/*reset the autoincrement when finished (something weird is happening if this is not done at the end*/
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access = set_field(access, DMI_SBCS_SBAUTOINCREMENT, 0);
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dmi_write(target, DMI_SBCS, access);
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return ERROR_OK;
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}
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static int write_memory_bus_v1(struct target *target, target_addr_t address,
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uint32_t size, uint32_t count, const uint8_t *buffer)
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{
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RISCV013_INFO(info);
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@ -2338,20 +2499,22 @@ static int write_memory(struct target *target, target_addr_t address,
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uint32_t size, uint32_t count, const uint8_t *buffer)
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{
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RISCV013_INFO(info);
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if (info->progbufsize >= 2) {
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if (info->progbufsize >= 2)
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return write_memory_progbuf(target, address, size, count, buffer);
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} else if ((get_field(info->sbcs, DMI_SBCS_SBVERSION) == 1) && (
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(get_field(info->sbcs, DMI_SBCS_SBACCESS8) && size == 1) ||
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if ((get_field(info->sbcs, DMI_SBCS_SBACCESS8) && size == 1) ||
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(get_field(info->sbcs, DMI_SBCS_SBACCESS16) && size == 2) ||
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(get_field(info->sbcs, DMI_SBCS_SBACCESS32) && size == 4) ||
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(get_field(info->sbcs, DMI_SBCS_SBACCESS64) && size == 8) ||
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(get_field(info->sbcs, DMI_SBCS_SBACCESS128) && size == 16))) {
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return write_memory_bus(target, address, size, count, buffer);
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} else {
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(get_field(info->sbcs, DMI_SBCS_SBACCESS128) && size == 16)) {
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if (get_field(info->sbcs, DMI_SBCS_SBVERSION) == 0)
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return write_memory_bus_v0(target, address, size, count, buffer);
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else if (get_field(info->sbcs, DMI_SBCS_SBVERSION) == 1)
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return write_memory_bus_v1(target, address, size, count, buffer);
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}
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LOG_ERROR("Don't know how to write memory on this target.");
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return ERROR_FAIL;
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}
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}
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static int arch_state(struct target *target)
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{
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