psoc5lp: Add NV Latch flash driver
Erasing is not supported by the hardware, it can be written directly. Tested on CY8CKIT-059, except modifying-write. Change-Id: I6e920ed930dcd5c7f0b10c5b1b4791a828d9080a Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/3434 Tested-by: jenkinsriscv-compliance
Andreas Färber
Tomas Vanek
parent
53376dbbed
commit
06123153f3
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@ -6179,6 +6179,31 @@ flash bank $_CHIPNAME.eeprom psoc5lp_eeprom 0x40008000 0 0 0 $_TARGETNAME
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@end example
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@end deffn
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@deffn {Flash Driver} psoc5lp_nvl
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All members of the PSoC 5LP microcontroller family from Cypress
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include internal Nonvolatile Latches and use ARM Cortex-M3 cores.
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The driver probes for a number of these chips and autoconfigures itself.
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@example
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flash bank $_CHIPNAME.nvl psoc5lp_nvl 0 0 0 0 $_TARGETNAME
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@end example
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PSoC 5LP chips have multiple NV Latches:
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@itemize
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@item Device Configuration NV Latch - 4 bytes
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@item Write Once (WO) NV Latch - 4 bytes
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@end itemize
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@b{Note:} This driver only implements the Device Configuration NVL.
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The @var{psoc5lp} driver reads the ECC mode from Device Configuration NVL.
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@quotation Attention
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Switching ECC mode via write to Device Configuration NVL will require a reset
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after successful write.
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@end quotation
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@end deffn
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@deffn {Flash Driver} psoc6
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Supports PSoC6 (CY8C6xxx) family of Cypress microcontrollers.
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PSoC6 is a dual-core device with CM0+ and CM4 cores. Both cores share
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@ -58,6 +58,7 @@ extern struct flash_driver pic32mx_flash;
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extern struct flash_driver psoc4_flash;
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extern struct flash_driver psoc5lp_flash;
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extern struct flash_driver psoc5lp_eeprom_flash;
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extern struct flash_driver psoc5lp_nvl_flash;
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extern struct flash_driver psoc6_flash;
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extern struct flash_driver sim3x_flash;
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extern struct flash_driver stellaris_flash;
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@ -119,6 +120,7 @@ static struct flash_driver *flash_drivers[] = {
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&psoc4_flash,
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&psoc5lp_flash,
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&psoc5lp_eeprom_flash,
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&psoc5lp_nvl_flash,
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&psoc6_flash,
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&sim3x_flash,
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&stellaris_flash,
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@ -29,6 +29,7 @@
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#define PM_ACT_CFG12 0x400043AC
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#define SPC_CPU_DATA 0x40004720
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#define SPC_SR 0x40004722
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#define PRT1_PC2 0x4000500A
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#define PHUB_CH0_BASIC_CFG 0x40007010
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#define PHUB_CH0_ACTION 0x40007014
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#define PHUB_CH0_BASIC_STATUS 0x40007018
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@ -45,6 +46,11 @@
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#define PHUB_TDMEM1_ORIG_TD1 0x4000780C
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#define PANTHER_DEVICE_ID 0x4008001C
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/* NVL is not actually mapped to the Cortex-M address space
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* As we need a base addess different from other banks in the device
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* we use the address of NVL programming data in Cypress images */
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#define NVL_META_BASE 0x90000000
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#define PM_ACT_CFG12_EN_EE (1 << 4)
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#define SPC_KEY1 0xB6
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@ -359,6 +365,31 @@ static int psoc5lp_spc_busy_wait_idle(struct target *target)
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return ERROR_FLASH_OPERATION_FAILED;
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}
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static int psoc5lp_spc_load_byte(struct target *target,
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uint8_t array_id, uint8_t offset, uint8_t value)
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{
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int retval;
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retval = psoc5lp_spc_write_opcode(target, SPC_LOAD_BYTE);
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if (retval != ERROR_OK)
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return retval;
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retval = target_write_u8(target, SPC_CPU_DATA, array_id);
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if (retval != ERROR_OK)
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return retval;
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retval = target_write_u8(target, SPC_CPU_DATA, offset);
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if (retval != ERROR_OK)
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return retval;
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retval = target_write_u8(target, SPC_CPU_DATA, value);
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if (retval != ERROR_OK)
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return retval;
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retval = psoc5lp_spc_busy_wait_idle(target);
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if (retval != ERROR_OK)
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return retval;
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return ERROR_OK;
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}
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static int psoc5lp_spc_load_row(struct target *target,
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uint8_t array_id, const uint8_t *data, unsigned row_size)
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{
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@ -446,6 +477,25 @@ static int psoc5lp_spc_write_row(struct target *target,
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return ERROR_OK;
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}
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static int psoc5lp_spc_write_user_nvl(struct target *target,
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uint8_t array_id)
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{
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int retval;
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retval = psoc5lp_spc_write_opcode(target, SPC_WRITE_USER_NVL);
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if (retval != ERROR_OK)
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return retval;
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retval = target_write_u8(target, SPC_CPU_DATA, array_id);
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if (retval != ERROR_OK)
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return retval;
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retval = psoc5lp_spc_busy_wait_idle(target);
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if (retval != ERROR_OK)
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return retval;
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return ERROR_OK;
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}
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static int psoc5lp_spc_erase_sector(struct target *target,
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uint8_t array_id, uint8_t row_id)
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{
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@ -545,6 +595,272 @@ static int psoc5lp_spc_get_temp(struct target *target, uint8_t samples,
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return ERROR_OK;
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}
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static int psoc5lp_spc_read_volatile_byte(struct target *target,
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uint8_t array_id, uint8_t offset, uint8_t *data)
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{
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int retval;
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retval = psoc5lp_spc_write_opcode(target, SPC_READ_VOLATILE_BYTE);
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if (retval != ERROR_OK)
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return retval;
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retval = target_write_u8(target, SPC_CPU_DATA, array_id);
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if (retval != ERROR_OK)
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return retval;
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retval = target_write_u8(target, SPC_CPU_DATA, offset);
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if (retval != ERROR_OK)
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return retval;
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retval = psoc5lp_spc_busy_wait_data(target);
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if (retval != ERROR_OK)
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return retval;
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retval = target_read_u8(target, SPC_CPU_DATA, data);
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if (retval != ERROR_OK)
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return retval;
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retval = psoc5lp_spc_busy_wait_idle(target);
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if (retval != ERROR_OK)
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return retval;
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return ERROR_OK;
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}
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/*
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* NV Latch
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*/
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struct psoc5lp_nvl_flash_bank {
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bool probed;
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const struct psoc5lp_device *device;
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};
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static int psoc5lp_nvl_read(struct flash_bank *bank,
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uint8_t *buffer, uint32_t offset, uint32_t count)
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{
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int retval;
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retval = psoc5lp_spc_enable_clock(bank->target);
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if (retval != ERROR_OK)
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return retval;
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while (count > 0) {
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retval = psoc5lp_spc_read_byte(bank->target,
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SPC_ARRAY_NVL_USER, offset, buffer);
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if (retval != ERROR_OK)
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return retval;
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buffer++;
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offset++;
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count--;
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}
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return ERROR_OK;
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}
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static int psoc5lp_nvl_erase(struct flash_bank *bank, int first, int last)
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{
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LOG_WARNING("There is no erase operation for NV Latches");
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return ERROR_FLASH_OPER_UNSUPPORTED;
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}
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static int psoc5lp_nvl_erase_check(struct flash_bank *bank)
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{
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int i;
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for (i = 0; i < bank->num_sectors; i++)
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bank->sectors[i].is_erased = 0;
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return ERROR_OK;
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}
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static int psoc5lp_nvl_write(struct flash_bank *bank,
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const uint8_t *buffer, uint32_t offset, uint32_t byte_count)
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{
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struct target *target = bank->target;
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uint8_t *current_data, val;
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bool write_required = false, pullup_needed = false, ecc_changed = false;
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uint32_t i;
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int retval;
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if (offset != 0 || byte_count != bank->size) {
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LOG_ERROR("NVL can only be written in whole");
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return ERROR_FLASH_OPER_UNSUPPORTED;
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}
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current_data = calloc(1, bank->size);
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if (!current_data)
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return ERROR_FAIL;
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retval = psoc5lp_nvl_read(bank, current_data, offset, byte_count);
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if (retval != ERROR_OK) {
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free(current_data);
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return retval;
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}
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for (i = offset; i < byte_count; i++) {
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if (current_data[i] != buffer[i]) {
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write_required = true;
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break;
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}
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}
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if (((buffer[2] & 0x80) == 0x80) && ((current_data[0] & 0x0C) != 0x08))
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pullup_needed = true;
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if (((buffer[3] ^ current_data[3]) & 0x08) == 0x08)
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ecc_changed = true;
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free(current_data);
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if (!write_required) {
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LOG_INFO("Unchanged, skipping NVL write");
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return ERROR_OK;
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}
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if (pullup_needed) {
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retval = target_read_u8(target, PRT1_PC2, &val);
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if (retval != ERROR_OK)
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return retval;
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val &= 0xF0;
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val |= 0x05;
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retval = target_write_u8(target, PRT1_PC2, val);
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if (retval != ERROR_OK)
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return retval;
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}
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for (i = offset; i < byte_count; i++) {
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retval = psoc5lp_spc_load_byte(target,
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SPC_ARRAY_NVL_USER, i, buffer[i]);
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if (retval != ERROR_OK)
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return retval;
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retval = psoc5lp_spc_read_volatile_byte(target,
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SPC_ARRAY_NVL_USER, i, &val);
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if (retval != ERROR_OK)
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return retval;
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if (val != buffer[i]) {
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LOG_ERROR("Failed to load NVL byte %" PRIu32 ": "
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"expected 0x%02" PRIx8 ", read 0x%02" PRIx8,
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i, buffer[i], val);
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return ERROR_FLASH_OPERATION_FAILED;
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}
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}
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retval = psoc5lp_spc_write_user_nvl(target, SPC_ARRAY_NVL_USER);
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if (retval != ERROR_OK)
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return retval;
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if (ecc_changed) {
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retval = target_call_reset_callbacks(target, RESET_INIT);
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if (retval != ERROR_OK)
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LOG_WARNING("Reset failed after enabling or disabling ECC");
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}
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return ERROR_OK;
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}
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static int psoc5lp_nvl_protect_check(struct flash_bank *bank)
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{
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int i;
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for (i = 0; i < bank->num_sectors; i++)
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bank->sectors[i].is_protected = -1;
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return ERROR_OK;
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}
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static int psoc5lp_nvl_get_info_command(struct flash_bank *bank,
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char *buf, int buf_size)
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{
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struct psoc5lp_nvl_flash_bank *psoc_nvl_bank = bank->driver_priv;
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char part_number[PART_NUMBER_LEN];
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psoc5lp_get_part_number(psoc_nvl_bank->device, part_number);
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snprintf(buf, buf_size, "%s", part_number);
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return ERROR_OK;
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}
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static int psoc5lp_nvl_probe(struct flash_bank *bank)
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{
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struct psoc5lp_nvl_flash_bank *psoc_nvl_bank = bank->driver_priv;
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int retval;
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if (psoc_nvl_bank->probed)
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return ERROR_OK;
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if (bank->target->state != TARGET_HALTED) {
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LOG_ERROR("Target not halted");
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return ERROR_TARGET_NOT_HALTED;
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}
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retval = psoc5lp_find_device(bank->target, &psoc_nvl_bank->device);
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if (retval != ERROR_OK)
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return retval;
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bank->base = NVL_META_BASE;
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bank->size = 4;
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bank->num_sectors = 1;
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bank->sectors = calloc(bank->num_sectors,
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sizeof(struct flash_sector));
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bank->sectors[0].offset = 0;
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bank->sectors[0].size = 4;
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bank->sectors[0].is_erased = -1;
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bank->sectors[0].is_protected = -1;
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psoc_nvl_bank->probed = true;
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return ERROR_OK;
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}
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static int psoc5lp_nvl_auto_probe(struct flash_bank *bank)
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{
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struct psoc5lp_nvl_flash_bank *psoc_nvl_bank = bank->driver_priv;
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if (psoc_nvl_bank->probed)
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return ERROR_OK;
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return psoc5lp_nvl_probe(bank);
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}
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FLASH_BANK_COMMAND_HANDLER(psoc5lp_nvl_flash_bank_command)
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{
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struct psoc5lp_nvl_flash_bank *psoc_nvl_bank;
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psoc_nvl_bank = malloc(sizeof(struct psoc5lp_nvl_flash_bank));
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if (!psoc_nvl_bank)
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return ERROR_FLASH_OPERATION_FAILED;
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psoc_nvl_bank->probed = false;
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bank->driver_priv = psoc_nvl_bank;
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return ERROR_OK;
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}
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static const struct command_registration psoc5lp_nvl_exec_command_handlers[] = {
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COMMAND_REGISTRATION_DONE
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};
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static const struct command_registration psoc5lp_nvl_command_handlers[] = {
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{
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.name = "psoc5lp_nvl",
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.mode = COMMAND_ANY,
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.help = "PSoC 5LP NV Latch command group",
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.usage = "",
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.chain = psoc5lp_nvl_exec_command_handlers,
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},
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COMMAND_REGISTRATION_DONE
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};
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struct flash_driver psoc5lp_nvl_flash = {
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.name = "psoc5lp_nvl",
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.commands = psoc5lp_nvl_command_handlers,
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.flash_bank_command = psoc5lp_nvl_flash_bank_command,
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.info = psoc5lp_nvl_get_info_command,
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.probe = psoc5lp_nvl_probe,
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.auto_probe = psoc5lp_nvl_auto_probe,
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.protect_check = psoc5lp_nvl_protect_check,
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.read = psoc5lp_nvl_read,
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.erase = psoc5lp_nvl_erase,
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.erase_check = psoc5lp_nvl_erase_check,
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.write = psoc5lp_nvl_write,
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};
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/*
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* EEPROM
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*/
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@ -58,6 +58,7 @@ $_TARGETNAME configure -event reset-init {
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set _FLASHNAME $_CHIPNAME.flash
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flash bank $_FLASHNAME psoc5lp 0x00000000 0 0 0 $_TARGETNAME
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flash bank $_CHIPNAME.eeprom psoc5lp_eeprom 0x40008000 0 0 0 $_TARGETNAME
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flash bank $_CHIPNAME.nvl psoc5lp_nvl 0 0 0 0 $_TARGETNAME
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if {![using_hla]} {
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cortex_m reset_config sysresetreq
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