- further work on ETB decoding (not yet functional)
- fixed several uses of uninitialized bits (Thanks to Vincent Palatin for finding and fixing these bugs) git-svn-id: svn://svn.berlios.de/openocd/trunk@145 b42882b7-edfa-0310-969c-e2dbd0fdcd60__archive__
drath
parent
a1562e8f56
commit
054b091623
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@ -354,7 +354,12 @@ int str_to_buf(char* str, int str_len, u8 *buf, int buf_len, int radix)
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}
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for (j = 0; j < CEIL(buf_len, 8); j++)
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buf[j] = b256_buf[j];
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{
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if (j < b256_len)
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buf[j] = b256_buf[j];
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else
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buf[j] = 0;
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}
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/* mask out bits that don't belong to the buffer */
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if (buf_len % 8)
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@ -1039,6 +1039,7 @@ int jtag_read_buffer(u8 *buffer, scan_command_t *cmd)
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{
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int num_bits = cmd->fields[i].num_bits;
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u8 *captured = buf_set_buf(buffer, bit_count, malloc(CEIL(num_bits, 8)), 0, num_bits);
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#ifdef _DEBUG_JTAG_IO_
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char *char_buf;
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@ -1217,7 +1218,7 @@ int jtag_examine_chain()
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for (i = 0; i < JTAG_MAX_CHAIN_SIZE; i++)
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{
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buf_set_u32(idcode_buffer, 0, 32, 0x000000FF);
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buf_set_u32(idcode_buffer, i * 32, 32, 0x000000FF);
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}
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jtag_add_plain_dr_scan(1, &field, TAP_TLR, NULL);
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@ -2496,6 +2496,8 @@ int handle_arm7_9_etb_command(struct command_context_s *cmd_ctx, char *cmd, char
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arm7_9->etb->chain_pos = strtoul(args[1], NULL, 0);
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arm7_9->etb->cur_scan_chain = -1;
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arm7_9->etb->reg_cache = NULL;
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arm7_9->etb->RAM_width = 0;
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arm7_9->etb->RAM_depth = 0;
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return ERROR_OK;
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}
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253
src/target/etb.c
253
src/target/etb.c
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@ -58,6 +58,14 @@ int etb_read_reg(reg_t *reg);
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int handle_arm7_9_etb_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
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int handle_arm7_9_etb_dump_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
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char *etmv1_branch_reason_string[] =
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{
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"normal pc change", "tracing enabled", "restart after FIFO overflow",
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"exit from debug state", "peridoic synchronization point",
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"reserved", "reserved", "reserved"
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};
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int etb_set_instr(etb_t *etb, u32 new_instr)
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{
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jtag_device_t *device = jtag_get_device(etb->chain_pos);
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@ -334,15 +342,74 @@ int etb_register_commands(struct command_context_s *cmd_ctx, command_t *arm7_9_c
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return ERROR_OK;
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}
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#define PIPESTAT(x) ((x) & 0x7)
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#define TRACEPKT(x) (((x) & 0x7fff8) >> 3)
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#define TRACESYNC(x) (((x) & 0x80000) >> 19)
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int etmv1_next_packet(int trace_depth, u32 *trace_data, int frame, int *port_half, int apo, u8 *packet)
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{
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while (frame < trace_depth)
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{
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if (apo > 0)
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{
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if (TRACESYNC(trace_data[frame]))
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apo--;
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}
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else
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{
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/* we're looking for a branch address, skip if TRACESYNC isn't set */
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if ((apo == 0) && (!TRACESYNC(trace_data[frame])))
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{
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frame++;
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continue;
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}
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/* TRACEPKT is valid if this isn't a TD nor a TRIGGER cycle */
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if (((PIPESTAT(trace_data[frame]) != 0x7) && (PIPESTAT(trace_data[frame]) != 0x6))
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&& !((apo == 0) && (!TRACESYNC(trace_data[frame]))))
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{
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if (*port_half == 0)
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{
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*packet = TRACEPKT(trace_data[frame]) & 0xff;
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*port_half = 1;
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}
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else
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{
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*packet = (TRACEPKT(trace_data[frame]) & 0xff00) >> 8;
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*port_half = 0;
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frame++;
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}
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return frame;
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}
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}
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frame++;
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}
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/* we reached the end of the trace without finding the packet we're looking for
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* tracing is finished
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*/
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return -1;
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}
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int handle_arm7_9_etb_dump_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
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{
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int retval;
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target_t *target = get_current_target(cmd_ctx);
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armv4_5_common_t *armv4_5;
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arm7_9_common_t *arm7_9;
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int i;
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int i, j, k;
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int first_frame = 0;
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int last_frame;
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int addressbits_valid = 0;
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u32 address = 0x0;
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u32 *trace_data;
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int port_half = 0;
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int last_instruction = -1;
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u8 branch_reason;
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u8 packet;
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char trace_output[256];
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int trace_output_len;
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u8 apo;
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if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
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{
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@ -367,29 +434,191 @@ int handle_arm7_9_etb_dump_command(struct command_context_s *cmd_ctx, char *cmd,
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arm7_9->etb->RAM_width = buf_get_u32(arm7_9->etb->reg_cache->reg_list[ETB_RAM_WIDTH].value, 0, 32);
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}
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trace_data = malloc(sizeof(u32) * arm7_9->etb->RAM_depth);
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etb_read_reg(&arm7_9->etb->reg_cache->reg_list[ETB_STATUS]);
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etb_read_reg(&arm7_9->etb->reg_cache->reg_list[ETB_RAM_WRITE_POINTER]);
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jtag_execute_queue();
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/* check if we overflowed, and adjust first and last frame of the trace accordingly */
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if (buf_get_u32(arm7_9->etb->reg_cache->reg_list[ETB_STATUS].value, 1, 1))
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{
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first_frame = buf_get_u32(arm7_9->etb->reg_cache->reg_list[ETB_RAM_WRITE_POINTER].value, 0, 32);
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last_frame = first_frame - 1;
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}
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else
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{
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last_frame = buf_get_u32(arm7_9->etb->reg_cache->reg_list[ETB_RAM_WRITE_POINTER].value, 0, 32) - 1;
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}
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last_frame = buf_get_u32(arm7_9->etb->reg_cache->reg_list[ETB_RAM_WRITE_POINTER].value, 0, 32) - 1;
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etb_write_reg(&arm7_9->etb->reg_cache->reg_list[ETB_RAM_READ_POINTER], first_frame);
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for (i = first_frame; (i % arm7_9->etb->RAM_depth) != last_frame; i++)
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{
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u32 trace_data;
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/* read trace data from ETB */
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i = first_frame;
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j = 0;
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do {
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etb_read_reg(&arm7_9->etb->reg_cache->reg_list[ETB_RAM_DATA]);
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jtag_execute_queue();
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trace_data = buf_get_u32(arm7_9->etb->reg_cache->reg_list[ETB_RAM_DATA].value, 0, 32);
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command_print(cmd_ctx, "%8.8i: %i %2.2x %2.2x %2.2x (0x%8.8x)",
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i % 2048, (trace_data >> 19) & 1, (trace_data >> 11) & 0xff, (trace_data >> 3) & 0xff, trace_data & 0x7, trace_data);
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trace_data[j++] = buf_get_u32(arm7_9->etb->reg_cache->reg_list[ETB_RAM_DATA].value, 0, 32);
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i++;
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} while ((i % arm7_9->etb->RAM_depth) != (first_frame % arm7_9->etb->RAM_depth));
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for (i = 0, j = 0; i < arm7_9->etb->RAM_depth; i++)
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{
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int trigger = 0;
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trace_output_len = 0;
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/* catch trigger, actual PIPESTAT is encoded in TRACEPKT[2:0] */
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if (PIPESTAT(trace_data[i]) == 0x6)
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{
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trigger = 1;
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trace_data[i] &= ~0x7;
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trace_data[i] |= TRACEPKT(trace_data[i]) & 0x7;
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}
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if (addressbits_valid == 32)
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{
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trace_output_len += snprintf(trace_output + trace_output_len, 256 - trace_output_len,
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"%i: 0x%8.8x %s", i, address, (trigger) ? "(TRIGGER) " : "");
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}
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else if (addressbits_valid != 0)
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{
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trace_output_len += snprintf(trace_output + trace_output_len, 256 - trace_output_len,
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"%i: 0x...%x %s", i, address, (trigger) ? "(TRIGGER) " : "");
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}
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else
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{
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trace_output_len += snprintf(trace_output + trace_output_len, 256 - trace_output_len,
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"%i: 0xUNK %s", i, (trigger) ? "(TRIGGER) " : "");
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}
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switch (PIPESTAT(trace_data[i]))
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{
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case 0x0:
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trace_output_len += snprintf(trace_output + trace_output_len, 256 - trace_output_len,
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"IE");
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break;
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case 0x1:
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trace_output_len += snprintf(trace_output + trace_output_len, 256 - trace_output_len,
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"ID");
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break;
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case 0x2:
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/* Instruction exectued - TRACEPKT might be valid, but belongs to another cycle */
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trace_output_len += snprintf(trace_output + trace_output_len, 256 - trace_output_len,
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"IN");
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break;
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case 0x3:
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/* WAIT cycle - TRACEPKT is valid, but belongs to another cycle */
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trace_output_len += snprintf(trace_output + trace_output_len, 256 - trace_output_len,
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"WT");
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break;
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case 0x4:
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/* following a branch two APO cycles are output on PIPESTAT[1:0]
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* but another BE/BD could overwrite the current branch,
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* or a trigger could cause the APO to be output on TRACEPKT[1:0]
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*/
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if ((PIPESTAT(trace_data[i + 1]) == 0x4)
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|| (PIPESTAT(trace_data[i + 1]) == 0x5))
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{
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/* another branch occured, we ignore this one */
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j = (j < i + 1) ? i + 1 : j;
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break;
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}
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else if (PIPESTAT(trace_data[i + 1]) == 0x6)
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{
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apo = TRACEPKT(trace_data[i + 1]) & 0x3;
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}
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else
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{
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apo = PIPESTAT(trace_data[i + 1]) & 0x3;
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}
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if ((PIPESTAT(trace_data[i + 2]) == 0x4)
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|| (PIPESTAT(trace_data[i + 2]) == 0x5))
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{
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j = (j < i + 2) ? i + 1 : j;
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i = i + 1;
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break;
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}
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else if (PIPESTAT(trace_data[i + 2]) == 0x6)
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{
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apo |= (TRACEPKT(trace_data[i + 2]) & 0x3) << 2;
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}
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else
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{
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apo = (PIPESTAT(trace_data[i + 1]) & 0x3) << 2;
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}
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branch_reason = -1;
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k = 0;
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do
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{
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if ((j = etmv1_next_packet(arm7_9->etb->RAM_depth, trace_data, j, &port_half, apo, &packet)) != -1)
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{
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address &= ~(0x7f << (k * 7));
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address |= (packet & 0x7f) << (k * 7);
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}
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else
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{
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break;
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}
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k++;
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} while ((k < 5) && (packet & 0x80));
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if (addressbits_valid < ((k * 7 > 32) ? 32 : k * 7))
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addressbits_valid = (k * 7 > 32) ? 32 : k * 7;
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if (k == 5)
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{
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branch_reason = (packet & 0x7) >> 4;
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trace_output_len += snprintf(trace_output + trace_output_len, 256 - trace_output_len,
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"BE 0x%x (/%i) (%s)", address, addressbits_valid, etmv1_branch_reason_string[branch_reason]);
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}
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else
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{
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trace_output_len += snprintf(trace_output + trace_output_len, 256 - trace_output_len,
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"BE 0x%x (/%i)", address, addressbits_valid);
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}
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break;
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case 0x5:
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trace_output_len += snprintf(trace_output + trace_output_len, 256 - trace_output_len,
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"BD");
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break;
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case 0x6:
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/* We catch the trigger event before we get here */
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ERROR("TR pipestat should have been caught earlier");
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trace_output_len += snprintf(trace_output + trace_output_len, 256 - trace_output_len,
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"--");
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break;
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case 0x7:
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/* TRACE disabled - TRACEPKT = invalid */
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trace_output_len += snprintf(trace_output + trace_output_len, 256 - trace_output_len,
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"TD");
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break;
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}
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/* PIPESTAT other than WT (b011) and TD (b111) mean we executed an instruction */
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if ((PIPESTAT(trace_data[i]) & 0x3) != 0x3)
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{
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last_instruction = i;
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address += 4;
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}
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/* The group of packets for a particular instruction cannot start on or before any
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* previous functional PIPESTAT (IE, IN, ID, BE, or BD)
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*/
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if (j < last_instruction)
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{
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j = last_instruction + 1;
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}
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/* restore trigger PIPESTAT to ensure TRACEPKT is ignored */
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if (trigger == 1)
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{
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trace_data[i] &= ~0x7;
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trace_data[i] |= 0x6;
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}
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command_print(cmd_ctx, "%s (raw: 0x%8.8x)", trace_output, trace_data[i]);
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}
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return ERROR_OK;
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Loading…
Reference in New Issue