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- added svn props for newly added files 

git-svn-id: svn://svn.berlios.de/openocd/trunk@615 b42882b7-edfa-0310-969c-e2dbd0fdcd60
__archive__
ntfreak 2008-04-24 11:09:28 +00:00
parent 6ef27f4534
commit 040e254243
18 changed files with 3137 additions and 3139 deletions
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804
src/flash/ocl.c
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@ -1,402 +1,402 @@
/***************************************************************************
* Copyright (C) 2007 by Pavel Chromy *
* chromy@asix.cz *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc., *
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
***************************************************************************/
#ifdef HAVE_CONFIG_H
#include "config.h"
#endif
#include "replacements.h"
#include "ocl.h"
#include "flash.h"
#include "target.h"
#include "log.h"
#include "binarybuffer.h"
#include "types.h"
#include "embeddedice.h"
#include "arm7_9_common.h"
#include <stdlib.h>
#include <string.h>
#include <unistd.h>
int ocl_register_commands(struct command_context_s *cmd_ctx);
int ocl_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank);
int ocl_erase(struct flash_bank_s *bank, int first, int last);
int ocl_protect(struct flash_bank_s *bank, int set, int first, int last);
int ocl_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count);
int ocl_probe(struct flash_bank_s *bank);
int ocl_erase_check(struct flash_bank_s *bank);
int ocl_protect_check(struct flash_bank_s *bank);
int ocl_info(struct flash_bank_s *bank, char *buf, int buf_size);
int ocl_auto_probe(struct flash_bank_s *bank);
flash_driver_t ocl_flash =
{
.name = "ocl",
.register_commands = ocl_register_commands,
.flash_bank_command = ocl_flash_bank_command,
.erase = ocl_erase,
.protect = ocl_protect,
.write = ocl_write,
.probe = ocl_probe,
.erase_check = ocl_erase_check,
.protect_check = ocl_protect_check,
.info = ocl_info,
.auto_probe = ocl_auto_probe
};
typedef struct ocl_priv_s
{
arm_jtag_t *jtag_info;
int buflen;
int bufalign;
} ocl_priv_t;
int ocl_register_commands(struct command_context_s *cmd_ctx)
{
return ERROR_OK;
}
int ocl_erase_check(struct flash_bank_s *bank)
{
return ERROR_OK;
}
int ocl_protect_check(struct flash_bank_s *bank)
{
return ERROR_OK;
}
/* flash_bank ocl 0 0 0 0 <target#> */
int ocl_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank)
{
int retval;
armv4_5_common_t *armv4_5;
arm7_9_common_t *arm7_9;
ocl_priv_t *ocl;
if (argc < 6)
{
LOG_WARNING("incomplete flash_bank ocl configuration");
return ERROR_FLASH_BANK_INVALID;
}
if ((retval = arm7_9_get_arch_pointers(bank->target, &armv4_5, &arm7_9)) != ERROR_OK)
return retval;
ocl = bank->driver_priv = malloc(sizeof(ocl_priv_t));
ocl->jtag_info = &arm7_9->jtag_info;
ocl->buflen = 0;
ocl->bufalign = 1;
return ERROR_OK;
}
int ocl_erase(struct flash_bank_s *bank, int first, int last)
{
ocl_priv_t *ocl = bank->driver_priv;
int retval;
u32 dcc_buffer[3];
/* check preconditions */
if (bank->num_sectors == 0)
return ERROR_FLASH_BANK_NOT_PROBED;
if (bank->target->state != TARGET_RUNNING)
{
LOG_ERROR("target has to be running to communicate with the loader");
return ERROR_TARGET_NOT_RUNNING;
}
if ((first == 0) && (last == bank->num_sectors - 1))
{
dcc_buffer[0] = OCL_ERASE_ALL;
if ((retval = embeddedice_send(ocl->jtag_info, dcc_buffer, 1) != ERROR_OK))
return retval;
}
else
{
dcc_buffer[0] = OCL_ERASE_BLOCK;
dcc_buffer[1] = first;
dcc_buffer[2] = last;
if ((retval = embeddedice_send(ocl->jtag_info, dcc_buffer, 3) != ERROR_OK))
return retval;
}
/* wait for response, fixed timeout of 1 s */
if ((retval = embeddedice_handshake(ocl->jtag_info, EICE_COMM_CTRL_WBIT, 1000) != ERROR_OK))
{
if (retval == ERROR_TARGET_TIMEOUT)
LOG_ERROR("loader not responding");
return retval;
}
/* receive response */
if ((retval = embeddedice_receive(ocl->jtag_info, dcc_buffer+1, 1) != ERROR_OK))
return retval;
if (dcc_buffer[1] != OCL_CMD_DONE)
{
if (dcc_buffer[0] == OCL_ERASE_ALL)
LOG_ERROR("loader response to OCL_ERASE_ALL 0x%08lX", dcc_buffer[1]);
else
LOG_ERROR("loader response to OCL_ERASE_BLOCK 0x%08lX", dcc_buffer[1]);
return ERROR_FLASH_OPERATION_FAILED;
}
return ERROR_OK;
}
int ocl_protect(struct flash_bank_s *bank, int set, int first, int last)
{
return ERROR_OK;
}
int ocl_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
{
ocl_priv_t *ocl = bank->driver_priv;
int retval;
u32 *dcc_buffer;
u32 *dcc_bufptr;
int byteofs;
int runlen;
u32 chksum;
int i;
/* check preconditions */
if (ocl->buflen == 0 || ocl->bufalign==0)
return ERROR_FLASH_BANK_NOT_PROBED;
if (bank->target->state != TARGET_RUNNING)
{
LOG_ERROR("target has to be running to communicate with the loader");
return ERROR_TARGET_NOT_RUNNING;
}
/* allocate buffer for max. ocl buffer + overhead */
dcc_buffer = malloc(sizeof(u32)*(ocl->buflen/4+3));
while (count)
{
if (count + (offset % ocl->bufalign) > ocl->buflen)
runlen = ocl->buflen - (offset % ocl->bufalign);
else
runlen = count;
dcc_buffer[0] = OCL_FLASH_BLOCK | runlen;
dcc_buffer[1] = offset;
dcc_bufptr = &dcc_buffer[2];
*dcc_bufptr = 0xffffffff;
byteofs = (offset % ocl->bufalign) % 4;
chksum = OCL_CHKS_INIT;
/* copy data to DCC buffer in proper byte order and properly aligned */
for (i=0; i<runlen; i++)
{
switch (byteofs++)
{
case 0:
*dcc_bufptr &= *(buffer++) | 0xffffff00;
break;
case 1:
*dcc_bufptr &= ((*(buffer++))<<8) | 0xffff00ff;
break;
case 2:
*dcc_bufptr &= ((*(buffer++))<<16) | 0xff00ffff;
break;
case 3:
*dcc_bufptr &= ((*(buffer++))<<24) | 0x00ffffff;
chksum ^= *(dcc_bufptr++);
*dcc_bufptr = 0xffffffff;
byteofs = 0;
break;
}
}
/* add the remaining word to checksum */
if (byteofs)
chksum ^= *(dcc_bufptr++);
*(dcc_bufptr++) = chksum;
/* send the data */
if ((retval = embeddedice_send(ocl->jtag_info, dcc_buffer, dcc_bufptr-dcc_buffer)) != ERROR_OK)
{
free(dcc_buffer);
return retval;
}
/* wait for response, fixed timeout of 1 s */
if ((retval = embeddedice_handshake(ocl->jtag_info, EICE_COMM_CTRL_WBIT, 1000) != ERROR_OK))
{
if (retval == ERROR_TARGET_TIMEOUT)
LOG_ERROR("loader not responding");
free(dcc_buffer);
return retval;
}
/* receive response */
if ((retval = embeddedice_receive(ocl->jtag_info, dcc_buffer, 1) != ERROR_OK))
{
free(dcc_buffer);
return retval;
}
if (dcc_buffer[0] != OCL_CMD_DONE)
{
LOG_ERROR("loader response to OCL_FLASH_BLOCK 0x%08lX", dcc_buffer[0]);
free(dcc_buffer);
return ERROR_FLASH_OPERATION_FAILED;
}
count -= runlen;
offset += runlen;
}
free(dcc_buffer);
return ERROR_OK;
}
int ocl_probe(struct flash_bank_s *bank)
{
ocl_priv_t *ocl = bank->driver_priv;
int retval;
u32 dcc_buffer[1];
int sectsize;
int i;
/* purge pending data in DCC */
embeddedice_receive(ocl->jtag_info, dcc_buffer, 1);
dcc_buffer[0] = OCL_PROBE;
if ((retval = embeddedice_send(ocl->jtag_info, dcc_buffer, 1) != ERROR_OK))
return retval;
/* wait for response, fixed timeout of 1 s */
if ((retval = embeddedice_handshake(ocl->jtag_info, EICE_COMM_CTRL_WBIT, 1000) != ERROR_OK))
{
if (retval == ERROR_TARGET_TIMEOUT)
LOG_ERROR("loader not responding");
return retval;
}
/* receive response */
if ((retval = embeddedice_receive(ocl->jtag_info, dcc_buffer, 1) != ERROR_OK))
return retval;
if (dcc_buffer[0] != OCL_CMD_DONE)
{
LOG_ERROR("loader response to OCL_PROBE 0x%08lX", dcc_buffer[0]);
return ERROR_FLASH_OPERATION_FAILED;
}
/* receive and fill in parameters, detection of loader is important, receive it one by one */
if ((retval = embeddedice_handshake(ocl->jtag_info, EICE_COMM_CTRL_WBIT, 0) != ERROR_OK)
|| (retval = embeddedice_receive(ocl->jtag_info, dcc_buffer, 1) != ERROR_OK))
return retval;
bank->base = dcc_buffer[0];
if ((retval = embeddedice_handshake(ocl->jtag_info, EICE_COMM_CTRL_WBIT, 0) != ERROR_OK)
|| (retval = embeddedice_receive(ocl->jtag_info, dcc_buffer, 1) != ERROR_OK))
return retval;
bank->size = dcc_buffer[0];
if ((retval = embeddedice_handshake(ocl->jtag_info, EICE_COMM_CTRL_WBIT, 0) != ERROR_OK)
|| (retval = embeddedice_receive(ocl->jtag_info, dcc_buffer, 1) != ERROR_OK))
return retval;
bank->num_sectors = dcc_buffer[0];
if ((retval = embeddedice_handshake(ocl->jtag_info, EICE_COMM_CTRL_WBIT, 0) != ERROR_OK)
|| (retval = embeddedice_receive(ocl->jtag_info, dcc_buffer, 1) != ERROR_OK))
return retval;
ocl->buflen = dcc_buffer[0] & 0xffff;
ocl->bufalign = dcc_buffer[0] >> 16;
bank->sectors = realloc(bank->sectors, sizeof(flash_sector_t)*bank->num_sectors);
if (bank->num_sectors == 0)
{
LOG_ERROR("number of sectors shall be non zero value");
return ERROR_FLASH_BANK_INVALID;
}
if (bank->size % bank->num_sectors) {
LOG_ERROR("bank size not divisible by number of sectors");
return ERROR_FLASH_BANK_INVALID;
}
sectsize = bank->size / bank->num_sectors;
for (i=0; i<bank->num_sectors; i++)
{
bank->sectors[i].offset = i * sectsize;
bank->sectors[i].size = sectsize;
bank->sectors[i].is_erased = -1;
bank->sectors[i].is_protected = -1;
}
if (ocl->bufalign == 0)
ocl->bufalign = 1;
if (ocl->buflen == 0)
{
LOG_ERROR("buflen shall be non zero value");
return ERROR_FLASH_BANK_INVALID;
}
if ((ocl->bufalign > ocl->buflen) || (ocl->buflen % ocl->bufalign))
{
LOG_ERROR("buflen is not multiple of bufalign");
return ERROR_FLASH_BANK_INVALID;
}
if (ocl->buflen % 4)
{
LOG_ERROR("buflen shall be divisible by 4");
return ERROR_FLASH_BANK_INVALID;
}
return ERROR_OK;
}
int ocl_info(struct flash_bank_s *bank, char *buf, int buf_size)
{
return ERROR_OK;
}
int ocl_auto_probe(struct flash_bank_s *bank)
{
ocl_priv_t *ocl = bank->driver_priv;
if (ocl->buflen == 0 || ocl->bufalign==0)
return ERROR_FLASH_BANK_NOT_PROBED;
return ERROR_OK;
}
/***************************************************************************
* Copyright (C) 2007 by Pavel Chromy *
* chromy@asix.cz *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc., *
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
***************************************************************************/
#ifdef HAVE_CONFIG_H
#include "config.h"
#endif
#include "replacements.h"
#include "ocl.h"
#include "flash.h"
#include "target.h"
#include "log.h"
#include "binarybuffer.h"
#include "types.h"
#include "embeddedice.h"
#include "arm7_9_common.h"
#include <stdlib.h>
#include <string.h>
#include <unistd.h>
int ocl_register_commands(struct command_context_s *cmd_ctx);
int ocl_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank);
int ocl_erase(struct flash_bank_s *bank, int first, int last);
int ocl_protect(struct flash_bank_s *bank, int set, int first, int last);
int ocl_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count);
int ocl_probe(struct flash_bank_s *bank);
int ocl_erase_check(struct flash_bank_s *bank);
int ocl_protect_check(struct flash_bank_s *bank);
int ocl_info(struct flash_bank_s *bank, char *buf, int buf_size);
int ocl_auto_probe(struct flash_bank_s *bank);
flash_driver_t ocl_flash =
{
.name = "ocl",
.register_commands = ocl_register_commands,
.flash_bank_command = ocl_flash_bank_command,
.erase = ocl_erase,
.protect = ocl_protect,
.write = ocl_write,
.probe = ocl_probe,
.erase_check = ocl_erase_check,
.protect_check = ocl_protect_check,
.info = ocl_info,
.auto_probe = ocl_auto_probe
};
typedef struct ocl_priv_s
{
arm_jtag_t *jtag_info;
int buflen;
int bufalign;
} ocl_priv_t;
int ocl_register_commands(struct command_context_s *cmd_ctx)
{
return ERROR_OK;
}
int ocl_erase_check(struct flash_bank_s *bank)
{
return ERROR_OK;
}
int ocl_protect_check(struct flash_bank_s *bank)
{
return ERROR_OK;
}
/* flash_bank ocl 0 0 0 0 <target#> */
int ocl_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank)
{
int retval;
armv4_5_common_t *armv4_5;
arm7_9_common_t *arm7_9;
ocl_priv_t *ocl;
if (argc < 6)
{
LOG_WARNING("incomplete flash_bank ocl configuration");
return ERROR_FLASH_BANK_INVALID;
}
if ((retval = arm7_9_get_arch_pointers(bank->target, &armv4_5, &arm7_9)) != ERROR_OK)
return retval;
ocl = bank->driver_priv = malloc(sizeof(ocl_priv_t));
ocl->jtag_info = &arm7_9->jtag_info;
ocl->buflen = 0;
ocl->bufalign = 1;
return ERROR_OK;
}
int ocl_erase(struct flash_bank_s *bank, int first, int last)
{
ocl_priv_t *ocl = bank->driver_priv;
int retval;
u32 dcc_buffer[3];
/* check preconditions */
if (bank->num_sectors == 0)
return ERROR_FLASH_BANK_NOT_PROBED;
if (bank->target->state != TARGET_RUNNING)
{
LOG_ERROR("target has to be running to communicate with the loader");
return ERROR_TARGET_NOT_RUNNING;
}
if ((first == 0) && (last == bank->num_sectors - 1))
{
dcc_buffer[0] = OCL_ERASE_ALL;
if ((retval = embeddedice_send(ocl->jtag_info, dcc_buffer, 1) != ERROR_OK))
return retval;
}
else
{
dcc_buffer[0] = OCL_ERASE_BLOCK;
dcc_buffer[1] = first;
dcc_buffer[2] = last;
if ((retval = embeddedice_send(ocl->jtag_info, dcc_buffer, 3) != ERROR_OK))
return retval;
}
/* wait for response, fixed timeout of 1 s */
if ((retval = embeddedice_handshake(ocl->jtag_info, EICE_COMM_CTRL_WBIT, 1000) != ERROR_OK))
{
if (retval == ERROR_TARGET_TIMEOUT)
LOG_ERROR("loader not responding");
return retval;
}
/* receive response */
if ((retval = embeddedice_receive(ocl->jtag_info, dcc_buffer+1, 1) != ERROR_OK))
return retval;
if (dcc_buffer[1] != OCL_CMD_DONE)
{
if (dcc_buffer[0] == OCL_ERASE_ALL)
LOG_ERROR("loader response to OCL_ERASE_ALL 0x%08lX", dcc_buffer[1]);
else
LOG_ERROR("loader response to OCL_ERASE_BLOCK 0x%08lX", dcc_buffer[1]);
return ERROR_FLASH_OPERATION_FAILED;
}
return ERROR_OK;
}
int ocl_protect(struct flash_bank_s *bank, int set, int first, int last)
{
return ERROR_OK;
}
int ocl_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
{
ocl_priv_t *ocl = bank->driver_priv;
int retval;
u32 *dcc_buffer;
u32 *dcc_bufptr;
int byteofs;
int runlen;
u32 chksum;
int i;
/* check preconditions */
if (ocl->buflen == 0 || ocl->bufalign==0)
return ERROR_FLASH_BANK_NOT_PROBED;
if (bank->target->state != TARGET_RUNNING)
{
LOG_ERROR("target has to be running to communicate with the loader");
return ERROR_TARGET_NOT_RUNNING;
}
/* allocate buffer for max. ocl buffer + overhead */
dcc_buffer = malloc(sizeof(u32)*(ocl->buflen/4+3));
while (count)
{
if (count + (offset % ocl->bufalign) > ocl->buflen)
runlen = ocl->buflen - (offset % ocl->bufalign);
else
runlen = count;
dcc_buffer[0] = OCL_FLASH_BLOCK | runlen;
dcc_buffer[1] = offset;
dcc_bufptr = &dcc_buffer[2];
*dcc_bufptr = 0xffffffff;
byteofs = (offset % ocl->bufalign) % 4;
chksum = OCL_CHKS_INIT;
/* copy data to DCC buffer in proper byte order and properly aligned */
for (i=0; i<runlen; i++)
{
switch (byteofs++)
{
case 0:
*dcc_bufptr &= *(buffer++) | 0xffffff00;
break;
case 1:
*dcc_bufptr &= ((*(buffer++))<<8) | 0xffff00ff;
break;
case 2:
*dcc_bufptr &= ((*(buffer++))<<16) | 0xff00ffff;
break;
case 3:
*dcc_bufptr &= ((*(buffer++))<<24) | 0x00ffffff;
chksum ^= *(dcc_bufptr++);
*dcc_bufptr = 0xffffffff;
byteofs = 0;
break;
}
}
/* add the remaining word to checksum */
if (byteofs)
chksum ^= *(dcc_bufptr++);
*(dcc_bufptr++) = chksum;
/* send the data */
if ((retval = embeddedice_send(ocl->jtag_info, dcc_buffer, dcc_bufptr-dcc_buffer)) != ERROR_OK)
{
free(dcc_buffer);
return retval;
}
/* wait for response, fixed timeout of 1 s */
if ((retval = embeddedice_handshake(ocl->jtag_info, EICE_COMM_CTRL_WBIT, 1000) != ERROR_OK))
{
if (retval == ERROR_TARGET_TIMEOUT)
LOG_ERROR("loader not responding");
free(dcc_buffer);
return retval;
}
/* receive response */
if ((retval = embeddedice_receive(ocl->jtag_info, dcc_buffer, 1) != ERROR_OK))
{
free(dcc_buffer);
return retval;
}
if (dcc_buffer[0] != OCL_CMD_DONE)
{
LOG_ERROR("loader response to OCL_FLASH_BLOCK 0x%08lX", dcc_buffer[0]);
free(dcc_buffer);
return ERROR_FLASH_OPERATION_FAILED;
}
count -= runlen;
offset += runlen;
}
free(dcc_buffer);
return ERROR_OK;
}
int ocl_probe(struct flash_bank_s *bank)
{
ocl_priv_t *ocl = bank->driver_priv;
int retval;
u32 dcc_buffer[1];
int sectsize;
int i;
/* purge pending data in DCC */
embeddedice_receive(ocl->jtag_info, dcc_buffer, 1);
dcc_buffer[0] = OCL_PROBE;
if ((retval = embeddedice_send(ocl->jtag_info, dcc_buffer, 1) != ERROR_OK))
return retval;
/* wait for response, fixed timeout of 1 s */
if ((retval = embeddedice_handshake(ocl->jtag_info, EICE_COMM_CTRL_WBIT, 1000) != ERROR_OK))
{
if (retval == ERROR_TARGET_TIMEOUT)
LOG_ERROR("loader not responding");
return retval;
}
/* receive response */
if ((retval = embeddedice_receive(ocl->jtag_info, dcc_buffer, 1) != ERROR_OK))
return retval;
if (dcc_buffer[0] != OCL_CMD_DONE)
{
LOG_ERROR("loader response to OCL_PROBE 0x%08lX", dcc_buffer[0]);
return ERROR_FLASH_OPERATION_FAILED;
}
/* receive and fill in parameters, detection of loader is important, receive it one by one */
if ((retval = embeddedice_handshake(ocl->jtag_info, EICE_COMM_CTRL_WBIT, 0) != ERROR_OK)
|| (retval = embeddedice_receive(ocl->jtag_info, dcc_buffer, 1) != ERROR_OK))
return retval;
bank->base = dcc_buffer[0];
if ((retval = embeddedice_handshake(ocl->jtag_info, EICE_COMM_CTRL_WBIT, 0) != ERROR_OK)
|| (retval = embeddedice_receive(ocl->jtag_info, dcc_buffer, 1) != ERROR_OK))
return retval;
bank->size = dcc_buffer[0];
if ((retval = embeddedice_handshake(ocl->jtag_info, EICE_COMM_CTRL_WBIT, 0) != ERROR_OK)
|| (retval = embeddedice_receive(ocl->jtag_info, dcc_buffer, 1) != ERROR_OK))
return retval;
bank->num_sectors = dcc_buffer[0];
if ((retval = embeddedice_handshake(ocl->jtag_info, EICE_COMM_CTRL_WBIT, 0) != ERROR_OK)
|| (retval = embeddedice_receive(ocl->jtag_info, dcc_buffer, 1) != ERROR_OK))
return retval;
ocl->buflen = dcc_buffer[0] & 0xffff;
ocl->bufalign = dcc_buffer[0] >> 16;
bank->sectors = realloc(bank->sectors, sizeof(flash_sector_t)*bank->num_sectors);
if (bank->num_sectors == 0)
{
LOG_ERROR("number of sectors shall be non zero value");
return ERROR_FLASH_BANK_INVALID;
}
if (bank->size % bank->num_sectors) {
LOG_ERROR("bank size not divisible by number of sectors");
return ERROR_FLASH_BANK_INVALID;
}
sectsize = bank->size / bank->num_sectors;
for (i=0; i<bank->num_sectors; i++)
{
bank->sectors[i].offset = i * sectsize;
bank->sectors[i].size = sectsize;
bank->sectors[i].is_erased = -1;
bank->sectors[i].is_protected = -1;
}
if (ocl->bufalign == 0)
ocl->bufalign = 1;
if (ocl->buflen == 0)
{
LOG_ERROR("buflen shall be non zero value");
return ERROR_FLASH_BANK_INVALID;
}
if ((ocl->bufalign > ocl->buflen) || (ocl->buflen % ocl->bufalign))
{
LOG_ERROR("buflen is not multiple of bufalign");
return ERROR_FLASH_BANK_INVALID;
}
if (ocl->buflen % 4)
{
LOG_ERROR("buflen shall be divisible by 4");
return ERROR_FLASH_BANK_INVALID;
}
return ERROR_OK;
}
int ocl_info(struct flash_bank_s *bank, char *buf, int buf_size)
{
return ERROR_OK;
}
int ocl_auto_probe(struct flash_bank_s *bank)
{
ocl_priv_t *ocl = bank->driver_priv;
if (ocl->buflen == 0 || ocl->bufalign==0)
return ERROR_FLASH_BANK_NOT_PROBED;
return ERROR_OK;
}

80
src/flash/ocl.h
View File

@ -1,40 +1,40 @@
/***************************************************************************
* Copyright (C) 2007 by Pavel Chromy *
* chromy@asix.cz *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc., *
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
***************************************************************************/
#ifndef OCL_H
#define OCL_H
/* command/response mask */
#define OCL_CMD_MASK 0xFFFF0000L
/* commads */
#define OCL_FLASH_BLOCK 0x0CFB0000L
#define OCL_ERASE_BLOCK 0x0CEB0000L
#define OCL_ERASE_ALL 0x0CEA0000L
#define OCL_PROBE 0x0CBE0000L
/* responses */
#define OCL_CMD_DONE 0x0ACD0000L
#define OCL_CMD_ERR 0x0ACE0000L
#define OCL_CHKS_FAIL 0x0ACF0000L
#define OCL_BUFF_OVER 0x0AB00000L
#define OCL_CHKS_INIT 0xC100CD0CL
#endif /* OCL_H */
/***************************************************************************
* Copyright (C) 2007 by Pavel Chromy *
* chromy@asix.cz *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc., *
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
***************************************************************************/
#ifndef OCL_H
#define OCL_H
/* command/response mask */
#define OCL_CMD_MASK 0xFFFF0000L
/* commads */
#define OCL_FLASH_BLOCK 0x0CFB0000L
#define OCL_ERASE_BLOCK 0x0CEB0000L
#define OCL_ERASE_ALL 0x0CEA0000L
#define OCL_PROBE 0x0CBE0000L
/* responses */
#define OCL_CMD_DONE 0x0ACD0000L
#define OCL_CMD_ERR 0x0ACE0000L
#define OCL_CHKS_FAIL 0x0ACF0000L
#define OCL_BUFF_OVER 0x0AB00000L
#define OCL_CHKS_INIT 0xC100CD0CL
#endif /* OCL_H */

8
src/flash/ocl/at91sam7x/at91sam7x_ocl_flash.script
View File

@ -1,4 +1,4 @@
soft_reset_halt
load_image at91sam7x_ocl.bin 0x200000
resume 0x200000
flash probe 0
soft_reset_halt
load_image at91sam7x_ocl.bin 0x200000
resume 0x200000
flash probe 0

264
src/flash/ocl/at91sam7x/at91sam7x_ram.ld
View File

@ -1,132 +1,132 @@
/****************************************************************************
* Copyright (c) 2006 by Michael Fischer. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the author nor the names of its contributors may
* be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
* THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
* THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
****************************************************************************
*
* History:
*
* 30.03.06 mifi First Version
****************************************************************************/
ENTRY(ResetHandler)
SEARCH_DIR(.)
/*
* Define stack size here
*/
FIQ_STACK_SIZE = 0x0100;
IRQ_STACK_SIZE = 0x0100;
ABT_STACK_SIZE = 0x0100;
UND_STACK_SIZE = 0x0100;
SVC_STACK_SIZE = 0x0100;
MEMORY
{
ram : org = 0x00200000, len = 64k
}
/*
* Do not change the next code
*/
SECTIONS
{
.text :
{
*(.vectors);
. = ALIGN(4);
*(.init);
. = ALIGN(4);
*(.text);
. = ALIGN(4);
*(.rodata);
. = ALIGN(4);
*(.rodata*);
. = ALIGN(4);
*(.glue_7t);
. = ALIGN(4);
*(.glue_7);
. = ALIGN(4);
etext = .;
} > ram
.data :
{
PROVIDE (__data_start = .);
*(.data)
. = ALIGN(4);
edata = .;
_edata = .;
PROVIDE (__data_end = .);
} > ram
.bss :
{
PROVIDE (__bss_start = .);
*(.bss)
*(COMMON)
. = ALIGN(4);
PROVIDE (__bss_end = .);
. = ALIGN(256);
PROVIDE (__stack_start = .);
PROVIDE (__stack_fiq_start = .);
. += FIQ_STACK_SIZE;
. = ALIGN(4);
PROVIDE (__stack_fiq_end = .);
PROVIDE (__stack_irq_start = .);
. += IRQ_STACK_SIZE;
. = ALIGN(4);
PROVIDE (__stack_irq_end = .);
PROVIDE (__stack_abt_start = .);
. += ABT_STACK_SIZE;
. = ALIGN(4);
PROVIDE (__stack_abt_end = .);
PROVIDE (__stack_und_start = .);
. += UND_STACK_SIZE;
. = ALIGN(4);
PROVIDE (__stack_und_end = .);
PROVIDE (__stack_svc_start = .);
. += SVC_STACK_SIZE;
. = ALIGN(4);
PROVIDE (__stack_svc_end = .);
PROVIDE (__stack_end = .);
PROVIDE (__heap_start = .);
} > ram
}
/*** EOF ***/
/****************************************************************************
* Copyright (c) 2006 by Michael Fischer. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the author nor the names of its contributors may
* be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
* THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
* THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
****************************************************************************
*
* History:
*
* 30.03.06 mifi First Version
****************************************************************************/
ENTRY(ResetHandler)
SEARCH_DIR(.)
/*
* Define stack size here
*/
FIQ_STACK_SIZE = 0x0100;
IRQ_STACK_SIZE = 0x0100;
ABT_STACK_SIZE = 0x0100;
UND_STACK_SIZE = 0x0100;
SVC_STACK_SIZE = 0x0100;
MEMORY
{
ram : org = 0x00200000, len = 64k
}
/*
* Do not change the next code
*/
SECTIONS
{
.text :
{
*(.vectors);
. = ALIGN(4);
*(.init);
. = ALIGN(4);
*(.text);
. = ALIGN(4);
*(.rodata);
. = ALIGN(4);
*(.rodata*);
. = ALIGN(4);
*(.glue_7t);
. = ALIGN(4);
*(.glue_7);
. = ALIGN(4);
etext = .;
} > ram
.data :
{
PROVIDE (__data_start = .);
*(.data)
. = ALIGN(4);
edata = .;
_edata = .;
PROVIDE (__data_end = .);
} > ram
.bss :
{
PROVIDE (__bss_start = .);
*(.bss)
*(COMMON)
. = ALIGN(4);
PROVIDE (__bss_end = .);
. = ALIGN(256);
PROVIDE (__stack_start = .);
PROVIDE (__stack_fiq_start = .);
. += FIQ_STACK_SIZE;
. = ALIGN(4);
PROVIDE (__stack_fiq_end = .);
PROVIDE (__stack_irq_start = .);
. += IRQ_STACK_SIZE;
. = ALIGN(4);
PROVIDE (__stack_irq_end = .);
PROVIDE (__stack_abt_start = .);
. += ABT_STACK_SIZE;
. = ALIGN(4);
PROVIDE (__stack_abt_end = .);
PROVIDE (__stack_und_start = .);
. += UND_STACK_SIZE;
. = ALIGN(4);
PROVIDE (__stack_und_end = .);
PROVIDE (__stack_svc_start = .);
. += SVC_STACK_SIZE;
. = ALIGN(4);
PROVIDE (__stack_svc_end = .);
PROVIDE (__stack_end = .);
PROVIDE (__heap_start = .);
} > ram
}
/*** EOF ***/

448
src/flash/ocl/at91sam7x/crt.s
View File

@ -1,225 +1,223 @@
/****************************************************************************
* Copyright (c) 2006 by Michael Fischer. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the author nor the names of its contributors may
* be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
* THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
* THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
****************************************************************************
*
* History:
*
* 18.12.06 mifi First Version
* The hardware initialization is based on the startup file
* crtat91sam7x256_rom.S from NutOS 4.2.1.
* Therefore partial copyright by egnite Software GmbH.
****************************************************************************/
/*
* Some defines for the program status registers
*/
ARM_MODE_USER = 0x10 /* Normal User Mode */
ARM_MODE_FIQ = 0x11 /* FIQ Fast Interrupts Mode */
ARM_MODE_IRQ = 0x12 /* IRQ Standard Interrupts Mode */
ARM_MODE_SVC = 0x13 /* Supervisor Interrupts Mode */
ARM_MODE_ABORT = 0x17 /* Abort Processing memory Faults Mode */
ARM_MODE_UNDEF = 0x1B /* Undefined Instructions Mode */
ARM_MODE_SYS = 0x1F /* System Running in Priviledged Operating Mode */
ARM_MODE_MASK = 0x1F
I_BIT = 0x80 /* disable IRQ when I bit is set */
F_BIT = 0x40 /* disable IRQ when I bit is set */
/*
* Register Base Address
*/
AIC_BASE = 0xFFFFF000
AIC_EOICR_OFF = 0x130
AIC_IDCR_OFF = 0x124
RSTC_MR = 0xFFFFFD08
RSTC_KEY = 0xA5000000
RSTC_URSTEN = 0x00000001
WDT_BASE = 0xFFFFFD40
WDT_MR_OFF = 0x00000004
WDT_WDDIS = 0x00008000
MC_BASE = 0xFFFFFF00
MC_FMR_OFF = 0x00000060
MC_FWS_1FWS = 0x00480100
.section .vectors,"ax"
.code 32
/****************************************************************************/
/* Vector table and reset entry */
/****************************************************************************/
_vectors:
ldr pc, ResetAddr /* Reset */
ldr pc, UndefAddr /* Undefined instruction */
ldr pc, SWIAddr /* Software interrupt */
ldr pc, PAbortAddr /* Prefetch abort */
ldr pc, DAbortAddr /* Data abort */
ldr pc, ReservedAddr /* Reserved */
ldr pc, IRQAddr /* IRQ interrupt */
ldr pc, FIQAddr /* FIQ interrupt */
ResetAddr: .word ResetHandler
UndefAddr: .word UndefHandler
SWIAddr: .word SWIHandler
PAbortAddr: .word PAbortHandler
DAbortAddr: .word DAbortHandler
ReservedAddr: .word 0
IRQAddr: .word IRQHandler
FIQAddr: .word FIQHandler
.ltorg
.section .init, "ax"
.code 32
.global ResetHandler
.global ExitFunction
.extern main
/****************************************************************************/
/* Reset handler */
/****************************************************************************/
ResetHandler:
/*
* The watchdog is enabled after processor reset. Disable it.
*/
ldr r1, =WDT_BASE
ldr r0, =WDT_WDDIS
str r0, [r1, #WDT_MR_OFF]
/*
* Enable user reset: assertion length programmed to 1ms
*/
ldr r0, =(RSTC_KEY | RSTC_URSTEN | (4 << 8))
ldr r1, =RSTC_MR
str r0, [r1, #0]
/*
* Use 2 cycles for flash access.
*/
ldr r1, =MC_BASE
ldr r0, =MC_FWS_1FWS
str r0, [r1, #MC_FMR_OFF]
/*
* Disable all interrupts. Useful for debugging w/o target reset.
*/
ldr r1, =AIC_BASE
mvn r0, #0
str r0, [r1, #AIC_EOICR_OFF]
str r0, [r1, #AIC_IDCR_OFF]
/*
* Setup a stack for each mode
*/
msr CPSR_c, #ARM_MODE_UNDEF | I_BIT | F_BIT /* Undefined Instruction Mode */
ldr sp, =__stack_und_end
msr CPSR_c, #ARM_MODE_ABORT | I_BIT | F_BIT /* Abort Mode */
ldr sp, =__stack_abt_end
msr CPSR_c, #ARM_MODE_FIQ | I_BIT | F_BIT /* FIQ Mode */
ldr sp, =__stack_fiq_end
msr CPSR_c, #ARM_MODE_IRQ | I_BIT | F_BIT /* IRQ Mode */
ldr sp, =__stack_irq_end
msr CPSR_c, #ARM_MODE_SVC | I_BIT | F_BIT /* Supervisor Mode */
ldr sp, =__stack_svc_end
/*
* Clear .bss section
*/
ldr r1, =__bss_start
ldr r2, =__bss_end
ldr r3, =0
bss_clear_loop:
cmp r1, r2
strne r3, [r1], #+4
bne bss_clear_loop
/*
* Jump to main
*/
mrs r0, cpsr
bic r0, r0, #I_BIT | F_BIT /* Enable FIQ and IRQ interrupt */
msr cpsr, r0
mov r0, #0 /* No arguments */
mov r1, #0 /* No arguments */
ldr r2, =main
mov lr, pc
bx r2 /* And jump... */
ExitFunction:
nop
nop
nop
b ExitFunction
/****************************************************************************/
/* Default interrupt handler */
/****************************************************************************/
UndefHandler:
b UndefHandler
SWIHandler:
b SWIHandler
PAbortHandler:
b PAbortHandler
DAbortHandler:
b DAbortHandler
IRQHandler:
b IRQHandler
FIQHandler:
b FIQHandler
.weak ExitFunction
.weak UndefHandler, PAbortHandler, DAbortHandler
.weak IRQHandler, FIQHandler
.ltorg
/*** EOF ***/
Index: src/flash/ocl/at91sam7x/dcc.c
/****************************************************************************
* Copyright (c) 2006 by Michael Fischer. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the author nor the names of its contributors may
* be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
* THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
* THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
****************************************************************************
*
* History:
*
* 18.12.06 mifi First Version
* The hardware initialization is based on the startup file
* crtat91sam7x256_rom.S from NutOS 4.2.1.
* Therefore partial copyright by egnite Software GmbH.
****************************************************************************/
/*
* Some defines for the program status registers
*/
ARM_MODE_USER = 0x10 /* Normal User Mode */
ARM_MODE_FIQ = 0x11 /* FIQ Fast Interrupts Mode */
ARM_MODE_IRQ = 0x12 /* IRQ Standard Interrupts Mode */
ARM_MODE_SVC = 0x13 /* Supervisor Interrupts Mode */
ARM_MODE_ABORT = 0x17 /* Abort Processing memory Faults Mode */
ARM_MODE_UNDEF = 0x1B /* Undefined Instructions Mode */
ARM_MODE_SYS = 0x1F /* System Running in Priviledged Operating Mode */
ARM_MODE_MASK = 0x1F
I_BIT = 0x80 /* disable IRQ when I bit is set */
F_BIT = 0x40 /* disable IRQ when I bit is set */
/*
* Register Base Address
*/
AIC_BASE = 0xFFFFF000
AIC_EOICR_OFF = 0x130
AIC_IDCR_OFF = 0x124
RSTC_MR = 0xFFFFFD08
RSTC_KEY = 0xA5000000
RSTC_URSTEN = 0x00000001
WDT_BASE = 0xFFFFFD40
WDT_MR_OFF = 0x00000004
WDT_WDDIS = 0x00008000
MC_BASE = 0xFFFFFF00
MC_FMR_OFF = 0x00000060
MC_FWS_1FWS = 0x00480100
.section .vectors,"ax"
.code 32
/****************************************************************************/
/* Vector table and reset entry */
/****************************************************************************/
_vectors:
ldr pc, ResetAddr /* Reset */
ldr pc, UndefAddr /* Undefined instruction */
ldr pc, SWIAddr /* Software interrupt */
ldr pc, PAbortAddr /* Prefetch abort */
ldr pc, DAbortAddr /* Data abort */
ldr pc, ReservedAddr /* Reserved */
ldr pc, IRQAddr /* IRQ interrupt */
ldr pc, FIQAddr /* FIQ interrupt */
ResetAddr: .word ResetHandler
UndefAddr: .word UndefHandler
SWIAddr: .word SWIHandler
PAbortAddr: .word PAbortHandler
DAbortAddr: .word DAbortHandler
ReservedAddr: .word 0
IRQAddr: .word IRQHandler
FIQAddr: .word FIQHandler
.ltorg
.section .init, "ax"
.code 32
.global ResetHandler
.global ExitFunction
.extern main
/****************************************************************************/
/* Reset handler */
/****************************************************************************/
ResetHandler:
/*
* The watchdog is enabled after processor reset. Disable it.
*/
ldr r1, =WDT_BASE
ldr r0, =WDT_WDDIS
str r0, [r1, #WDT_MR_OFF]
/*
* Enable user reset: assertion length programmed to 1ms
*/
ldr r0, =(RSTC_KEY | RSTC_URSTEN | (4 << 8))
ldr r1, =RSTC_MR
str r0, [r1, #0]
/*
* Use 2 cycles for flash access.
*/
ldr r1, =MC_BASE
ldr r0, =MC_FWS_1FWS
str r0, [r1, #MC_FMR_OFF]
/*
* Disable all interrupts. Useful for debugging w/o target reset.
*/
ldr r1, =AIC_BASE
mvn r0, #0
str r0, [r1, #AIC_EOICR_OFF]
str r0, [r1, #AIC_IDCR_OFF]
/*
* Setup a stack for each mode
*/
msr CPSR_c, #ARM_MODE_UNDEF | I_BIT | F_BIT /* Undefined Instruction Mode */
ldr sp, =__stack_und_end
msr CPSR_c, #ARM_MODE_ABORT | I_BIT | F_BIT /* Abort Mode */
ldr sp, =__stack_abt_end
msr CPSR_c, #ARM_MODE_FIQ | I_BIT | F_BIT /* FIQ Mode */
ldr sp, =__stack_fiq_end
msr CPSR_c, #ARM_MODE_IRQ | I_BIT | F_BIT /* IRQ Mode */
ldr sp, =__stack_irq_end
msr CPSR_c, #ARM_MODE_SVC | I_BIT | F_BIT /* Supervisor Mode */
ldr sp, =__stack_svc_end
/*
* Clear .bss section
*/
ldr r1, =__bss_start
ldr r2, =__bss_end
ldr r3, =0
bss_clear_loop:
cmp r1, r2
strne r3, [r1], #+4
bne bss_clear_loop
/*
* Jump to main
*/
mrs r0, cpsr
bic r0, r0, #I_BIT | F_BIT /* Enable FIQ and IRQ interrupt */
msr cpsr, r0
mov r0, #0 /* No arguments */
mov r1, #0 /* No arguments */
ldr r2, =main
mov lr, pc
bx r2 /* And jump... */
ExitFunction:
nop
nop
nop
b ExitFunction
/****************************************************************************/
/* Default interrupt handler */
/****************************************************************************/
UndefHandler:
b UndefHandler
SWIHandler:
b SWIHandler
PAbortHandler:
b PAbortHandler
DAbortHandler:
b DAbortHandler
IRQHandler:
b IRQHandler
FIQHandler:
b FIQHandler
.weak ExitFunction
.weak UndefHandler, PAbortHandler, DAbortHandler
.weak IRQHandler, FIQHandler
.ltorg
/*** EOF ***/

102
src/flash/ocl/at91sam7x/dcc.c
View File

@ -1,51 +1,51 @@
/***************************************************************************
* Copyright (C) 2007 by Pavel Chromy *
* chromy@asix.cz *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc., *
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
***************************************************************************/
#include "dcc.h"
/* debug channel read (debugger->MCU) */
uint32 dcc_rd(void)
{
volatile uint32 dcc_reg;
do {
asm volatile ("mrc p14, 0, %0, C0, C0" : "=r" (dcc_reg) : );
} while ((dcc_reg&1)==0);
asm volatile ("mrc p14, 0, %0, C1, C0" : "=r" (dcc_reg) : );
return dcc_reg;
}
/* debug channel write (MCU->debugger) */
int dcc_wr(uint32 data)
{
volatile uint32 dcc_reg;
do {
asm volatile ("mrc p14, 0, %0, C0, C0" : "=r" (dcc_reg) : );
/* operation controled by master, cancel operation
upon reception of data for immediate response */
if (dcc_reg&1) return -1;
} while (dcc_reg&2);
asm volatile ("mcr p14, 0, %0, C1, C0" : : "r" (data));
return 0;
}
/***************************************************************************
* Copyright (C) 2007 by Pavel Chromy *
* chromy@asix.cz *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc., *
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
***************************************************************************/
#include "dcc.h"
/* debug channel read (debugger->MCU) */
uint32 dcc_rd(void)
{
volatile uint32 dcc_reg;
do {
asm volatile ("mrc p14, 0, %0, C0, C0" : "=r" (dcc_reg) : );
} while ((dcc_reg&1)==0);
asm volatile ("mrc p14, 0, %0, C1, C0" : "=r" (dcc_reg) : );
return dcc_reg;
}
/* debug channel write (MCU->debugger) */
int dcc_wr(uint32 data)
{
volatile uint32 dcc_reg;
do {
asm volatile ("mrc p14, 0, %0, C0, C0" : "=r" (dcc_reg) : );
/* operation controled by master, cancel operation
upon reception of data for immediate response */
if (dcc_reg&1) return -1;
} while (dcc_reg&2);
asm volatile ("mcr p14, 0, %0, C1, C0" : : "r" (data));
return 0;
}

62
src/flash/ocl/at91sam7x/dcc.h
View File

@ -1,31 +1,31 @@
/***************************************************************************
* Copyright (C) 2007 by Pavel Chromy *
* chromy@asix.cz *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc., *
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
***************************************************************************/
#ifndef dccH
#define dccH
#include "platform.h"
/* debug channel read (debugger->MCU) */
extern uint32 dcc_rd(void);
/* debug channel write (MCU->debugger) */
extern int dcc_wr(uint32 data);
#endif
/***************************************************************************
* Copyright (C) 2007 by Pavel Chromy *
* chromy@asix.cz *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc., *
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
***************************************************************************/
#ifndef dccH
#define dccH
#include "platform.h"
/* debug channel read (debugger->MCU) */
extern uint32 dcc_rd(void);
/* debug channel write (MCU->debugger) */
extern int dcc_wr(uint32 data);
#endif

214
src/flash/ocl/at91sam7x/main.c
View File

@ -1,107 +1,107 @@
/***************************************************************************
* Copyright (C) 2007 by Pavel Chromy *
* chromy@asix.cz *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc., *
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
***************************************************************************/
#include "platform.h"
#include "ocl.h"
#include "dcc.h"
#include "samflash.h"
#define BUFSIZE 1024 /* words, i.e. 4 KiB */
uint32 buffer[1024];
void cmd_flash(uint32 cmd)
{
unsigned int len;
uint32 adr;
uint32 chksum;
unsigned int bi; /* buffer index */
unsigned int bi_start; /* receive start mark */
unsigned int bi_end; /* receive end mark */
unsigned int ofs;
int pagenum;
int result;
adr=dcc_rd();
len=cmd&0xffff;
ofs=adr%flash_page_size;
bi_start=ofs/4;
bi_end=(ofs+len+3)/4;
if (bi_end>BUFSIZE) {
dcc_wr(OCL_BUFF_OVER);
return;
}
chksum=OCL_CHKS_INIT;
for (bi=0; bi<bi_end; bi++) chksum^=buffer[bi]=dcc_rd();
if (dcc_rd()!=chksum) {
dcc_wr(OCL_CHKS_FAIL);
return;
}
/* fill in unused positions with unprogrammed values */
for (bi=0; bi<bi_start; bi++) buffer[bi]=0xffffffff;
for (bi=bi_end; bi%flash_page_size; bi++) buffer[bi]=0xffffffff;
result=0;
pagenum=adr/flash_page_size;
for (bi=0; bi<bi_end; bi+=flash_page_size/4) {
result=flash_page_program(buffer+bi, pagenum++);
if (result) break;
}
/* verify written data */
if (!result) result=flash_verify(adr, len, ((uint8 *)buffer)+ofs);
dcc_wr(OCL_CMD_DONE|result);
}
int main (void)
{
uint32 cmd;
for (;;) {
cmd=dcc_rd();
switch (cmd&OCL_CMD_MASK) {
case OCL_PROBE:
dcc_wr(OCL_CMD_DONE|flash_init());
dcc_wr(0x100000); /* base */
dcc_wr(flash_page_count*flash_page_size); /* size */
dcc_wr(1); /* num_sectors */
dcc_wr(4096 | ((unsigned long) flash_page_size<<16)); /* buflen and bufalign */
break;
case OCL_ERASE_ALL:
dcc_wr(OCL_CMD_DONE|flash_erase_all());
break;
case OCL_FLASH_BLOCK:
cmd_flash(cmd);
break;
default:
/* unknown command */
dcc_wr(OCL_CMD_ERR);
break;
}
}
return(0); /* we shall never get here, just to supress compiler warning */
}
/***************************************************************************
* Copyright (C) 2007 by Pavel Chromy *
* chromy@asix.cz *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc., *
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
***************************************************************************/
#include "platform.h"
#include "ocl.h"
#include "dcc.h"
#include "samflash.h"
#define BUFSIZE 1024 /* words, i.e. 4 KiB */
uint32 buffer[1024];
void cmd_flash(uint32 cmd)
{
unsigned int len;
uint32 adr;
uint32 chksum;
unsigned int bi; /* buffer index */
unsigned int bi_start; /* receive start mark */
unsigned int bi_end; /* receive end mark */
unsigned int ofs;
int pagenum;
int result;
adr=dcc_rd();
len=cmd&0xffff;
ofs=adr%flash_page_size;
bi_start=ofs/4;
bi_end=(ofs+len+3)/4;
if (bi_end>BUFSIZE) {
dcc_wr(OCL_BUFF_OVER);
return;
}
chksum=OCL_CHKS_INIT;
for (bi=0; bi<bi_end; bi++) chksum^=buffer[bi]=dcc_rd();
if (dcc_rd()!=chksum) {
dcc_wr(OCL_CHKS_FAIL);
return;
}
/* fill in unused positions with unprogrammed values */
for (bi=0; bi<bi_start; bi++) buffer[bi]=0xffffffff;
for (bi=bi_end; bi%flash_page_size; bi++) buffer[bi]=0xffffffff;
result=0;
pagenum=adr/flash_page_size;
for (bi=0; bi<bi_end; bi+=flash_page_size/4) {
result=flash_page_program(buffer+bi, pagenum++);
if (result) break;
}
/* verify written data */
if (!result) result=flash_verify(adr, len, ((uint8 *)buffer)+ofs);
dcc_wr(OCL_CMD_DONE|result);
}
int main (void)
{
uint32 cmd;
for (;;) {
cmd=dcc_rd();
switch (cmd&OCL_CMD_MASK) {
case OCL_PROBE:
dcc_wr(OCL_CMD_DONE|flash_init());
dcc_wr(0x100000); /* base */
dcc_wr(flash_page_count*flash_page_size); /* size */
dcc_wr(1); /* num_sectors */
dcc_wr(4096 | ((unsigned long) flash_page_size<<16)); /* buflen and bufalign */
break;
case OCL_ERASE_ALL:
dcc_wr(OCL_CMD_DONE|flash_erase_all());
break;
case OCL_FLASH_BLOCK:
cmd_flash(cmd);
break;
default:
/* unknown command */
dcc_wr(OCL_CMD_ERR);
break;
}
}
return(0); /* we shall never get here, just to supress compiler warning */
}

258
src/flash/ocl/at91sam7x/makefile
View File

@ -1,130 +1,130 @@
##############################################################################################
# Start of default section
#
TRGT = arm-elf-
CC = $(TRGT)gcc
CP = $(TRGT)objcopy
AS = $(TRGT)gcc -x assembler-with-cpp
HEX = $(CP) -O ihex
BIN = $(CP) -O binary
OBJDUMP = $(TRGT)objdump
MCU = arm7tdmi
# List all default C defines here, like -D_DEBUG=1
DDEFS =
# List all default ASM defines here, like -D_DEBUG=1
DADEFS =
# List all default directories to look for include files here
DINCDIR =
# List the default directory to look for the libraries here
DLIBDIR =
# List all default libraries here
DLIBS =
#
# End of default section
##############################################################################################
##############################################################################################
# Start of user section
#
# Define project name here
PROJECT = at91sam7x_ocl
# Define linker script file here
LDSCRIPT= at91sam7x_ram.ld
# List all user C define here, like -D_DEBUG=1
UDEFS =
# Define ASM defines here
UADEFS =
# List C source files here
SRC = main.c dcc.c samflash.c
# List ASM source files here
ASRC = crt.s
# List all user directories here
UINCDIR =
# List the user directory to look for the libraries here
ULIBDIR =
# List all user libraries here
ULIBS =
# Define optimisation level here
OPT = -O2
#
# End of user defines
##############################################################################################
INCDIR = $(patsubst %,-I%,$(DINCDIR) $(UINCDIR))
LIBDIR = $(patsubst %,-L%,$(DLIBDIR) $(ULIBDIR))
DEFS = $(DDEFS) $(UDEFS)
ADEFS = $(DADEFS) $(UADEFS)
OBJS = $(ASRC:.s=.o) $(SRC:.c=.o)
LIBS = $(DLIBS) $(ULIBS)
MCFLAGS = -mcpu=$(MCU)
ASFLAGS = $(MCFLAGS) -g -gdwarf-2 -Wa,-amhls=$(<:.s=.lst) $(ADEFS)
CPFLAGS = $(MCFLAGS) $(OPT) -gdwarf-2 -mthumb-interwork -fomit-frame-pointer -Wall -Wstrict-prototypes -fverbose-asm -Wa,-ahlms=$(<:.c=.lst) $(DEFS)
LDFLAGS = $(MCFLAGS) -nostartfiles -T$(LDSCRIPT) -Wl,-Map=$(PROJECT).map,--cref,--no-warn-mismatch $(LIBDIR)
# Generate dependency information
#CPFLAGS += -MD -MP -MF .dep/$(@F).d
#
# makefile rules
#
all: $(OBJS) $(PROJECT).elf $(PROJECT).hex $(PROJECT).bin $(PROJECT).lst
%o : %c
$(CC) -c $(CPFLAGS) -I . $(INCDIR) $< -o $@
%o : %s
$(AS) -c $(ASFLAGS) $< -o $@
%elf: $(OBJS)
$(CC) $(OBJS) $(LDFLAGS) $(LIBS) -o $@
%hex: %elf
$(HEX) $< $@
%bin: %elf
$(BIN) $< $@
%.lst: %.elf
$(OBJDUMP) -h -S $< > $@
clean:
-rm -f $(OBJS)
-rm -f $(PROJECT).elf
-rm -f $(PROJECT).map
-rm -f $(PROJECT).hex
-rm -f $(PROJECT).bin
-rm -f $(PROJECT).lst
-rm -f $(SRC:.c=.c.bak)
-rm -f $(SRC:.c=.lst)
-rm -f $(ASRC:.s=.s.bak)
-rm -f $(ASRC:.s=.lst)
-rm -fR .dep
#
# Include the dependency files, should be the last of the makefile
#
#-include $(shell mkdir .dep 2>/dev/null) $(wildcard .dep/*)
##############################################################################################
# Start of default section
#
TRGT = arm-elf-
CC = $(TRGT)gcc
CP = $(TRGT)objcopy
AS = $(TRGT)gcc -x assembler-with-cpp
HEX = $(CP) -O ihex
BIN = $(CP) -O binary
OBJDUMP = $(TRGT)objdump
MCU = arm7tdmi
# List all default C defines here, like -D_DEBUG=1
DDEFS =
# List all default ASM defines here, like -D_DEBUG=1
DADEFS =
# List all default directories to look for include files here
DINCDIR =
# List the default directory to look for the libraries here
DLIBDIR =
# List all default libraries here
DLIBS =
#
# End of default section
##############################################################################################
##############################################################################################
# Start of user section
#
# Define project name here
PROJECT = at91sam7x_ocl
# Define linker script file here
LDSCRIPT= at91sam7x_ram.ld
# List all user C define here, like -D_DEBUG=1
UDEFS =
# Define ASM defines here
UADEFS =
# List C source files here
SRC = main.c dcc.c samflash.c
# List ASM source files here
ASRC = crt.s
# List all user directories here
UINCDIR =
# List the user directory to look for the libraries here
ULIBDIR =
# List all user libraries here
ULIBS =
# Define optimisation level here
OPT = -O2
#
# End of user defines
##############################################################################################
INCDIR = $(patsubst %,-I%,$(DINCDIR) $(UINCDIR))
LIBDIR = $(patsubst %,-L%,$(DLIBDIR) $(ULIBDIR))
DEFS = $(DDEFS) $(UDEFS)
ADEFS = $(DADEFS) $(UADEFS)
OBJS = $(ASRC:.s=.o) $(SRC:.c=.o)
LIBS = $(DLIBS) $(ULIBS)
MCFLAGS = -mcpu=$(MCU)
ASFLAGS = $(MCFLAGS) -g -gdwarf-2 -Wa,-amhls=$(<:.s=.lst) $(ADEFS)
CPFLAGS = $(MCFLAGS) $(OPT) -gdwarf-2 -mthumb-interwork -fomit-frame-pointer -Wall -Wstrict-prototypes -fverbose-asm -Wa,-ahlms=$(<:.c=.lst) $(DEFS)
LDFLAGS = $(MCFLAGS) -nostartfiles -T$(LDSCRIPT) -Wl,-Map=$(PROJECT).map,--cref,--no-warn-mismatch $(LIBDIR)
# Generate dependency information
#CPFLAGS += -MD -MP -MF .dep/$(@F).d
#
# makefile rules
#
all: $(OBJS) $(PROJECT).elf $(PROJECT).hex $(PROJECT).bin $(PROJECT).lst
%o : %c
$(CC) -c $(CPFLAGS) -I . $(INCDIR) $< -o $@
%o : %s
$(AS) -c $(ASFLAGS) $< -o $@
%elf: $(OBJS)
$(CC) $(OBJS) $(LDFLAGS) $(LIBS) -o $@
%hex: %elf
$(HEX) $< $@
%bin: %elf
$(BIN) $< $@
%.lst: %.elf
$(OBJDUMP) -h -S $< > $@
clean:
-rm -f $(OBJS)
-rm -f $(PROJECT).elf
-rm -f $(PROJECT).map
-rm -f $(PROJECT).hex
-rm -f $(PROJECT).bin
-rm -f $(PROJECT).lst
-rm -f $(SRC:.c=.c.bak)
-rm -f $(SRC:.c=.lst)
-rm -f $(ASRC:.s=.s.bak)
-rm -f $(ASRC:.s=.lst)
-rm -fR .dep
#
# Include the dependency files, should be the last of the makefile
#
#-include $(shell mkdir .dep 2>/dev/null) $(wildcard .dep/*)
# *** EOF ***

80
src/flash/ocl/at91sam7x/ocl.h
View File

@ -1,40 +1,40 @@
/***************************************************************************
* Copyright (C) 2007 by Pavel Chromy *
* chromy@asix.cz *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc., *
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
***************************************************************************/
#ifndef OCL_H
#define OCL_H
/* command/response mask */
#define OCL_CMD_MASK 0xFFFF0000L
/* commads */
#define OCL_FLASH_BLOCK 0x0CFB0000L
#define OCL_ERASE_BLOCK 0x0CEB0000L
#define OCL_ERASE_ALL 0x0CEA0000L
#define OCL_PROBE 0x0CBE0000L
/* responses */
#define OCL_CMD_DONE 0x0ACD0000L
#define OCL_CMD_ERR 0x0ACE0000L
#define OCL_CHKS_FAIL 0x0ACF0000L
#define OCL_BUFF_OVER 0x0AB00000L
#define OCL_CHKS_INIT 0xC100CD0CL
#endif /* OCL_H */
/***************************************************************************
* Copyright (C) 2007 by Pavel Chromy *
* chromy@asix.cz *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc., *
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
***************************************************************************/
#ifndef OCL_H
#define OCL_H
/* command/response mask */
#define OCL_CMD_MASK 0xFFFF0000L
/* commads */
#define OCL_FLASH_BLOCK 0x0CFB0000L
#define OCL_ERASE_BLOCK 0x0CEB0000L
#define OCL_ERASE_ALL 0x0CEA0000L
#define OCL_PROBE 0x0CBE0000L
/* responses */
#define OCL_CMD_DONE 0x0ACD0000L
#define OCL_CMD_ERR 0x0ACE0000L
#define OCL_CHKS_FAIL 0x0ACF0000L
#define OCL_BUFF_OVER 0x0AB00000L
#define OCL_CHKS_INIT 0xC100CD0CL
#endif /* OCL_H */

92
src/flash/ocl/at91sam7x/platform.h
View File

@ -1,46 +1,46 @@
/***************************************************************************
* Copyright (C) 2007 by Pavel Chromy *
* chromy@asix.cz *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc., *
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
***************************************************************************/
#ifndef platformH
#define platformH
#include "samregs.h"
#define outb(_reg, _val) (*((volatile unsigned char *)(_reg)) = (_val))
#define outw(_reg, _val) (*((volatile unsigned short *)(_reg)) = (_val))
#define outr(_reg, _val) (*((volatile unsigned int *)(_reg)) = (_val))
#define inb(_reg) (*((volatile unsigned char *)(_reg)))
#define inw(_reg) (*((volatile unsigned short *)(_reg)))
#define inr(_reg) (*((volatile unsigned int *)(_reg)))
#define _BV(bit) (1 << (bit))
typedef signed char int8;
typedef unsigned char uint8;
typedef signed short int16;
typedef unsigned short uint16;
typedef signed int int32;
typedef unsigned int uint32;
#endif
/***************************************************************************
* Copyright (C) 2007 by Pavel Chromy *
* chromy@asix.cz *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc., *
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
***************************************************************************/
#ifndef platformH
#define platformH
#include "samregs.h"
#define outb(_reg, _val) (*((volatile unsigned char *)(_reg)) = (_val))
#define outw(_reg, _val) (*((volatile unsigned short *)(_reg)) = (_val))
#define outr(_reg, _val) (*((volatile unsigned int *)(_reg)) = (_val))
#define inb(_reg) (*((volatile unsigned char *)(_reg)))
#define inw(_reg) (*((volatile unsigned short *)(_reg)))
#define inr(_reg) (*((volatile unsigned int *)(_reg)))
#define _BV(bit) (1 << (bit))
typedef signed char int8;
typedef unsigned char uint8;
typedef signed short int16;
typedef unsigned short uint16;
typedef signed int int32;
typedef unsigned int uint32;
#endif

392
src/flash/ocl/at91sam7x/samflash.c
View File

@ -1,196 +1,196 @@
/***************************************************************************
* Copyright (C) 2007 by Pavel Chromy *
* chromy@asix.cz *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc., *
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
***************************************************************************/
#include "samflash.h"
unsigned int flash_page_count=1024;
unsigned int flash_page_size=256;
/* pages per lock bit */
unsigned int flash_lock_pages=1024/16;
/* detect chip and set loader parameters */
int flash_init(void)
{
unsigned int nvpsiz;
nvpsiz=(inr(DBGU_CIDR)>>8)&0xf;
switch (nvpsiz) {
case 3:
/* AT91SAM7x32 */
flash_page_count=256;
flash_page_size=128;
flash_lock_pages=256/8;
break;
case 5:
/* AT91SAM7x64 */
flash_page_count=512;
flash_page_size=128;
flash_lock_pages=512/16;
break;
case 7:
/* AT91SAM7x128*/
flash_page_count=512;
flash_page_size=256;
flash_lock_pages=512/8;
break;
case 9:
/* AT91SAM7x256 */
flash_page_count=1024;
flash_page_size=256;
flash_lock_pages=1024/16;
break;
case 10:
/* AT91SAM7x512 */
flash_page_count=2048;
flash_page_size=256;
flash_lock_pages=2048/32;
break;
default:
return FLASH_STAT_INITE;
}
return FLASH_STAT_OK;
}
/* program single flash page */
int flash_page_program(uint32 *data, int page_num)
{
int i;
int efc_ofs;
uint32 *flash_ptr;
uint32 *data_ptr;
/* select proper controller */
if (page_num>=1024) efc_ofs=0x10;
else efc_ofs=0;
/* wait until FLASH is ready, just for sure */
while ((inr(MC_FSR+efc_ofs)&MC_FRDY)==0);
/* calculate page address, only lower 8 bits are used to address the latch,
but the upper part of address is needed for writing to proper EFC */
flash_ptr=(uint32 *)(FLASH_AREA_ADDR+(page_num*flash_page_size));
data_ptr=data;
/* copy data to latch */
for (i=flash_page_size/4; i; i--) {
/* we do not use memcpy to be sure that only 32 bit access is used */
*(flash_ptr++)=*(data_ptr++);
}
/* page number and page write command to FCR */
outr(MC_FCR+efc_ofs, ((page_num&0x3ff)<<8) | MC_KEY | MC_FCMD_WP);
/* wait until it's done */
while ((inr(MC_FSR+efc_ofs)&MC_FRDY)==0);
/* check for errors */
if ((inr(MC_FSR+efc_ofs)&MC_PROGE)) return FLASH_STAT_PROGE;
if ((inr(MC_FSR+efc_ofs)&MC_LOCKE)) return FLASH_STAT_LOCKE;
#if 0
/* verify written data */
flash_ptr=(uint32 *)(FLASH_AREA_ADDR+(page_num*flash_page_size));
data_ptr=data;
for (i=flash_page_size/4; i; i--) {
if (*(flash_ptr++)!=*(data_ptr++)) return FLASH_STAT_VERIFE;
}
#endif
return FLASH_STAT_OK;
}
int flash_erase_plane(int efc_ofs)
{
unsigned int lockbits;
int page_num;
page_num=0;
lockbits=inr(MC_FSR+efc_ofs)>>16;
while (lockbits) {
if (lockbits&1) {
/* wait until FLASH is ready, just for sure */
while ((inr(MC_FSR+efc_ofs)&MC_FRDY)==0);
outr(MC_FCR+efc_ofs, ((page_num&0x3ff)<<8) | 0x5a000004);
/* wait until it's done */
while ((inr(MC_FSR+efc_ofs)&MC_FRDY)==0);
/* check for errors */
if ((inr(MC_FSR+efc_ofs)&MC_PROGE)) return FLASH_STAT_PROGE;
if ((inr(MC_FSR+efc_ofs)&MC_LOCKE)) return FLASH_STAT_LOCKE;
}
if ((page_num+=flash_lock_pages)>flash_page_count) break;
lockbits>>=1;
}
/* wait until FLASH is ready, just for sure */
while ((inr(MC_FSR+efc_ofs)&MC_FRDY)==0);
/* erase all command to FCR */
outr(MC_FCR+efc_ofs, 0x5a000008);
/* wait until it's done */
while ((inr(MC_FSR+efc_ofs)&MC_FRDY)==0);
/* check for errors */
if ((inr(MC_FSR+efc_ofs)&MC_PROGE)) return FLASH_STAT_PROGE;
if ((inr(MC_FSR+efc_ofs)&MC_LOCKE)) return FLASH_STAT_LOCKE;
/* set no erase before programming */
outr(MC_FMR+efc_ofs, inr(MC_FMR+efc_ofs)|0x80);
return FLASH_STAT_OK;
}
/* erase whole chip */
int flash_erase_all(void)
{
int result;
if ((result=flash_erase_plane(0))!=FLASH_STAT_OK) return result;
/* the second flash controller, if any */
if (flash_page_count>1024) result=flash_erase_plane(0x10);
return result;
}
int flash_verify(uint32 adr, unsigned int len, uint8 *src)
{
unsigned char *flash_ptr;
flash_ptr=(uint8 *)FLASH_AREA_ADDR+adr;
for ( ;len; len--) {
if (*(flash_ptr++)!=*(src++)) return FLASH_STAT_VERIFE;
}
return FLASH_STAT_OK;
}
/***************************************************************************
* Copyright (C) 2007 by Pavel Chromy *
* chromy@asix.cz *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc., *
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
***************************************************************************/
#include "samflash.h"
unsigned int flash_page_count=1024;
unsigned int flash_page_size=256;
/* pages per lock bit */
unsigned int flash_lock_pages=1024/16;
/* detect chip and set loader parameters */
int flash_init(void)
{
unsigned int nvpsiz;
nvpsiz=(inr(DBGU_CIDR)>>8)&0xf;
switch (nvpsiz) {
case 3:
/* AT91SAM7x32 */
flash_page_count=256;
flash_page_size=128;
flash_lock_pages=256/8;
break;
case 5:
/* AT91SAM7x64 */
flash_page_count=512;
flash_page_size=128;
flash_lock_pages=512/16;
break;
case 7:
/* AT91SAM7x128*/
flash_page_count=512;
flash_page_size=256;
flash_lock_pages=512/8;
break;
case 9:
/* AT91SAM7x256 */
flash_page_count=1024;
flash_page_size=256;
flash_lock_pages=1024/16;
break;
case 10:
/* AT91SAM7x512 */
flash_page_count=2048;
flash_page_size=256;
flash_lock_pages=2048/32;
break;
default:
return FLASH_STAT_INITE;
}
return FLASH_STAT_OK;
}
/* program single flash page */
int flash_page_program(uint32 *data, int page_num)
{
int i;
int efc_ofs;
uint32 *flash_ptr;
uint32 *data_ptr;
/* select proper controller */
if (page_num>=1024) efc_ofs=0x10;
else efc_ofs=0;
/* wait until FLASH is ready, just for sure */
while ((inr(MC_FSR+efc_ofs)&MC_FRDY)==0);
/* calculate page address, only lower 8 bits are used to address the latch,
but the upper part of address is needed for writing to proper EFC */
flash_ptr=(uint32 *)(FLASH_AREA_ADDR+(page_num*flash_page_size));
data_ptr=data;
/* copy data to latch */
for (i=flash_page_size/4; i; i--) {
/* we do not use memcpy to be sure that only 32 bit access is used */
*(flash_ptr++)=*(data_ptr++);
}
/* page number and page write command to FCR */
outr(MC_FCR+efc_ofs, ((page_num&0x3ff)<<8) | MC_KEY | MC_FCMD_WP);
/* wait until it's done */
while ((inr(MC_FSR+efc_ofs)&MC_FRDY)==0);
/* check for errors */
if ((inr(MC_FSR+efc_ofs)&MC_PROGE)) return FLASH_STAT_PROGE;
if ((inr(MC_FSR+efc_ofs)&MC_LOCKE)) return FLASH_STAT_LOCKE;
#if 0
/* verify written data */
flash_ptr=(uint32 *)(FLASH_AREA_ADDR+(page_num*flash_page_size));
data_ptr=data;
for (i=flash_page_size/4; i; i--) {
if (*(flash_ptr++)!=*(data_ptr++)) return FLASH_STAT_VERIFE;
}
#endif
return FLASH_STAT_OK;
}
int flash_erase_plane(int efc_ofs)
{
unsigned int lockbits;
int page_num;
page_num=0;
lockbits=inr(MC_FSR+efc_ofs)>>16;
while (lockbits) {
if (lockbits&1) {
/* wait until FLASH is ready, just for sure */
while ((inr(MC_FSR+efc_ofs)&MC_FRDY)==0);
outr(MC_FCR+efc_ofs, ((page_num&0x3ff)<<8) | 0x5a000004);
/* wait until it's done */
while ((inr(MC_FSR+efc_ofs)&MC_FRDY)==0);
/* check for errors */
if ((inr(MC_FSR+efc_ofs)&MC_PROGE)) return FLASH_STAT_PROGE;
if ((inr(MC_FSR+efc_ofs)&MC_LOCKE)) return FLASH_STAT_LOCKE;
}
if ((page_num+=flash_lock_pages)>flash_page_count) break;
lockbits>>=1;
}
/* wait until FLASH is ready, just for sure */
while ((inr(MC_FSR+efc_ofs)&MC_FRDY)==0);
/* erase all command to FCR */
outr(MC_FCR+efc_ofs, 0x5a000008);
/* wait until it's done */
while ((inr(MC_FSR+efc_ofs)&MC_FRDY)==0);
/* check for errors */
if ((inr(MC_FSR+efc_ofs)&MC_PROGE)) return FLASH_STAT_PROGE;
if ((inr(MC_FSR+efc_ofs)&MC_LOCKE)) return FLASH_STAT_LOCKE;
/* set no erase before programming */
outr(MC_FMR+efc_ofs, inr(MC_FMR+efc_ofs)|0x80);
return FLASH_STAT_OK;
}
/* erase whole chip */
int flash_erase_all(void)
{
int result;
if ((result=flash_erase_plane(0))!=FLASH_STAT_OK) return result;
/* the second flash controller, if any */
if (flash_page_count>1024) result=flash_erase_plane(0x10);
return result;
}
int flash_verify(uint32 adr, unsigned int len, uint8 *src)
{
unsigned char *flash_ptr;
flash_ptr=(uint8 *)FLASH_AREA_ADDR+adr;
for ( ;len; len--) {
if (*(flash_ptr++)!=*(src++)) return FLASH_STAT_VERIFE;
}
return FLASH_STAT_OK;
}

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src/flash/ocl/at91sam7x/samflash.h
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@ -1,48 +1,48 @@
/***************************************************************************
* Copyright (C) 2007 by Pavel Chromy *
* chromy@asix.cz *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc., *
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
***************************************************************************/
#ifndef samflashH
#define samflashH
#include "platform.h"
#define FLASH_AREA_ADDR 0x100000
#define FLASH_STAT_OK 0
#define FLASH_STAT_PROGE 1
#define FLASH_STAT_LOCKE 2
#define FLASH_STAT_VERIFE 3
#define FLASH_STAT_INITE 4
extern unsigned int flash_page_count;
extern unsigned int flash_page_size; /* words */
/* detect chip and set loader parameters */
extern int flash_init(void);
/* program single flash page */
extern int flash_page_program(uint32 *data, int page_num);
/* erase whole chip */
extern int flash_erase_all(void);
/* verify written data */
extern int flash_verify(uint32 adr, unsigned int len, uint8 *src);
#endif
/***************************************************************************
* Copyright (C) 2007 by Pavel Chromy *
* chromy@asix.cz *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc., *
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
***************************************************************************/
#ifndef samflashH
#define samflashH
#include "platform.h"
#define FLASH_AREA_ADDR 0x100000
#define FLASH_STAT_OK 0
#define FLASH_STAT_PROGE 1
#define FLASH_STAT_LOCKE 2
#define FLASH_STAT_VERIFE 3
#define FLASH_STAT_INITE 4
extern unsigned int flash_page_count;
extern unsigned int flash_page_size; /* words */
/* detect chip and set loader parameters */
extern int flash_init(void);
/* program single flash page */
extern int flash_page_program(uint32 *data, int page_num);
/* erase whole chip */
extern int flash_erase_all(void);
/* verify written data */
extern int flash_verify(uint32 adr, unsigned int len, uint8 *src);
#endif

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src/flash/ocl/at91sam7x/samregs.h
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/*
* Copyright (C) 2005-2006 by egnite Software GmbH. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the copyright holders nor the names of
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
* SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
* THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* For additional information see http://www.ethernut.de/
*/
#ifndef samregsH
#define samregsH
/*
* Register definitions below copied from NutOS
*/
#define DBGU_BASE 0xFFFFF200 /*!< \brief DBGU base address. */
#define DBGU_CIDR_OFF 0x00000040 /*!< \brief DBGU chip ID register offset. */
#define DBGU_CIDR (DBGU_BASE + DBGU_CIDR_OFF) /*!< \brief DBGU chip ID register. */
#define MC_BASE 0xFFFFFF00 /*!< \brief Memory controller base. */
#define MC_FMR_OFF 0x00000060 /*!< \brief MC flash mode register offset. */
#define MC_FMR (MC_BASE + MC_FMR_OFF) /*!< \brief MC flash mode register address. */
#define MC_FRDY 0x00000001 /*!< \brief Flash ready. */
#define MC_LOCKE 0x00000004 /*!< \brief Lock error. */
#define MC_PROGE 0x00000008 /*!< \brief Programming error. */
#define MC_NEBP 0x00000080 /*!< \brief No erase before programming. */
#define MC_FWS_MASK 0x00000300 /*!< \brief Flash wait state mask. */
#define MC_FWS_1R2W 0x00000000 /*!< \brief 1 cycle for read, 2 for write operations. */
#define MC_FWS_2R3W 0x00000100 /*!< \brief 2 cycles for read, 3 for write operations. */
#define MC_FWS_3R4W 0x00000200 /*!< \brief 3 cycles for read, 4 for write operations. */
#define MC_FWS_4R4W 0x00000300 /*!< \brief 4 cycles for read and write operations. */
#define MC_FMCN_MASK 0x00FF0000 /*!< \brief Flash microsecond cycle number mask. */
#define MC_FCR_OFF 0x00000064 /*!< \brief MC flash command register offset. */
#define MC_FCR (MC_BASE + MC_FCR_OFF) /*!< \brief MC flash command register address. */
#define MC_FCMD_MASK 0x0000000F /*!< \brief Flash command mask. */
#define MC_FCMD_NOP 0x00000000 /*!< \brief No command. */
#define MC_FCMD_WP 0x00000001 /*!< \brief Write page. */
#define MC_FCMD_SLB 0x00000002 /*!< \brief Set lock bit. */
#define MC_FCMD_WPL 0x00000003 /*!< \brief Write page and lock. */
#define MC_FCMD_CLB 0x00000004 /*!< \brief Clear lock bit. */
#define MC_FCMD_EA 0x00000008 /*!< \brief Erase all. */
#define MC_FCMD_SGPB 0x0000000B /*!< \brief Set general purpose NVM bit. */
#define MC_FCMD_CGPB 0x0000000D /*!< \brief Clear general purpose NVM bit. */
#define MC_FCMD_SSB 0x0000000F /*!< \brief Set security bit. */
#define MC_PAGEN_MASK 0x0003FF00 /*!< \brief Page number mask. */
#define MC_KEY 0x5A000000 /*!< \brief Writing protect key. */
#define MC_FSR_OFF 0x00000068 /*!< \brief MC flash status register offset. */
#define MC_FSR (MC_BASE + MC_FSR_OFF) /*!< \brief MC flash status register address. */
#define MC_SECURITY 0x00000010 /*!< \brief Security bit status. */
#endif
/*
* Copyright (C) 2005-2006 by egnite Software GmbH. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the copyright holders nor the names of
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
* SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
* THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* For additional information see http://www.ethernut.de/
*/
#ifndef samregsH
#define samregsH
/*
* Register definitions below copied from NutOS
*/
#define DBGU_BASE 0xFFFFF200 /*!< \brief DBGU base address. */
#define DBGU_CIDR_OFF 0x00000040 /*!< \brief DBGU chip ID register offset. */
#define DBGU_CIDR (DBGU_BASE + DBGU_CIDR_OFF) /*!< \brief DBGU chip ID register. */
#define MC_BASE 0xFFFFFF00 /*!< \brief Memory controller base. */
#define MC_FMR_OFF 0x00000060 /*!< \brief MC flash mode register offset. */
#define MC_FMR (MC_BASE + MC_FMR_OFF) /*!< \brief MC flash mode register address. */
#define MC_FRDY 0x00000001 /*!< \brief Flash ready. */
#define MC_LOCKE 0x00000004 /*!< \brief Lock error. */
#define MC_PROGE 0x00000008 /*!< \brief Programming error. */
#define MC_NEBP 0x00000080 /*!< \brief No erase before programming. */
#define MC_FWS_MASK 0x00000300 /*!< \brief Flash wait state mask. */
#define MC_FWS_1R2W 0x00000000 /*!< \brief 1 cycle for read, 2 for write operations. */
#define MC_FWS_2R3W 0x00000100 /*!< \brief 2 cycles for read, 3 for write operations. */
#define MC_FWS_3R4W 0x00000200 /*!< \brief 3 cycles for read, 4 for write operations. */
#define MC_FWS_4R4W 0x00000300 /*!< \brief 4 cycles for read and write operations. */
#define MC_FMCN_MASK 0x00FF0000 /*!< \brief Flash microsecond cycle number mask. */
#define MC_FCR_OFF 0x00000064 /*!< \brief MC flash command register offset. */
#define MC_FCR (MC_BASE + MC_FCR_OFF) /*!< \brief MC flash command register address. */
#define MC_FCMD_MASK 0x0000000F /*!< \brief Flash command mask. */
#define MC_FCMD_NOP 0x00000000 /*!< \brief No command. */
#define MC_FCMD_WP 0x00000001 /*!< \brief Write page. */
#define MC_FCMD_SLB 0x00000002 /*!< \brief Set lock bit. */
#define MC_FCMD_WPL 0x00000003 /*!< \brief Write page and lock. */
#define MC_FCMD_CLB 0x00000004 /*!< \brief Clear lock bit. */
#define MC_FCMD_EA 0x00000008 /*!< \brief Erase all. */
#define MC_FCMD_SGPB 0x0000000B /*!< \brief Set general purpose NVM bit. */
#define MC_FCMD_CGPB 0x0000000D /*!< \brief Clear general purpose NVM bit. */
#define MC_FCMD_SSB 0x0000000F /*!< \brief Set security bit. */
#define MC_PAGEN_MASK 0x0003FF00 /*!< \brief Page number mask. */
#define MC_KEY 0x5A000000 /*!< \brief Writing protect key. */
#define MC_FSR_OFF 0x00000068 /*!< \brief MC flash status register offset. */
#define MC_FSR (MC_BASE + MC_FSR_OFF) /*!< \brief MC flash status register address. */
#define MC_SECURITY 0x00000010 /*!< \brief Security bit status. */
#endif

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testing/results/template.html
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<html>
<meta http-equiv="content-type" content="text/html;charset=iso-8859-1">
<body>
<a href="../testcases.html">Testcases</a>
<table border="1">
<tr><td>Test</td><td>Interface</td><td>Target</td><td>Result</td></tr>
<tr><td><a href="../testcases.html#CON001">CON001</a></td><td> FILL IN! </td><td>FILL IN!</td><td>PASS/FAIL</td></tr>
<tr><td><a href="../testcases.html#CON002">CON002</a></td><td> FILL IN! </td><td>FILL IN!</td><td>PASS/FAIL</td></tr>
<tr><td><a href="../testcases.html#RES001">RES001</a></td><td> FILL IN! </td><td>FILL IN!</td><td>PASS/FAIL</td></tr>
<tr><td><a href="../testcases.html#RES002">RES002</a></td><td> FILL IN! </td><td>FILL IN!</td><td>PASS/FAIL</td></tr>
<tr><td><a href="../testcases.html#RES003">RES003</a></td><td> FILL IN! </td><td>FILL IN!</td><td>PASS/FAIL</td></tr>
<tr><td><a href="../testcases.html#DBG001">DBG001</a></td><td> FILL IN! </td><td>FILL IN!</td><td>PASS/FAIL</td></tr>
</table>
</body>
<html>
<meta http-equiv="content-type" content="text/html;charset=iso-8859-1">
<body>
<a href="../testcases.html">Testcases</a>
<table border="1">
<tr><td>Test</td><td>Interface</td><td>Target</td><td>Result</td></tr>
<tr><td><a href="../testcases.html#CON001">CON001</a></td><td> FILL IN! </td><td>FILL IN!</td><td>PASS/FAIL</td></tr>
<tr><td><a href="../testcases.html#CON002">CON002</a></td><td> FILL IN! </td><td>FILL IN!</td><td>PASS/FAIL</td></tr>
<tr><td><a href="../testcases.html#RES001">RES001</a></td><td> FILL IN! </td><td>FILL IN!</td><td>PASS/FAIL</td></tr>
<tr><td><a href="../testcases.html#RES002">RES002</a></td><td> FILL IN! </td><td>FILL IN!</td><td>PASS/FAIL</td></tr>
<tr><td><a href="../testcases.html#RES003">RES003</a></td><td> FILL IN! </td><td>FILL IN!</td><td>PASS/FAIL</td></tr>
<tr><td><a href="../testcases.html#DBG001">DBG001</a></td><td> FILL IN! </td><td>FILL IN!</td><td>PASS/FAIL</td></tr>
</table>
</body>
</html>

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testing/smoketests.html
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<html>
<meta http-equiv="content-type" content="text/html;charset=iso-8859-1">
<body>
<h1>OpenOCD smoketest results</h1>
These tests can be performed on any JTAG device as long as they are executed using the unmodified code from SVN.
<p>The latest version in which the test is known to have passed is in the table below.</p>
<h2>Vocabulary</h2>
<table border="1">
<tr>
<td width="100">Passed version</td>
<td>The latest branch and version on which the test is known to pass</td>
</tr>
<tr>
<td width="100">Broken version</td>
<td>The latest branch and version on which the test is known to fail. n/a when older than passed version.</td>
</tr>
<tr>
<td width="100">ID</td>
<td>A unqiue ID to refer to a test. The unique numbers are maintained in this file. Note that the same test can be run on different hardware/interface. Each combination yields a unique id. </td>
</tr>
</table>
<p></p>
<table border="1">
<tr>
<th width="100">Unique ID</th>
<th width="165">Synopsis</th>
<th align="center" width="110">JTAG device</th>
<th align="center" width="110">Passed version</th>
<th align="center" width="110">Broken version</th>
</tr>
<tr>
<td >fill_malloc</td>
<td width="165">Fill malloc() memory with garbage</td>
<td align="center" >n/a</td>
<td align="center" >n/a</td>
<td align="center" >n/a</td>
</tr>
<tr>
<td >ocd1</td>
<td width="165">Telnet Windows</td>
<td align="center" >n/a</td>
<td align="center" >n/a</td>
<td align="center" >n/a</td>
</tr>
<tr>
<td >ocd2</td>
<td width="165">Telnet Linux</td>
<td align="center" >n/a</td>
<td align="center" >n/a</td>
<td align="center" >n/a</td>
</tr>
<tr>
<td >ocd3</td>
<td width="165">Telnet Cygwin</td>
<td align="center" >n/a</td>
<td align="center" >n/a</td>
<td align="center" >n/a</td>
</tr>
<tr>
<td ><a href="#test_ocd4">ocd4</a></td>
<td width="165">ARM7 debugging</td>
<td align="center" >n/a</td>
<td align="center" >n/a</td>
<td align="center" >n/a</td>
</tr>
<tr>
<td >SAM9260</td>
<td width="165">SAM9260 debugging</td>
<td align="center">ft2232 </td>
<td align="center">500</td>
<td align="center">n/a</td>
</tr>
<tr>
<td >xscale1</td>
<td width="165">XScale debugging</td>
<td align="center" >bitbang</td>
<td align="center" >505</td>
<td align="center" >n/a</td>
</tr>
<tr>
<td >xscale2</td>
<td width="165">XScale debugging</td>
<td align="center" >FT2232</td>
<td align="center" >202</td>
<td align="center" >n/a</td>
</tr>
<tr>
<td ><a href="#bdte-ram">bdte-ram1</a></td>
<td width="165">str710 ram debugging</td>
<td align="center" >JTAGkey</td>
<td align="center" >536</td>
<td align="center" >n/a</td>
</tr>
<tr>
<td ><a href="#bdte-rom">bdte-rom2</a></td>
<td width="165">str710 rom debugging</td>
<td align="center" >JTAGkey</td>
<td align="center" >536</td>
<td align="center" >n/a</td>
</tr>
<tr>
<td ><a href="#bdte-ram">bdte-ram3</a></td>
<td width="165">str912 ram debugging</td>
<td align="center" >JTAGkey</td>
<td align="center" >536</td>
<td align="center" >n/a</td>
</tr>
<tr>
<td ><a href="#bdte-rom">bdte-rom4</a></td>
<td width="165">str912 rom debugging</td>
<td align="center" >JTAGkey</td>
<td align="center" >536</td>
<td align="center" >n/a</td>
</tr>
<tr>
<td ><a href="#bdte-ram">bdte-ram5</a></td>
<td width="165">lpc2148 ram debugging</td>
<td align="center" >JTAGkey</td>
<td align="center" >536</td>
<td align="center" >n/a</td>
</tr>
<tr>
<td ><a href="#bdte-rom">bdte-rom6</a></td>
<td width="165">lpc2148 rom debugging</td>
<td align="center" >JTAGkey</td>
<td align="center" >536</td>
<td align="center" >n/a</td>
</tr>
<tr>
<td ><a href="#bdte-ram">bdte-ram7</a></td>
<td width="165">lpc2294 ram debugging</td>
<td align="center" >JTAGkey</td>
<td align="center" >536</td>
<td align="center" >n/a</td>
</tr>
<tr>
<td ><a href="#bdte-rom">bdte-rom8</a></td>
<td width="165">lpc2294 rom debugging</td>
<td align="center" >JTAGkey</td>
<td align="center" >536</td>
<td align="center" >n/a</td>
</tr>
<tr>
<td ><a href="#bdte-ram">bdte-ram9</a></td>
<td width="165">sam7s256 ram debugging</td>
<td align="center" >JTAGkey</td>
<td align="center" >536</td>
<td align="center" >n/a</td>
</tr>
<tr>
<td ><a href="#bdte-rom">bdte-rom10</a></td>
<td width="165">sam7s256 rom debugging</td>
<td align="center" >JTAGkey</td>
<td align="center" >536</td>
<td align="center" >n/a</td>
</tr>
<tr>
<td ><a href="#bdte-ram">bdte-ram11</a></td>
<td width="165">sam7x256 ram debugging</td>
<td align="center" >JTAGkey</td>
<td align="center" >517</td>
<td align="center" >n/a</td>
</tr>
<tr>
<td ><a href="#bdte-rom">bdte-rom12</a></td>
<td width="165">sam7x256 rom debugging</td>
<td align="center" >JTAGkey</td>
<td align="center" >517</td>
<td align="center" >n/a</td>
</tr>
<tr>
<td ><a href="#bdte-ram">bdte-ram13</a></td>
<td width="165">at91r40008 ram debugging</td>
<td align="center" >JTAGkey</td>
<td align="center" >536</td>
<td align="center" >n/a</td>
</tr>
</table>
<p></p>
<hr>
<h1>OpenOCD JTAG device test results</h1>
Each JTAG device must be tested
<table border="1">
<tr>
<th align="center" width="40">ID</th>
<th width="90">Synopsis</th>
<th >Passed version</th>
<th >Broken version</th>
</tr>
<tr>
<td width="40">jtag1</td>
<td width="90">Parport</td>
<td align="center" >n/a</td>
<td align="center" >n/a</td>
</tr>
<tr>
<td width="40">jtag2</td>
<td width="90">JTAGkey</td>
<td align="center" >536</td>
<td align="center" >n/a</td>
</tr>
<tr>
<td width="40">jtag3</td>
<td width="90">Turtelizer2</td>
<td align="center" >536</td>
<td align="center" >n/a</td>
</tr>
<tr>
<td width="40">jtag4</td>
<td width="90">JTAGkey</td>
<td align="center" >536</td>
<td align="center" >n/a</td>
</tr>
<tr>
<td width="40">jtag5</td>
<td width="90">add new one</td>
<td align="center" >n/a</td>
<td align="center" >n/a</td>
</tr>
</table>
<p>jtag1:</p>
<p>jtag2: Tested on Windows XP Prof. (SP2) with original FTDI&nbsp;driver.</p>
<p>jtag3: Tested on Windows XP Prof. (SP2) with original FTDI&nbsp;driver.</p>
<p>jtag4: Tested on Mac OS X (10.5.2, Intel) with libftdi-0.10 and libusb-0.1.12</p>
<p>jtag5:</p>
<hr>
<h1>OpenOCD JTAG device speed test result</h1>
<p>The test result is in KB/sec.</p>
<table border="1">
<tr>
<th align="center" width="50">ID</th>
<th width="90">Synopsis</th>
<th width="40">r320</th>
<th width="40">r420</th>
<th width="40">r423</th>
<th width="40">r459</th>
<th width="40">r517</th>
<th width="40">r536</th>
</tr>
<tr>
<td width="50"><a href="#speed1">speed1</a></td>
<td width="90">JTAGkey</td>
<td align="center" width="40">93</td>
<td align="center" width="40">64 </td>
<td align="center" width="40">93</td>
<td align="center" width="40">93</td>
<td align="center" width="40">93</td>
<td align="center" width="40">93</td>
</tr>
<tr>
<td width="50"><a href="#speed2">speed2</a></td>
<td width="90">JTAGkey</td>
<td align="center" width="40">n/a</td>
<td align="center" width="40">n/a</td>
<td align="center" width="40">n/a</td>
<td align="center" width="40">n/a</td>
<td align="center" width="40">52</td>
<td align="center" width="40">52</td>
</tr>
<tr>
<td width="50">speed3</td>
<td width="90">add new one</td>
<td align="center" width="40">n/a</td>
<td align="center" width="40">n/a</td>
<td align="center" width="40">n/a</td>
<td align="center" width="40">n/a</td>
<td align="center" width="40">n/a</td>
<td align="center" width="40">n/a</td>
</tr>
</table>
<p></p>
<hr>
<h1>Policy on removing features from OpenOCD</h1>
If a feature in OpenOCD is known to be broken and nobody has submitted a fix and the feature is causing trouble for maintainence, it can be removed from OpenOCD trunk. The threshold for temporarily removing something from OpenOCD trunk is low to ease maintainence and place the burden of maintainence on those that care about a feature.
<p>Note that code is never deleted from OpenOCD svn, it remains in svn so if somebody sees a feature removed that they would like kept, they have but to port and fix that feature back up to main trunk. This document can be helpful in this regard in that the latest working version and the known broken version may be listed.</p>
<h1>Policy on adding features from OpenOCD</h1>
To add a feature to OpenOCD, generally it should not break any existing features and it should be functional and the code reasonably readable and useful to others in the OpenOCD community. The code does not have to be completed. Work in progress is fine for OpenOCD trunk.
<p>Also new tests should be defined. Note that the code does not have to pass all the tests. In fact it can be helpful to have tests to describe facets that really should be working, but aren't done yet. </p>
<hr>
<h1>ocd4 - ARM7 debugging<a name="test_ocd4"></a></h1>
Connect to ARM7 device(any), use GDB load to load a program into RAM and single halt, resume and single step.
<hr>
<h1>bdte-ram (Basic debugging test with Eclipse in RAM)<a id="bdte-ram" name="bdte-ram"></a></h1>
<p>This test was made under Eclipse with the Zylin Embedded CDT&nbsp;plugin. For the GDB &quot;Initialize commands&quot; take a look in the examples/&lt;target&gt;/prj/<b>eclipse_ram.gdb</b> file.</p>
<p>Start debugging, the debugger should stop at main. set some breakpoints and &quot;Resume&quot;. If the debugger hit a breakpoint check if the &quot;Variables&quot; looks correct. Remove some breakpoints and &quot;Resume&quot; again. If the target is running, use the &quot;Suspend&quot; function and use &quot;Step Into&quot; or &quot;Step Over&quot; through the source. Even open the &quot;Disassembly&quot; view and enable the &quot;Instruction Stepping Mode&quot;. Now you can single step through the assembler source. Use &quot;Resume&quot; again to run the program, set a breakpoint while the target is running. Check if you can inspect the variables with the mouse over. Play a little with the target...</p>
<hr>
<h1>bdte-rom (Basic debugging test with Eclipse in ROM)<a id="bdte-rom" name="bdte-rom"></a></h1>
<p>This test was made under Eclipse with the Zylin Embedded CDT&nbsp;plugin. For the GDB &quot;Initialize commands&quot; take a look in the examples/&lt;target&gt;/prj/<b>eclipse_rom.gdb</b> file.</p>
<p>Start debugging, the debugger should download and store the program in the flash of the target.</p>
<p>Now you can make some tests like described in the <a href="#bdte-ram">bdte-ram</a> section above too.</p>
<hr>
<h1>speed1 - Download speed test<a id="speed1" name="speed1"></a></h1>
<p>For this test a STR710 with external memory was used. The example project can be found under examples/STR710JtagSpeed. Here Eclipse or the arm-elf-gdb can be used to download the test.elf file into the RAM. The result of the GDB&nbsp;can look like:</p>
<p>Loading section .text, size 0x6019c lma 0x62000000<br>
Start address 0x62000040, load size 393628<br>
Transfer rate: 93 KB/sec, 2008 bytes/write.</p>
<p>In this example a speed of 93 KB/sec was reached. The hardware which was used for the test can be found <a href="http://www.yagarto.de/projects/str7usbmsd/index.html" target="new">here</a>.</p>
<p>The test was made on Windows XP Prof. (SP2) with a JTAGkey and the original FTDI driver.</p>
<hr>
<h1>speed2 - Download speed test<a id="speed2" name="speed2"></a></h1>
<p>For this test a STR710 with external memory was used. The example project can be found under examples/STR710JtagSpeed. Here Eclipse or the arm-elf-gdb can be used to download the test.elf file into the RAM. The result of the GDB&nbsp;can look like:</p>
<p>Loading section .text, size 0x6019c lma 0x62000000<br>
Start address 0x62000040, load size 393628<br>Transfer rate: 52 KB/sec, 2008 bytes/write.</p>
<p>In this example a speed of 52 KB/sec was reached. The hardware which was used for the test can be found <a href="http://www.yagarto.de/projects/str7usbmsd/index.html" target="new">here</a>.</p>
<p>The test was made on Mac OS X (10.5.2, Intel) with a JTAGkey and the following driver:</p>
<p>- libftdi 0.10<br>
- libusb 0.1.12</p>
<p></p>
<p></p>
</body>
<html>
<meta http-equiv="content-type" content="text/html;charset=iso-8859-1">
<body>
<h1>OpenOCD smoketest results</h1>
These tests can be performed on any JTAG device as long as they are executed using the unmodified code from SVN.
<p>The latest version in which the test is known to have passed is in the table below.</p>
<h2>Vocabulary</h2>
<table border="1">
<tr>
<td width="100">Passed version</td>
<td>The latest branch and version on which the test is known to pass</td>
</tr>
<tr>
<td width="100">Broken version</td>
<td>The latest branch and version on which the test is known to fail. n/a when older than passed version.</td>
</tr>
<tr>
<td width="100">ID</td>
<td>A unqiue ID to refer to a test. The unique numbers are maintained in this file. Note that the same test can be run on different hardware/interface. Each combination yields a unique id. </td>
</tr>
</table>
<p></p>
<table border="1">
<tr>
<th width="100">Unique ID</th>
<th width="165">Synopsis</th>
<th align="center" width="110">JTAG device</th>
<th align="center" width="110">Passed version</th>
<th align="center" width="110">Broken version</th>
</tr>
<tr>
<td >fill_malloc</td>
<td width="165">Fill malloc() memory with garbage</td>
<td align="center" >n/a</td>
<td align="center" >n/a</td>
<td align="center" >n/a</td>
</tr>
<tr>
<td >ocd1</td>
<td width="165">Telnet Windows</td>
<td align="center" >n/a</td>
<td align="center" >n/a</td>
<td align="center" >n/a</td>
</tr>
<tr>
<td >ocd2</td>
<td width="165">Telnet Linux</td>
<td align="center" >n/a</td>
<td align="center" >n/a</td>
<td align="center" >n/a</td>
</tr>
<tr>
<td >ocd3</td>
<td width="165">Telnet Cygwin</td>
<td align="center" >n/a</td>
<td align="center" >n/a</td>
<td align="center" >n/a</td>
</tr>
<tr>
<td ><a href="#test_ocd4">ocd4</a></td>
<td width="165">ARM7 debugging</td>
<td align="center" >n/a</td>
<td align="center" >n/a</td>
<td align="center" >n/a</td>
</tr>
<tr>
<td >SAM9260</td>
<td width="165">SAM9260 debugging</td>
<td align="center">ft2232 </td>
<td align="center">500</td>
<td align="center">n/a</td>
</tr>
<tr>
<td >xscale1</td>
<td width="165">XScale debugging</td>
<td align="center" >bitbang</td>
<td align="center" >505</td>
<td align="center" >n/a</td>
</tr>
<tr>
<td >xscale2</td>
<td width="165">XScale debugging</td>
<td align="center" >FT2232</td>
<td align="center" >202</td>
<td align="center" >n/a</td>
</tr>
<tr>
<td ><a href="#bdte-ram">bdte-ram1</a></td>
<td width="165">str710 ram debugging</td>
<td align="center" >JTAGkey</td>
<td align="center" >536</td>
<td align="center" >n/a</td>
</tr>
<tr>
<td ><a href="#bdte-rom">bdte-rom2</a></td>
<td width="165">str710 rom debugging</td>
<td align="center" >JTAGkey</td>
<td align="center" >536</td>
<td align="center" >n/a</td>
</tr>
<tr>
<td ><a href="#bdte-ram">bdte-ram3</a></td>
<td width="165">str912 ram debugging</td>
<td align="center" >JTAGkey</td>
<td align="center" >536</td>
<td align="center" >n/a</td>
</tr>
<tr>
<td ><a href="#bdte-rom">bdte-rom4</a></td>
<td width="165">str912 rom debugging</td>
<td align="center" >JTAGkey</td>
<td align="center" >536</td>
<td align="center" >n/a</td>
</tr>
<tr>
<td ><a href="#bdte-ram">bdte-ram5</a></td>
<td width="165">lpc2148 ram debugging</td>
<td align="center" >JTAGkey</td>
<td align="center" >536</td>
<td align="center" >n/a</td>
</tr>
<tr>
<td ><a href="#bdte-rom">bdte-rom6</a></td>
<td width="165">lpc2148 rom debugging</td>
<td align="center" >JTAGkey</td>
<td align="center" >536</td>
<td align="center" >n/a</td>
</tr>
<tr>
<td ><a href="#bdte-ram">bdte-ram7</a></td>
<td width="165">lpc2294 ram debugging</td>
<td align="center" >JTAGkey</td>
<td align="center" >536</td>
<td align="center" >n/a</td>
</tr>
<tr>
<td ><a href="#bdte-rom">bdte-rom8</a></td>
<td width="165">lpc2294 rom debugging</td>
<td align="center" >JTAGkey</td>
<td align="center" >536</td>
<td align="center" >n/a</td>
</tr>
<tr>
<td ><a href="#bdte-ram">bdte-ram9</a></td>
<td width="165">sam7s256 ram debugging</td>
<td align="center" >JTAGkey</td>
<td align="center" >536</td>
<td align="center" >n/a</td>
</tr>
<tr>
<td ><a href="#bdte-rom">bdte-rom10</a></td>
<td width="165">sam7s256 rom debugging</td>
<td align="center" >JTAGkey</td>
<td align="center" >536</td>
<td align="center" >n/a</td>
</tr>
<tr>
<td ><a href="#bdte-ram">bdte-ram11</a></td>
<td width="165">sam7x256 ram debugging</td>
<td align="center" >JTAGkey</td>
<td align="center" >517</td>
<td align="center" >n/a</td>
</tr>
<tr>
<td ><a href="#bdte-rom">bdte-rom12</a></td>
<td width="165">sam7x256 rom debugging</td>
<td align="center" >JTAGkey</td>
<td align="center" >517</td>
<td align="center" >n/a</td>
</tr>
<tr>
<td ><a href="#bdte-ram">bdte-ram13</a></td>
<td width="165">at91r40008 ram debugging</td>
<td align="center" >JTAGkey</td>
<td align="center" >536</td>
<td align="center" >n/a</td>
</tr>
</table>
<p></p>
<hr>
<h1>OpenOCD JTAG device test results</h1>
Each JTAG device must be tested
<table border="1">
<tr>
<th align="center" width="40">ID</th>
<th width="90">Synopsis</th>
<th >Passed version</th>
<th >Broken version</th>
</tr>
<tr>
<td width="40">jtag1</td>
<td width="90">Parport</td>
<td align="center" >n/a</td>
<td align="center" >n/a</td>
</tr>
<tr>
<td width="40">jtag2</td>
<td width="90">JTAGkey</td>
<td align="center" >536</td>
<td align="center" >n/a</td>
</tr>
<tr>
<td width="40">jtag3</td>
<td width="90">Turtelizer2</td>
<td align="center" >536</td>
<td align="center" >n/a</td>
</tr>
<tr>
<td width="40">jtag4</td>
<td width="90">JTAGkey</td>
<td align="center" >536</td>
<td align="center" >n/a</td>
</tr>
<tr>
<td width="40">jtag5</td>
<td width="90">add new one</td>
<td align="center" >n/a</td>
<td align="center" >n/a</td>
</tr>
</table>
<p>jtag1:</p>
<p>jtag2: Tested on Windows XP Prof. (SP2) with original FTDI&nbsp;driver.</p>
<p>jtag3: Tested on Windows XP Prof. (SP2) with original FTDI&nbsp;driver.</p>
<p>jtag4: Tested on Mac OS X (10.5.2, Intel) with libftdi-0.10 and libusb-0.1.12</p>
<p>jtag5:</p>
<hr>
<h1>OpenOCD JTAG device speed test result</h1>
<p>The test result is in KB/sec.</p>
<table border="1">
<tr>
<th align="center" width="50">ID</th>
<th width="90">Synopsis</th>
<th width="40">r320</th>
<th width="40">r420</th>
<th width="40">r423</th>
<th width="40">r459</th>
<th width="40">r517</th>
<th width="40">r536</th>
</tr>
<tr>
<td width="50"><a href="#speed1">speed1</a></td>
<td width="90">JTAGkey</td>
<td align="center" width="40">93</td>
<td align="center" width="40">64 </td>
<td align="center" width="40">93</td>
<td align="center" width="40">93</td>
<td align="center" width="40">93</td>
<td align="center" width="40">93</td>
</tr>
<tr>
<td width="50"><a href="#speed2">speed2</a></td>
<td width="90">JTAGkey</td>
<td align="center" width="40">n/a</td>
<td align="center" width="40">n/a</td>
<td align="center" width="40">n/a</td>
<td align="center" width="40">n/a</td>
<td align="center" width="40">52</td>
<td align="center" width="40">52</td>
</tr>
<tr>
<td width="50">speed3</td>
<td width="90">add new one</td>
<td align="center" width="40">n/a</td>
<td align="center" width="40">n/a</td>
<td align="center" width="40">n/a</td>
<td align="center" width="40">n/a</td>
<td align="center" width="40">n/a</td>
<td align="center" width="40">n/a</td>
</tr>
</table>
<p></p>
<hr>
<h1>Policy on removing features from OpenOCD</h1>
If a feature in OpenOCD is known to be broken and nobody has submitted a fix and the feature is causing trouble for maintainence, it can be removed from OpenOCD trunk. The threshold for temporarily removing something from OpenOCD trunk is low to ease maintainence and place the burden of maintainence on those that care about a feature.
<p>Note that code is never deleted from OpenOCD svn, it remains in svn so if somebody sees a feature removed that they would like kept, they have but to port and fix that feature back up to main trunk. This document can be helpful in this regard in that the latest working version and the known broken version may be listed.</p>
<h1>Policy on adding features from OpenOCD</h1>
To add a feature to OpenOCD, generally it should not break any existing features and it should be functional and the code reasonably readable and useful to others in the OpenOCD community. The code does not have to be completed. Work in progress is fine for OpenOCD trunk.
<p>Also new tests should be defined. Note that the code does not have to pass all the tests. In fact it can be helpful to have tests to describe facets that really should be working, but aren't done yet. </p>
<hr>
<h1>ocd4 - ARM7 debugging<a name="test_ocd4"></a></h1>
Connect to ARM7 device(any), use GDB load to load a program into RAM and single halt, resume and single step.
<hr>
<h1>bdte-ram (Basic debugging test with Eclipse in RAM)<a id="bdte-ram" name="bdte-ram"></a></h1>
<p>This test was made under Eclipse with the Zylin Embedded CDT&nbsp;plugin. For the GDB &quot;Initialize commands&quot; take a look in the examples/&lt;target&gt;/prj/<b>eclipse_ram.gdb</b> file.</p>
<p>Start debugging, the debugger should stop at main. set some breakpoints and &quot;Resume&quot;. If the debugger hit a breakpoint check if the &quot;Variables&quot; looks correct. Remove some breakpoints and &quot;Resume&quot; again. If the target is running, use the &quot;Suspend&quot; function and use &quot;Step Into&quot; or &quot;Step Over&quot; through the source. Even open the &quot;Disassembly&quot; view and enable the &quot;Instruction Stepping Mode&quot;. Now you can single step through the assembler source. Use &quot;Resume&quot; again to run the program, set a breakpoint while the target is running. Check if you can inspect the variables with the mouse over. Play a little with the target...</p>
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<h1>bdte-rom (Basic debugging test with Eclipse in ROM)<a id="bdte-rom" name="bdte-rom"></a></h1>
<p>This test was made under Eclipse with the Zylin Embedded CDT&nbsp;plugin. For the GDB &quot;Initialize commands&quot; take a look in the examples/&lt;target&gt;/prj/<b>eclipse_rom.gdb</b> file.</p>
<p>Start debugging, the debugger should download and store the program in the flash of the target.</p>
<p>Now you can make some tests like described in the <a href="#bdte-ram">bdte-ram</a> section above too.</p>
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<h1>speed1 - Download speed test<a id="speed1" name="speed1"></a></h1>
<p>For this test a STR710 with external memory was used. The example project can be found under examples/STR710JtagSpeed. Here Eclipse or the arm-elf-gdb can be used to download the test.elf file into the RAM. The result of the GDB&nbsp;can look like:</p>
<p>Loading section .text, size 0x6019c lma 0x62000000<br>
Start address 0x62000040, load size 393628<br>
Transfer rate: 93 KB/sec, 2008 bytes/write.</p>
<p>In this example a speed of 93 KB/sec was reached. The hardware which was used for the test can be found <a href="http://www.yagarto.de/projects/str7usbmsd/index.html" target="new">here</a>.</p>
<p>The test was made on Windows XP Prof. (SP2) with a JTAGkey and the original FTDI driver.</p>
<hr>
<h1>speed2 - Download speed test<a id="speed2" name="speed2"></a></h1>
<p>For this test a STR710 with external memory was used. The example project can be found under examples/STR710JtagSpeed. Here Eclipse or the arm-elf-gdb can be used to download the test.elf file into the RAM. The result of the GDB&nbsp;can look like:</p>
<p>Loading section .text, size 0x6019c lma 0x62000000<br>
Start address 0x62000040, load size 393628<br>Transfer rate: 52 KB/sec, 2008 bytes/write.</p>
<p>In this example a speed of 52 KB/sec was reached. The hardware which was used for the test can be found <a href="http://www.yagarto.de/projects/str7usbmsd/index.html" target="new">here</a>.</p>
<p>The test was made on Mac OS X (10.5.2, Intel) with a JTAGkey and the following driver:</p>
<p>- libftdi 0.10<br>
- libusb 0.1.12</p>
<p></p>
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