Add tcl configurations for Altera Soc devices

This commit adds two tcl configuration files, one for the Altera
Cyclone V SoC series, and one for the SoCkit development board.
The board configuration is able to halt and resume the cpu cores,
and dump register contents etc.  It has not been fully tested, however.

Change-Id: Id3f18c3408975cf986a5f5aec410b5b13240c35e
Signed-off-by: Brad Riensche <brad.riensche@gmail.com>
Reviewed-on: http://openocd.zylin.com/1494
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>

tcl/board/altera_sockit.cfg

@@ -0,0 +1,19 @@
+#
+# Cyclone V SocKit board
+# http://www.altera.com/b/arrow-sockit.html
+#
+# Software support page:
+# http://www.rocketboards.org/
+
+# openocd does not currently support the on-board USB Blaster II.
+# Install the JTAG header and use a USB Blaster instead.
+interface usb_blaster
+
+source [find target/altera_fpgasoc.cfg]
+
+# If the USB Blaster II were supported, these settings would be needed
+#usb_blaster_vid_pid 0x6810 0x09fb
+#usb_blaster_device_desc "USB-Blaster II"
+
+adapter_khz 100
+

tcl/target/altera_fpgasoc.cfg

@@ -0,0 +1,64 @@
+#
+# Altera cyclone V SoC family, 5Cxxx
+#
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME fpgasoc
+}
+
+# CoreSight Debug Access Port
+if { [info exists DAP_TAPID] } {
+        set _DAP_TAPID $DAP_TAPID
+} else {
+        set _DAP_TAPID 0x4ba00477
+}
+
+jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x01 -irmask 0x0f \
+        -expected-id $_DAP_TAPID
+
+# Subsidiary TAP: fpga
+if { [info exists FPGA_TAPID] } {
+   set _FPGA_TAPID $FPGA_TAPID
+} else {
+   set _FPGA_TAPID 0x02d020dd
+}
+jtag newtap $_CHIPNAME.fpga tap -irlen 10 -ircapture 0x01 -irmask 0x3 -expected-id $_FPGA_TAPID
+
+
+#
+# Cortex A9 target
+#
+
+# GDB target: Cortex-A9, using DAP, configuring only one core
+# Base addresses of cores:
+# core 0  -  0x80110000
+# core 1  -  0x80112000
+
+# Slow speed to be sure it will work
+jtag_rclk 1000
+
+set _TARGETNAME1 $_CHIPNAME.cpu.0
+set _TARGETNAME2 $_CHIPNAME.cpu.1
+
+# A9 core 0
+target create $_TARGETNAME1 cortex_a -chain-position $_CHIPNAME.dap \
+        -coreid 0 -dbgbase 0x80110000
+
+$_TARGETNAME1 configure -event reset-start { jtag_rclk 1000 }
+$_TARGETNAME1 configure -event reset-assert-post "cycv_dbginit $_TARGETNAME1"
+$_TARGETNAME1 configure -event gdb-attach { halt }
+
+
+# A9 core 1
+#target create $_TARGETNAME2 cortex_a -chain-position $_CHIPNAME.dap \
+#        -coreid 1 -dbgbase 0x80112000
+
+#$_TARGETNAME2 configure -event reset-start { jtag_rclk 1000 }
+#$_TARGETNAME2 configure -event reset-assert-post "cycv_dbginit $_TARGETNAME2"
+#$_TARGETNAME2 configure -event gdb-attach { halt }
+
+proc cycv_dbginit {target} {
+        # General Cortex A8/A9 debug initialisation
+        cortex_a8 dbginit
+}