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target/arm_adi_v5: sync CSW and TAR cache on apreg write 

When using apreg to change AP registers CSW or TAR we get internal
cached value not valid anymore.

Reuse the setup functions for CSW and TAR to write them.
Invalidate the cached value before the call to force the write, thus
keeping original apreg behaviour.

Change-Id: Ib14fafd5e584345de94f2e983de55406c588ac1c
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/4565
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
bscan_tunnel
Antonio Borneo 2018-06-15 16:30:41 +02:00 committed by Tomas Vanek
parent 4301ad83db
commit 0057c71ab6
1 changed files with 16 additions and 2 deletions
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18
src/target/arm_adi_v5.c
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@ -1722,6 +1722,7 @@ COMMAND_HANDLER(dap_apreg_command)
{
struct adiv5_dap *dap = adiv5_get_dap(CMD_DATA);
uint32_t apsel, reg, value;
struct adiv5_ap *ap;
int retval;
if (CMD_ARGC < 2 || CMD_ARGC > 3)
@ -1731,6 +1732,7 @@ COMMAND_HANDLER(dap_apreg_command)
/* AP address is in bits 31:24 of DP_SELECT */
if (apsel >= 256)
return ERROR_COMMAND_SYNTAX_ERROR;
ap = dap_ap(dap, apsel);
COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], reg);
if (reg >= 256 || (reg & 3))
@ -1738,9 +1740,21 @@ COMMAND_HANDLER(dap_apreg_command)
if (CMD_ARGC == 3) {
COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], value);
retval = dap_queue_ap_write(dap_ap(dap, apsel), reg, value);
switch (reg) {
case MEM_AP_REG_CSW:
ap->csw_default = 0; /* invalid, force write */
retval = mem_ap_setup_csw(ap, value);
break;
case MEM_AP_REG_TAR:
ap->tar_valid = false; /* invalid, force write */
retval = mem_ap_setup_tar(ap, value);
break;
default:
retval = dap_queue_ap_write(ap, reg, value);
break;
}
} else {
retval = dap_queue_ap_read(dap_ap(dap, apsel), reg, &value);
retval = dap_queue_ap_read(ap, reg, &value);
}
if (retval == ERROR_OK)
retval = dap_run(dap);