2014-06-04 07:49:58 +00:00
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# MB9BF506
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2011-07-27 09:56:25 +00:00
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# Fujitsu Cortex-M3 with 512kB Flash and 64kB RAM
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2013-09-28 10:23:15 +00:00
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source [find target/swj-dp.tcl]
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2011-07-27 09:56:25 +00:00
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if { [info exists CHIPNAME] } {
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2011-10-29 21:32:17 +00:00
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set _CHIPNAME $CHIPNAME
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2011-07-27 09:56:25 +00:00
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} else {
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2014-06-04 07:49:58 +00:00
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set _CHIPNAME mb9bfxx6
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2011-07-27 09:56:25 +00:00
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}
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if { [info exists ENDIAN] } {
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2011-10-29 21:32:17 +00:00
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set _ENDIAN $ENDIAN
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2011-07-27 09:56:25 +00:00
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} else {
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2011-10-29 21:32:17 +00:00
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set _ENDIAN little
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2011-07-27 09:56:25 +00:00
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}
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2011-10-29 21:32:17 +00:00
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if { [info exists CPUTAPID] } {
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2011-07-27 09:56:25 +00:00
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set _CPUTAPID $CPUTAPID
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} else {
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set _CPUTAPID 0x4ba00477
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}
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# delays on reset lines
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2012-03-26 13:41:39 +00:00
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adapter_nsrst_delay 100
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2013-09-28 10:23:15 +00:00
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if {[using_jtag]} {
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jtag_ntrst_delay 100
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}
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2011-07-27 09:56:25 +00:00
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2016-05-14 18:21:49 +00:00
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# Fujitsu Cortex-M3 reset configuration
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2011-07-27 09:56:25 +00:00
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reset_config trst_only
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2013-09-28 10:23:15 +00:00
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swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
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2018-03-23 20:17:29 +00:00
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dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
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2011-07-27 09:56:25 +00:00
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set _TARGETNAME $_CHIPNAME.cpu
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2018-03-23 20:17:29 +00:00
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target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
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2011-07-27 09:56:25 +00:00
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# MB9BF506 has 64kB of SRAM on its main system bus
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$_TARGETNAME configure -work-area-phys 0x1FFF8000 -work-area-size 0x10000 -work-area-backup 0
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# MB9BF506 has 512kB internal FLASH
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set _FLASHNAME $_CHIPNAME.flash
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flash bank $_FLASHNAME fm3 0 0 0 0 $_TARGETNAME
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# 4MHz / 6 = 666kHz, so use 500
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adapter_khz 500
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2013-09-28 10:23:15 +00:00
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if {![using_hla]} {
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# if srst is not fitted use SYSRESETREQ to
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# perform a soft reset
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cortex_m reset_config sysresetreq
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}
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