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tinyriscv-openocd/contrib/loaders/checksum/Makefile

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armv7m: Integrate build of checksum code Add rules to build armv7m_crc.inc and include it via preprocessor. Change-Id: I4482c7acb8454de28bdf210d9f06c0720ada490a Signed-off-by: Andreas Färber <afaerber@suse.de> Reviewed-on: http://openocd.zylin.com/3474 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2016-05-08 18:41:51 +00:00
BIN2C = ../../../src/helper/bin2char.sh
ARM_CROSS_COMPILE ?= arm-none-eabi-
ARM_AS ?= $(ARM_CROSS_COMPILE)as
ARM_OBJCOPY ?= $(ARM_CROSS_COMPILE)objcopy
contrib/loaders: Enforce Little Endian ARM machine code arm-none-eabi target triplet defaults to Little Endian, and so far any submitted machine code snippets have been verified to be Little Endian. However a user might override [ARM_]CROSS_COMPILE with an armeb toolchain, potentially resulting in invalid machine code. Let's be safe and enforce Little Endian mode for assembler and compiler. Change-Id: I9cefe24689eaded25d60ffb1f254b254e8d76f9d Signed-off-by: Andreas Färber <afaerber@suse.de> Reviewed-on: http://openocd.zylin.com/3498 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2016-05-21 22:41:15 +00:00
ARM_AFLAGS = -EL
Improve block read and checksum speed (#381) * Cache program buffer writes. Speeds up flash program by 3%, flash verify by 2%. Change-Id: I19f8f44f560a1111fa8f4e4fc04ce6de3c94999a * Remove nop from batch reads. program @ 22.123 KiB/s, verify @ 47.654 KiB/s (up from program @ 20.287 KiB/s, verify @ 23.148 KiB/s originally). Change-Id: I7ee19d967b1080336b0088d20e1fc30828afd935 * Use "algorithm" to compute CRC on RISC-V targets. Use the C compiler to generate the algorithm code. It's better at assembly than I am. We need separate RV32 and RV64 binaries to handle shift instructions. I used the code from gdb (libiberty really) because it returns the correct result. I'm not sure if the table is worth it since we do have to save/download/restore more bytes now. riscv_run_algorithm() now properly saves and reads back all registers used for parameters. It also doesn't check final_pc if exit_point is 0. Using gdb means I don't know the exact address where the code will end. Small target.[ch] change to be able to run algorithms at 64-bit addresses. Flashing an arty board now: ``` wrote 2228224 bytes from file /media/sf_tnewsome/SiFive/arty_images/arty.E21TraceFPGAEvaluationConfig.mcs in 105.589180s (20.608 KiB/s) verified 2192012 bytes in 7.037476s (304.177 KiB/s) 9.87user 16.16system 1:53.16elapsed 23%CPU (0avgtext+0avgdata 24768maxresident)k ``` Change-Id: I6696bd4cda7c89ac5ccd21b2ff3aa1663d7d7190 * Clean up formatting. Change-Id: I7f2d792a2b9432a04209272abb00d8136ee01025
2019-06-19 17:56:37 +00:00
RISCV_CROSS_COMPILE ?= riscv64-unknown-elf-
RISCV_CC ?= $(RISCV_CROSS_COMPILE)gcc
RISCV_OBJCOPY ?= $(RISCV_CROSS_COMPILE)objcopy
Fix flashing HiFive Unleashed (#402) * Align algorithm stack to XLEN. This fixes algorithm timeout on RV64 targets. Also improve debug information in various places. Change-Id: Id3121f9c6e753c6a7e14da511e4de0587a6f7b4d * Compile 32-bit RISC-V algorithms for RV32E. Change-Id: I33a698c0c6ba540de29fa0459242c72a67b0cbaa * Remove debug code. Change-Id: I37c966ce0f2d1fe68cd6ae0724d19ae95ebaf51b * Dump start of gdb packets escaping non-printable. Change-Id: Ie5f36b5c9041bfc0e5aa9543f0afe2c4810c2915 * Propagate flash programming errors. Change-Id: I0c938ce7a1062bcc93426538cbc82424000f37b7 * Improve debug messaging. Change-Id: I47ac3518f3b241986c677824864102936100adf6 * Add debug output to flash image. This is helpful when you're debugging the flash algorithm itself, and a nop when running it through OpenOCD. Change-Id: Id44c6498c288872cc2cec79044116ac38198c572 * Make timeout depend on how much data is written. Change-Id: I819efa04cd6f6bd6664afd5c53cc7a8a5c84f54e * Fix issi erase commands. This is required to flash HiFive Unleashed. Change-Id: I33e4869d1d05ca8a1df6136bccf11afda61bfe10 * Fix running algorithm on multicore `-rtos riscv`. The bug was that poll() might change the currently selected hart, and in that case we'd access registers on that other hart after the algorithm is finished. Change-Id: I140431898285cf471b372139cef2378ab4879377 * Make fespi flash algorithm debugging optional. Also add a scheme that allows you to see the stack trace of where a failure occurred if debugging is enabled. Change-Id: Ia9a3a9a941ceba0f8ff6b47da5a8643e5f84b252
2019-09-09 19:01:17 +00:00
RISCV32_CFLAGS = -march=rv32e -mabi=ilp32e -nostdlib -nostartfiles -Os -fPIC
Improve block read and checksum speed (#381) * Cache program buffer writes. Speeds up flash program by 3%, flash verify by 2%. Change-Id: I19f8f44f560a1111fa8f4e4fc04ce6de3c94999a * Remove nop from batch reads. program @ 22.123 KiB/s, verify @ 47.654 KiB/s (up from program @ 20.287 KiB/s, verify @ 23.148 KiB/s originally). Change-Id: I7ee19d967b1080336b0088d20e1fc30828afd935 * Use "algorithm" to compute CRC on RISC-V targets. Use the C compiler to generate the algorithm code. It's better at assembly than I am. We need separate RV32 and RV64 binaries to handle shift instructions. I used the code from gdb (libiberty really) because it returns the correct result. I'm not sure if the table is worth it since we do have to save/download/restore more bytes now. riscv_run_algorithm() now properly saves and reads back all registers used for parameters. It also doesn't check final_pc if exit_point is 0. Using gdb means I don't know the exact address where the code will end. Small target.[ch] change to be able to run algorithms at 64-bit addresses. Flashing an arty board now: ``` wrote 2228224 bytes from file /media/sf_tnewsome/SiFive/arty_images/arty.E21TraceFPGAEvaluationConfig.mcs in 105.589180s (20.608 KiB/s) verified 2192012 bytes in 7.037476s (304.177 KiB/s) 9.87user 16.16system 1:53.16elapsed 23%CPU (0avgtext+0avgdata 24768maxresident)k ``` Change-Id: I6696bd4cda7c89ac5ccd21b2ff3aa1663d7d7190 * Clean up formatting. Change-Id: I7f2d792a2b9432a04209272abb00d8136ee01025
2019-06-19 17:56:37 +00:00
RISCV64_CFLAGS = -march=rv64i -mabi=lp64 -nostdlib -nostartfiles -Os -fPIC
all: arm riscv
armv4_5: Integrate build of checksum code Add rules to build armv4_5_crc.inc, and convert the code to target endianness the least intrusive way. Change-Id: I7452b2c7e679dae14f9cda5f89bc81c16fc12cad Signed-off-by: Andreas Färber <afaerber@suse.de> Reviewed-on: http://openocd.zylin.com/3473 Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Tested-by: jenkins
2016-05-08 18:12:12 +00:00
arm: armv4_5_crc.inc armv7m_crc.inc
Improve block read and checksum speed (#381) * Cache program buffer writes. Speeds up flash program by 3%, flash verify by 2%. Change-Id: I19f8f44f560a1111fa8f4e4fc04ce6de3c94999a * Remove nop from batch reads. program @ 22.123 KiB/s, verify @ 47.654 KiB/s (up from program @ 20.287 KiB/s, verify @ 23.148 KiB/s originally). Change-Id: I7ee19d967b1080336b0088d20e1fc30828afd935 * Use "algorithm" to compute CRC on RISC-V targets. Use the C compiler to generate the algorithm code. It's better at assembly than I am. We need separate RV32 and RV64 binaries to handle shift instructions. I used the code from gdb (libiberty really) because it returns the correct result. I'm not sure if the table is worth it since we do have to save/download/restore more bytes now. riscv_run_algorithm() now properly saves and reads back all registers used for parameters. It also doesn't check final_pc if exit_point is 0. Using gdb means I don't know the exact address where the code will end. Small target.[ch] change to be able to run algorithms at 64-bit addresses. Flashing an arty board now: ``` wrote 2228224 bytes from file /media/sf_tnewsome/SiFive/arty_images/arty.E21TraceFPGAEvaluationConfig.mcs in 105.589180s (20.608 KiB/s) verified 2192012 bytes in 7.037476s (304.177 KiB/s) 9.87user 16.16system 1:53.16elapsed 23%CPU (0avgtext+0avgdata 24768maxresident)k ``` Change-Id: I6696bd4cda7c89ac5ccd21b2ff3aa1663d7d7190 * Clean up formatting. Change-Id: I7f2d792a2b9432a04209272abb00d8136ee01025
2019-06-19 17:56:37 +00:00
riscv: riscv32_crc.inc riscv64_crc.inc
armv4_5: Integrate build of checksum code Add rules to build armv4_5_crc.inc, and convert the code to target endianness the least intrusive way. Change-Id: I7452b2c7e679dae14f9cda5f89bc81c16fc12cad Signed-off-by: Andreas Färber <afaerber@suse.de> Reviewed-on: http://openocd.zylin.com/3473 Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Tested-by: jenkins
2016-05-08 18:12:12 +00:00
armv4_5_%.elf: armv4_5_%.s
contrib/loaders: Enforce Little Endian ARM machine code arm-none-eabi target triplet defaults to Little Endian, and so far any submitted machine code snippets have been verified to be Little Endian. However a user might override [ARM_]CROSS_COMPILE with an armeb toolchain, potentially resulting in invalid machine code. Let's be safe and enforce Little Endian mode for assembler and compiler. Change-Id: I9cefe24689eaded25d60ffb1f254b254e8d76f9d Signed-off-by: Andreas Färber <afaerber@suse.de> Reviewed-on: http://openocd.zylin.com/3498 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2016-05-21 22:41:15 +00:00
$(ARM_AS) $(ARM_AFLAGS) $< -o $@
armv4_5: Integrate build of checksum code Add rules to build armv4_5_crc.inc, and convert the code to target endianness the least intrusive way. Change-Id: I7452b2c7e679dae14f9cda5f89bc81c16fc12cad Signed-off-by: Andreas Färber <afaerber@suse.de> Reviewed-on: http://openocd.zylin.com/3473 Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Tested-by: jenkins
2016-05-08 18:12:12 +00:00
armv4_5_%.bin: armv4_5_%.elf
$(ARM_OBJCOPY) -Obinary $< $@
armv7m: Integrate build of checksum code Add rules to build armv7m_crc.inc and include it via preprocessor. Change-Id: I4482c7acb8454de28bdf210d9f06c0720ada490a Signed-off-by: Andreas Färber <afaerber@suse.de> Reviewed-on: http://openocd.zylin.com/3474 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2016-05-08 18:41:51 +00:00
armv7m_%.elf: armv7m_%.s
contrib/loaders: Enforce Little Endian ARM machine code arm-none-eabi target triplet defaults to Little Endian, and so far any submitted machine code snippets have been verified to be Little Endian. However a user might override [ARM_]CROSS_COMPILE with an armeb toolchain, potentially resulting in invalid machine code. Let's be safe and enforce Little Endian mode for assembler and compiler. Change-Id: I9cefe24689eaded25d60ffb1f254b254e8d76f9d Signed-off-by: Andreas Färber <afaerber@suse.de> Reviewed-on: http://openocd.zylin.com/3498 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2016-05-21 22:41:15 +00:00
$(ARM_AS) $(ARM_AFLAGS) $< -o $@
armv7m: Integrate build of checksum code Add rules to build armv7m_crc.inc and include it via preprocessor. Change-Id: I4482c7acb8454de28bdf210d9f06c0720ada490a Signed-off-by: Andreas Färber <afaerber@suse.de> Reviewed-on: http://openocd.zylin.com/3474 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2016-05-08 18:41:51 +00:00
armv7m_%.bin: armv7m_%.elf
$(ARM_OBJCOPY) -Obinary $< $@
Improve block read and checksum speed (#381) * Cache program buffer writes. Speeds up flash program by 3%, flash verify by 2%. Change-Id: I19f8f44f560a1111fa8f4e4fc04ce6de3c94999a * Remove nop from batch reads. program @ 22.123 KiB/s, verify @ 47.654 KiB/s (up from program @ 20.287 KiB/s, verify @ 23.148 KiB/s originally). Change-Id: I7ee19d967b1080336b0088d20e1fc30828afd935 * Use "algorithm" to compute CRC on RISC-V targets. Use the C compiler to generate the algorithm code. It's better at assembly than I am. We need separate RV32 and RV64 binaries to handle shift instructions. I used the code from gdb (libiberty really) because it returns the correct result. I'm not sure if the table is worth it since we do have to save/download/restore more bytes now. riscv_run_algorithm() now properly saves and reads back all registers used for parameters. It also doesn't check final_pc if exit_point is 0. Using gdb means I don't know the exact address where the code will end. Small target.[ch] change to be able to run algorithms at 64-bit addresses. Flashing an arty board now: ``` wrote 2228224 bytes from file /media/sf_tnewsome/SiFive/arty_images/arty.E21TraceFPGAEvaluationConfig.mcs in 105.589180s (20.608 KiB/s) verified 2192012 bytes in 7.037476s (304.177 KiB/s) 9.87user 16.16system 1:53.16elapsed 23%CPU (0avgtext+0avgdata 24768maxresident)k ``` Change-Id: I6696bd4cda7c89ac5ccd21b2ff3aa1663d7d7190 * Clean up formatting. Change-Id: I7f2d792a2b9432a04209272abb00d8136ee01025
2019-06-19 17:56:37 +00:00
%.inc: %.bin
armv7m: Integrate build of checksum code Add rules to build armv7m_crc.inc and include it via preprocessor. Change-Id: I4482c7acb8454de28bdf210d9f06c0720ada490a Signed-off-by: Andreas Färber <afaerber@suse.de> Reviewed-on: http://openocd.zylin.com/3474 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2016-05-08 18:41:51 +00:00
$(BIN2C) < $< > $@
Improve block read and checksum speed (#381) * Cache program buffer writes. Speeds up flash program by 3%, flash verify by 2%. Change-Id: I19f8f44f560a1111fa8f4e4fc04ce6de3c94999a * Remove nop from batch reads. program @ 22.123 KiB/s, verify @ 47.654 KiB/s (up from program @ 20.287 KiB/s, verify @ 23.148 KiB/s originally). Change-Id: I7ee19d967b1080336b0088d20e1fc30828afd935 * Use "algorithm" to compute CRC on RISC-V targets. Use the C compiler to generate the algorithm code. It's better at assembly than I am. We need separate RV32 and RV64 binaries to handle shift instructions. I used the code from gdb (libiberty really) because it returns the correct result. I'm not sure if the table is worth it since we do have to save/download/restore more bytes now. riscv_run_algorithm() now properly saves and reads back all registers used for parameters. It also doesn't check final_pc if exit_point is 0. Using gdb means I don't know the exact address where the code will end. Small target.[ch] change to be able to run algorithms at 64-bit addresses. Flashing an arty board now: ``` wrote 2228224 bytes from file /media/sf_tnewsome/SiFive/arty_images/arty.E21TraceFPGAEvaluationConfig.mcs in 105.589180s (20.608 KiB/s) verified 2192012 bytes in 7.037476s (304.177 KiB/s) 9.87user 16.16system 1:53.16elapsed 23%CPU (0avgtext+0avgdata 24768maxresident)k ``` Change-Id: I6696bd4cda7c89ac5ccd21b2ff3aa1663d7d7190 * Clean up formatting. Change-Id: I7f2d792a2b9432a04209272abb00d8136ee01025
2019-06-19 17:56:37 +00:00
riscv32_%.elf: riscv_%.c
$(RISCV_CC) $(RISCV32_CFLAGS) $< -o $@
riscv64_%.elf: riscv_%.c
$(RISCV_CC) $(RISCV64_CFLAGS) $< -o $@
riscv%.bin: riscv%.elf
$(RISCV_OBJCOPY) -Obinary $< $@
armv7m: Integrate build of checksum code Add rules to build armv7m_crc.inc and include it via preprocessor. Change-Id: I4482c7acb8454de28bdf210d9f06c0720ada490a Signed-off-by: Andreas Färber <afaerber@suse.de> Reviewed-on: http://openocd.zylin.com/3474 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2016-05-08 18:41:51 +00:00
clean:
-rm -f *.elf *.bin *.inc