2010-12-16 14:33:16 +00:00
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################################################################################
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# Author: Michael Trensch (MTrensch@googlemail.com)
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################################################################################
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source [find target/hilscher_netx10.cfg]
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# Usually it is not needed to set srst_pulls_trst
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# but sometimes it does not work without it. If you encounter
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# problems try to line below
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# reset_config trst_and_srst srst_pulls_trst
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reset_config trst_and_srst
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2012-03-26 13:41:39 +00:00
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adapter_nsrst_delay 500
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2010-12-16 14:33:16 +00:00
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jtag_ntrst_delay 500
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$_TARGETNAME configure -work-area-virt 0x08000000 -work-area-phys 0x08000000 -work-area-size 0x4000 -work-area-backup 1
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# Par. Flash can only be accessed if DIP switch on the board is set in proper
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# position and init_sdrambus was called. Don't call these functions if the DIP
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# switch is in invalid position, as some outputs may collide. This is why this
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# function is not called automatically
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proc flash_init { } {
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puts "Configuring SRAM nCS0 for 90ns Par. Flash (x16)"
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mww 0x101C0100 0x01010008
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flash probe 0
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}
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proc mread32 {addr} {
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set value(0) 0
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mem2array value 32 $addr 1
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return $value(0)
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}
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proc init_clocks { } {
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puts "Enabling all clocks "
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set accesskey [mread32 0x101c0070]
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mww 0x101c0070 [expr $accesskey]
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mww 0x101c0028 0x00007511
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}
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proc init_sdrambus { } {
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puts "Initializing external SDRAM Bus 16 Bit "
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set accesskey [mread32 0x101c0070]
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mww 0x101c0070 [expr $accesskey]
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mww 0x101c0C40 0x00000050
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puts "Configuring SDRAM controller for K4S561632E (32MB) "
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mww 0x101C0140 0
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sleep 100
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#mww 0x101C0144 0x00a13262
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mww 0x101C0144 0x00a13251
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mww 0x101C0148 0x00000033
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mww 0x101C0140 0x030d0121
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}
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$_TARGETNAME configure -event reset-init {
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halt
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wait_halt 1000
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arm7_9 fast_memory_access enable
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arm7_9 dcc_downloads enable
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init_clocks
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# init_sdrambus
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puts ""
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puts "-------------------------------------------------"
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puts "Call 'init_clocks' to enable all clocks"
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puts "Call 'init_sdrambus' to enable external SDRAM bus"
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puts "-------------------------------------------------"
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}
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#####################
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# Flash configuration
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#####################
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#flash bank <name> <driver> <base> <size> <chip width> <bus width> <target#>
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#flash bank parflash cfi 0xC0000000 0x01000000 2 2 $_TARGETNAME
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init
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reset init
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