318 lines
12 KiB
Python
318 lines
12 KiB
Python
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#!/usr/bin/python3
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#
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# Copyright (C) 2015 Robert Jordens <jordens@gmail.com>
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#
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# This program is free software; you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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# the Free Software Foundation; either version 2 of the License, or
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# (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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from migen.fhdl.std import *
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from mibuild.generic_platform import *
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from mibuild.xilinx import XilinxPlatform
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from mibuild.xilinx.vivado import XilinxVivadoToolchain
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from mibuild.xilinx.ise import XilinxISEToolchain
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"""
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This migen script produces proxy bitstreams to allow programming SPI flashes
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behind FPGAs. JTAG signalling is connected directly to SPI signalling. CS_N is
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asserted when the JTAG IR contains the USER1 instruction and the state is
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SHIFT-DR.
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Xilinx bscan cells sample TDO on falling TCK and forward it.
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MISO requires sampling on rising CLK and leads to one cycle of latency.
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https://github.com/m-labs/migen
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"""
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class Spartan3(Module):
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macro = "BSCAN_SPARTAN3"
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def __init__(self, platform):
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self.clock_domains.cd_jtag = ClockDomain(reset_less=True)
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spi = platform.request("spiflash")
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shift = Signal()
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tdo = Signal()
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sel1 = Signal()
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self.comb += [
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self.cd_jtag.clk.eq(spi.clk),
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spi.cs_n.eq(~shift | ~sel1),
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]
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self.sync.jtag += tdo.eq(spi.miso)
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self.specials += Instance(self.macro,
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o_DRCK1=spi.clk, o_SHIFT=shift,
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o_TDI=spi.mosi, i_TDO1=tdo, i_TDO2=0,
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o_SEL1=sel1)
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class Spartan3A(Spartan3):
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macro = "BSCAN_SPARTAN3A"
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class Spartan6(Module):
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def __init__(self, platform):
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self.clock_domains.cd_jtag = ClockDomain(reset_less=True)
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spi = platform.request("spiflash")
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shift = Signal()
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tdo = Signal()
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sel = Signal()
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self.comb += self.cd_jtag.clk.eq(spi.clk), spi.cs_n.eq(~shift | ~sel)
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self.sync.jtag += tdo.eq(spi.miso)
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self.specials += Instance("BSCAN_SPARTAN6", p_JTAG_CHAIN=1,
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o_TCK=spi.clk, o_SHIFT=shift, o_SEL=sel,
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o_TDI=spi.mosi, i_TDO=tdo)
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class Series7(Module):
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def __init__(self, platform):
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self.clock_domains.cd_jtag = ClockDomain(reset_less=True)
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spi = platform.request("spiflash")
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clk = Signal()
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shift = Signal()
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tdo = Signal()
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sel = Signal()
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self.comb += self.cd_jtag.clk.eq(clk), spi.cs_n.eq(~shift | ~sel)
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self.sync.jtag += tdo.eq(spi.miso)
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self.specials += Instance("BSCANE2", p_JTAG_CHAIN=1,
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o_SHIFT=shift, o_TCK=clk, o_SEL=sel,
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o_TDI=spi.mosi, i_TDO=tdo)
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self.specials += Instance("STARTUPE2", i_CLK=0, i_GSR=0, i_GTS=0,
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i_KEYCLEARB=0, i_PACK=1, i_USRCCLKO=clk,
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i_USRCCLKTS=0, i_USRDONEO=1, i_USRDONETS=1)
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class XilinxBscanSpi(XilinxPlatform):
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pinouts = {
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# bitstreams are named by die, package does not matter, speed grade
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# should not matter.
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# cs_n, clk, mosi, miso, *pullups
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"xc3s100e": ("cp132",
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["M2", "N12", "N2", "N8"],
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"LVCMOS33", Spartan3),
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"xc3s1200e": ("fg320",
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["U3", "U16", "T4", "N10"],
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"LVCMOS33", Spartan3),
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"xc3s1400a": ("fg484",
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["Y4", "AA20", "AB14", "AB20"],
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"LVCMOS33", Spartan3A),
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"xc3s1400an": ("fgg484",
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["Y4", "AA20", "AB14", "AB20"],
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"LVCMOS33", Spartan3A),
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"xc3s1600e": ("fg320",
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["U3", "U16", "T4", "N10"],
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"LVCMOS33", Spartan3),
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"xc3s200a": ("fg320",
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["V3", "U16", "T11", "V16"],
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"LVCMOS33", Spartan3A),
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"xc3s200an": ("ftg256",
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["T2", "R14", "P10", "T14"],
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"LVCMOS33", Spartan3A),
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"xc3s250e": ("cp132",
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["M2", "N12", "N2", "N8"],
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"LVCMOS33", Spartan3),
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"xc3s400a": ("fg320",
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["V3", "U16", "T11", "V16"],
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"LVCMOS33", Spartan3A),
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"xc3s400an": ("fgg400",
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["Y2", "Y19", "W12", "W18"],
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"LVCMOS33", Spartan3A),
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"xc3s500e": ("cp132",
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["M2", "N12", "N2", "N8"],
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"LVCMOS33", Spartan3),
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"xc3s50a": ("ft256",
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["T2", "R14", "P10", "T14"],
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"LVCMOS33", Spartan3A),
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"xc3s50an": ("ftg256",
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["T2", "R14", "P10", "T14"],
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"LVCMOS33", Spartan3A),
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"xc3s700a": ("fg400",
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["Y2", "Y19", "W12", "W18"],
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"LVCMOS33", Spartan3A),
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"xc3s700an": ("fgg484",
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["Y4", "AA20", "AB14", "AB20"],
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"LVCMOS33", Spartan3A),
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"xc3sd1800a": ("cs484",
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["U7", "V17", "V13", "W17"],
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"LVCMOS33", Spartan3A),
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"xc3sd3400a": ("cs484",
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["U7", "V17", "V13", "W17"],
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"LVCMOS33", Spartan3A),
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"xc6slx100": ("csg484-2",
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["AB5", "W17", "AB17", "Y17", "V13", "W13"],
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"LVCMOS33", Spartan6),
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"xc6slx100t": ("csg484-2",
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["AB5", "W17", "AB17", "Y17", "V13", "W13"],
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"LVCMOS33", Spartan6),
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"xc6slx150": ("csg484-2",
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["AB5", "W17", "AB17", "Y17", "V13", "W13"],
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"LVCMOS33", Spartan6),
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"xc6slx150t": ("csg484-2",
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["AB5", "W17", "AB17", "Y17", "V13", "W13"],
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"LVCMOS33", Spartan6),
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"xc6slx16": ("cpg196-2",
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["P2", "N13", "P11", "N11", "N10", "P10"],
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"LVCMOS33", Spartan6),
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"xc6slx25": ("csg324-2",
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["V3", "R15", "T13", "R13", "T14", "V14"],
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"LVCMOS33", Spartan6),
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"xc6slx25t": ("csg324-2",
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["V3", "R15", "T13", "R13", "T14", "V14"],
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"LVCMOS33", Spartan6),
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"xc6slx45": ("csg324-2",
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["V3", "R15", "T13", "R13", "T14", "V14"],
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"LVCMOS33", Spartan6),
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"xc6slx45t": ("csg324-2",
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["V3", "R15", "T13", "R13", "T14", "V14"],
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"LVCMOS33", Spartan6),
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"xc6slx4": ("cpg196-2",
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["P2", "N13", "P11", "N11", "N10", "P10"],
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"LVCMOS33", Spartan6),
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"xc6slx4t": ("qg144-2",
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["P38", "P70", "P64", "P65", "P62", "P61"],
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"LVCMOS33", Spartan6),
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"xc6slx75": ("csg484-2",
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["AB5", "W17", "AB17", "Y17", "V13", "W13"],
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"LVCMOS33", Spartan6),
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"xc6slx75t": ("csg484-2",
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["AB5", "W17", "AB17", "Y17", "V13", "W13"],
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"LVCMOS33", Spartan6),
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"xc6slx9": ("cpg196-2",
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["P2", "N13", "P11", "N11", "N10", "P10"],
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"LVCMOS33", Spartan6),
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"xc6slx9t": ("qg144-2",
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["P38", "P70", "P64", "P65", "P62", "P61"],
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"LVCMOS33", Spartan6),
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"xc7a100t": ("csg324-1",
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["L13", None, "K17", "K18", "L14", "M14"],
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"LVCMOS25", Series7),
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"xc7a15t": ("cpg236-1",
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["K19", None, "D18", "D19", "G18", "F18"],
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"LVCMOS25", Series7),
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"xc7a200t": ("fbg484-1",
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["T19", None, "P22", "R22", "P21", "R21"],
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"LVCMOS25", Series7),
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"xc7a35t": ("cpg236-1",
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["K19", None, "D18", "D19", "G18", "F18"],
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"LVCMOS25", Series7),
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"xc7a50t": ("cpg236-1",
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["K19", None, "D18", "D19", "G18", "F18"],
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"LVCMOS25", Series7),
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"xc7a75t": ("csg324-1",
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["L13", None, "K17", "K18", "L14", "M14"],
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"LVCMOS25", Series7),
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"xc7k160t": ("fbg484-1",
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["L16", None, "H18", "H19", "G18", "F19"],
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"LVCMOS25", Series7),
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"xc7k325t": ("fbg676-1",
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["C23", None, "B24", "A25", "B22", "A22"],
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"LVCMOS25", Series7),
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"xc7k355t": ("ffg901-1",
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["V26", None, "R30", "T30", "R28", "T28"],
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"LVCMOS25", Series7),
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"xc7k410t": ("fbg676-1",
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["C23", None, "B24", "A25", "B22", "A22"],
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"LVCMOS25", Series7),
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"xc7k420t": ("ffg1156-1",
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["V30", None, "AA33", "AA34", "Y33", "Y34"],
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"LVCMOS25", Series7),
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"xc7k480t": ("ffg1156-1",
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["V30", None, "AA33", "AA34", "Y33", "Y34"],
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"LVCMOS25", Series7),
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"xc7k70t": ("fbg484-1",
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["L16", None, "H18", "H19", "G18", "F19"],
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"LVCMOS25", Series7),
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"xc7v2000t": ("fhg1761-1",
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["AL36", None, "AM36", "AN36", "AJ36", "AJ37"],
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"LVCMOS18", Series7),
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"xc7v585t": ("ffg1157-1",
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["AL33", None, "AN33", "AN34", "AK34", "AL34"],
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"LVCMOS18", Series7),
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"xc7vh580t": ("flg1155-1",
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["AL28", None, "AE28", "AF28", "AJ29", "AJ30"],
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"LVCMOS18", Series7),
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"xc7vh870t": ("flg1932-1",
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["V32", None, "T33", "R33", "U31", "T31"],
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"LVCMOS18", Series7),
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"xc7vx1140t": ("flg1926-1",
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["AK33", None, "AN34", "AN35", "AJ34", "AK34"],
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"LVCMOS18", Series7),
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"xc7vx330t": ("ffg1157-1",
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["AL33", None, "AN33", "AN34", "AK34", "AL34"],
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"LVCMOS18", Series7),
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"xc7vx415t": ("ffg1157-1",
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["AL33", None, "AN33", "AN34", "AK34", "AL34"],
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"LVCMOS18", Series7),
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"xc7vx485t": ("ffg1157-1",
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["AL33", None, "AN33", "AN34", "AK34", "AL34"],
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"LVCMOS18", Series7),
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"xc7vx550t": ("ffg1158-1",
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["C24", None, "A23", "A24", "B26", "A26"],
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"LVCMOS18", Series7),
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"xc7vx690t": ("ffg1157-1",
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["AL33", None, "AN33", "AN34", "AK34", "AL34"],
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"LVCMOS18", Series7),
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"xc7vx980t": ("ffg1926-1",
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["AK33", None, "AN34", "AN35", "AJ34", "AK34"],
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"LVCMOS18", Series7),
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}
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def __init__(self, device, pins, std):
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cs_n, clk, mosi, miso = pins[:4]
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io = ["spiflash", 0,
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Subsignal("cs_n", Pins(cs_n)),
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Subsignal("mosi", Pins(mosi)),
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Subsignal("miso", Pins(miso), Misc("PULLUP")),
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IOStandard(std),
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]
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if clk:
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io.append(Subsignal("clk", Pins(clk)))
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for i, p in enumerate(pins[4:]):
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io.append(Subsignal("pullup{}".format(i), Pins(p), Misc("PULLUP")))
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XilinxPlatform.__init__(self, device, [io])
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if isinstance(self.toolchain, XilinxVivadoToolchain):
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self.toolchain.bitstream_commands.append(
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"set_property BITSTREAM.GENERAL.COMPRESS True [current_design]"
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)
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elif isinstance(self.toolchain, XilinxISEToolchain):
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self.toolchain.bitgen_opt += " -g compress"
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@classmethod
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def make(cls, device, errors=False):
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pkg, pins, std, Top = cls.pinouts[device]
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platform = cls("{}-{}".format(device, pkg), pins, std)
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top = Top(platform)
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name = "bscan_spi_{}".format(device)
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dir = "build_{}".format(device)
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try:
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platform.build(top, build_name=name, build_dir=dir)
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except Exception as e:
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print("ERROR: build failed for {}: {}".format(device, e))
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if errors:
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raise
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if __name__ == "__main__":
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import argparse
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import multiprocessing
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p = argparse.ArgumentParser(description="build bscan_spi bitstreams "
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"for openocd jtagspi flash driver")
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p.add_argument("device", nargs="*",
|
||
|
|
default=sorted(list(XilinxBscanSpi.pinouts)),
|
||
|
|
help="build for these devices (default: %(default)s)")
|
||
|
|
p.add_argument("-p", "--parallel", default=1, type=int,
|
||
|
|
help="number of parallel builds (default: %(default)s)")
|
||
|
|
args = p.parse_args()
|
||
|
|
pool = multiprocessing.Pool(args.parallel)
|
||
|
|
pool.map(XilinxBscanSpi.make, args.device, chunksize=1)
|