2010-12-10 19:37:39 +00:00
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/***************************************************************************
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* Copyright (C) 2005, 2007 by Dominic Rath *
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* Dominic.Rath@gmx.de *
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* Copyright (C) 2010 Spencer Oliver *
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* spen@spen-soft.co.uk *
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* *
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* This program is free software; you can redistribute it and/or modify *
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* it under the terms of the GNU General Public License as published by *
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* the Free Software Foundation; either version 2 of the License, or *
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* (at your option) any later version. *
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* *
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* This program is distributed in the hope that it will be useful, *
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* but WITHOUT ANY WARRANTY; without even the implied warranty of *
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
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* GNU General Public License for more details. *
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* *
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* You should have received a copy of the GNU General Public License *
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* along with this program; if not, write to the *
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* Free Software Foundation, Inc., *
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2013-06-02 19:32:36 +00:00
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
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2010-12-10 19:37:39 +00:00
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***************************************************************************/
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.text
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.arm
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.arch armv4
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.section .init
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/* algorithm register usage:
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* r0: source address (in RAM)
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* r1: target address (in Flash)
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* r2: count
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* r3: flash write command
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* r4: status byte (returned to host)
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* r5: busy test pattern
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* r6: error test pattern
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*/
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loop:
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ldrb r4, [r0], #1
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strb r3, [r1]
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strb r4, [r1]
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busy:
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ldrb r4, [r1]
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and r7, r4, r5
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cmp r7, r5
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bne busy
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tst r4, r6
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bne done
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subs r2, r2, #1
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beq done
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add r1, r1, #1
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b loop
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done:
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b done
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.end
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