2009-05-14 21:55:56 +00:00
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# The Linuxstamp-mx27 is board has a single IMX27 chip
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# For further info see http://opencircuits.com/Linuxstamp_mx27#OpenOCD
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source [find target/imx27.cfg]
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$_TARGETNAME configure -event gdb-attach { reset init }
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$_TARGETNAME configure -event reset-init { imx27lnst_init }
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proc imx27lnst_init { } {
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# This setup puts RAM at 0xA0000000
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# reset the board correctly
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2010-03-15 15:37:43 +00:00
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adapter_khz 500
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2009-05-14 21:55:56 +00:00
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reset run
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reset halt
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mww 0x10000000 0x20040304
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mww 0x10020000 0x00000000
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mww 0x10000004 0xDFFBFCFB
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mww 0x10020004 0xFFFFFFFF
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sleep 100
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# ========================================
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# Configure DDR on CSD0 -- initial reset
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# ========================================
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2009-09-21 18:48:22 +00:00
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mww 0xD8001010 0x00000008
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2009-05-14 21:55:56 +00:00
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sleep 100
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# ========================================
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2009-09-21 18:48:22 +00:00
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# Configure DDR on CSD0 -- wait 5000 cycle
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2009-05-14 21:55:56 +00:00
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# ========================================
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2009-09-21 18:48:22 +00:00
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mww 0x10027828 0x55555555
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mww 0x10027830 0x55555555
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mww 0x10027834 0x55555555
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mww 0x10027838 0x00005005
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mww 0x1002783C 0x15555555
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2009-05-14 21:55:56 +00:00
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2009-09-21 18:48:22 +00:00
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mww 0xD8001010 0x00000004
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2009-05-14 21:55:56 +00:00
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2009-09-21 18:48:22 +00:00
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mww 0xD8001004 0x00795729
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2009-05-14 21:55:56 +00:00
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#mww 0xD8001000 0x92200000
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mww 0xD8001000 0x91120000
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mww 0xA0000F00 0x0
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2009-09-21 18:48:22 +00:00
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#mww 0xD8001000 0xA2200000
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2009-05-14 21:55:56 +00:00
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mww 0xD8001000 0xA1120000
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mww 0xA0000F00 0x0
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mww 0xA0000F00 0x0
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2009-09-21 18:48:22 +00:00
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#mww 0xD8001000 0xB2200000
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2009-05-14 21:55:56 +00:00
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mww 0xD8001000 0xB1120000
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mwb 0xA0000033 0xFF
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mwb 0xA1000000 0xAA
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2009-09-21 18:48:22 +00:00
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#mww 0xD8001000 0x82228085
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2009-05-14 21:55:56 +00:00
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mww 0xD8001000 0x81128080
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}
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