65 lines
1.6 KiB
INI
65 lines
1.6 KiB
INI
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#
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# Altera cyclone V SoC family, 5Cxxx
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#
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if { [info exists CHIPNAME] } {
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set _CHIPNAME $CHIPNAME
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} else {
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set _CHIPNAME fpgasoc
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}
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# CoreSight Debug Access Port
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if { [info exists DAP_TAPID] } {
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set _DAP_TAPID $DAP_TAPID
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} else {
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set _DAP_TAPID 0x4ba00477
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}
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jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x01 -irmask 0x0f \
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-expected-id $_DAP_TAPID
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# Subsidiary TAP: fpga
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if { [info exists FPGA_TAPID] } {
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set _FPGA_TAPID $FPGA_TAPID
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} else {
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set _FPGA_TAPID 0x02d020dd
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}
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jtag newtap $_CHIPNAME.fpga tap -irlen 10 -ircapture 0x01 -irmask 0x3 -expected-id $_FPGA_TAPID
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#
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# Cortex A9 target
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#
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# GDB target: Cortex-A9, using DAP, configuring only one core
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# Base addresses of cores:
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# core 0 - 0x80110000
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# core 1 - 0x80112000
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# Slow speed to be sure it will work
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jtag_rclk 1000
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set _TARGETNAME1 $_CHIPNAME.cpu.0
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set _TARGETNAME2 $_CHIPNAME.cpu.1
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# A9 core 0
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target create $_TARGETNAME1 cortex_a -chain-position $_CHIPNAME.dap \
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-coreid 0 -dbgbase 0x80110000
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$_TARGETNAME1 configure -event reset-start { jtag_rclk 1000 }
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$_TARGETNAME1 configure -event reset-assert-post "cycv_dbginit $_TARGETNAME1"
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$_TARGETNAME1 configure -event gdb-attach { halt }
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# A9 core 1
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#target create $_TARGETNAME2 cortex_a -chain-position $_CHIPNAME.dap \
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# -coreid 1 -dbgbase 0x80112000
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#$_TARGETNAME2 configure -event reset-start { jtag_rclk 1000 }
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#$_TARGETNAME2 configure -event reset-assert-post "cycv_dbginit $_TARGETNAME2"
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#$_TARGETNAME2 configure -event gdb-attach { halt }
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proc cycv_dbginit {target} {
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# General Cortex A8/A9 debug initialisation
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cortex_a8 dbginit
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}
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