72 lines
1.9 KiB
INI
72 lines
1.9 KiB
INI
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#
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# Configuration script for Arm CoreLink SSE-200 Subsystem based IoT SoCs.
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#
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global TARGET
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set TARGET $_CHIPNAME
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swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
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dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
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#
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# SRAM on ARM CoreLink SSE-200 can be 4 banks of 8/16/32/64 KB
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# We will configure work area assuming 8-KB bank size in SRAM bank 1.
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# Also SRAM start addresses defaults to secure mode alias.
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# These values can be overridden as per board configuration
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#
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global _WORKAREASIZE_CPU0
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if { [info exists WORKAREASIZE_CPU0] } {
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set _WORKAREASIZE_CPU0 $WORKAREASIZE_CPU0
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} else {
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set _WORKAREASIZE_CPU0 0x1000
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}
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global _WORKAREAADDR_CPU0
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if { [info exists WORKAREAADDR_CPU0] } {
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set _WORKAREAADDR_CPU0 $WORKAREAADDR_CPU0
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} else {
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set _WORKAREAADDR_CPU0 0x30008000
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}
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#
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# Target configuration for Cortex M33 Core 0 on ARM CoreLink SSE-200
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# Core 0 is the boot core and will always be configured.
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#
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target create ${TARGET}.CPU0 cortex_m -dap $_CHIPNAME.dap -ap-num 1 -coreid 0
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${TARGET}.CPU0 configure -work-area-phys $_WORKAREAADDR_CPU0 -work-area-size $_WORKAREASIZE_CPU0 -work-area-backup 0
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${TARGET}.CPU0 cortex_m reset_config sysresetreq
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#
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# Target configuration for Cortex M33 Core 1 on ARM CoreLink SSE-200
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# Core 1 is optional and locked at boot until core 0 unlocks it.
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#
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if { $_ENABLE_CPU1 } {
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global _WORKAREASIZE_CPU1
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if { [info exists WORKAREASIZE_CPU1] } {
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set _WORKAREASIZE_CPU1 $WORKAREASIZE_CPU1
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} else {
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set _WORKAREASIZE_CPU1 0x1000
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}
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global _WORKAREAADDR_CPU1
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if { [info exists WORKAREAADDR_CPU1] } {
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set _WORKAREAADDR_CPU1 $WORKAREAADDR_CPU1
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} else {
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set _WORKAREAADDR_CPU1 0x30009000
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}
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target create ${TARGET}.CPU1 cortex_m -dap $_CHIPNAME.dap -ap-num 2 -coreid 1
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${TARGET}.CPU1 configure -work-area-phys $_WORKAREAADDR_CPU1 -work-area-size $_WORKAREASIZE_CPU1 -work-area-backup 0
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${TARGET}.CPU1 cortex_m reset_config vectreset
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}
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# Make sure the default target is the boot core
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targets ${TARGET}.CPU0
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