182 lines
3.6 KiB
INI
182 lines
3.6 KiB
INI
|
# Board configuration file for Amazon Kindle Model No. D00701 and D00801
|
||
|
|
# AKA Kindle 2nd generation and Kindle DX
|
||
|
|
# using a Freescale MCIMX31LDVKN5D i.MX31 processor
|
||
|
|
#
|
||
|
|
# Pins at J9 40-Pin FFC-A:
|
||
|
|
# 1 - GND
|
||
|
|
# 16 - TRSTB
|
||
|
|
# 17 - TDI
|
||
|
|
# 18 - TMS
|
||
|
|
# 19 - TCK
|
||
|
|
# 20 - RTCK
|
||
|
|
# 21 - TDO
|
||
|
|
# 22 - DE
|
||
|
|
# 25 - BOOT_MODE4
|
||
|
|
# 27 - BOOT_MODE2
|
||
|
|
|
||
|
|
source [find target/imx31.cfg]
|
||
|
|
source [find target/imx.cfg]
|
||
|
|
|
||
|
|
$_TARGETNAME configure -event reset-init { kindle2_init }
|
||
|
|
$_TARGETNAME configure -event reset-start { adapter_khz 1000 }
|
||
|
|
|
||
|
|
# 8MiB NOR Flash
|
||
|
|
set _FLASHNAME $_CHIPNAME.flash
|
||
|
|
flash bank $_FLASHNAME cfi 0xa0000000 0x800000 2 2 $_TARGETNAME
|
||
|
|
|
||
|
|
# 16kiB internal SRAM
|
||
|
|
$_TARGETNAME configure -work-area-phys 0x1fffc000 \
|
||
|
|
-work-area-size 0x4000 -work-area-backup 0
|
||
|
|
|
||
|
|
# FIXME: currently SRST is not wired to the system
|
||
|
|
reset_config trst_only
|
||
|
|
jtag_ntrst_assert_width 10
|
||
|
|
jtag_ntrst_delay 30
|
||
|
|
|
||
|
|
# this is broken but enabled by default
|
||
|
|
arm11 memwrite burst disable
|
||
|
|
|
||
|
|
adapter_khz 1000
|
||
|
|
ftdi_tdo_sample_edge falling
|
||
|
|
|
||
|
|
proc kindle2_init {} {
|
||
|
|
imx3x_reset
|
||
|
|
kindle2_clock_setup
|
||
|
|
disable_mmu_and_cache
|
||
|
|
kindle2_misc_init
|
||
|
|
kindle2_sdram_init
|
||
|
|
arm core_state arm
|
||
|
|
}
|
||
|
|
|
||
|
|
proc kindle2_clock_setup {} {
|
||
|
|
# CCMR: clock from FPM/CKIL
|
||
|
|
mww 0x53f80000 0x074b0b7b
|
||
|
|
# IPU_CONF
|
||
|
|
mww 0x53fc0000 0x040
|
||
|
|
# 398MHz
|
||
|
|
mww 0x53f80004 0xff871650
|
||
|
|
mww 0x53f80010 0x00331c23
|
||
|
|
}
|
||
|
|
|
||
|
|
proc kindle2_misc_init { } {
|
||
|
|
# AIPS1
|
||
|
|
mww 0x43f00040 0x0
|
||
|
|
mww 0x43f00044 0x0
|
||
|
|
mww 0x43f00048 0x0
|
||
|
|
mww 0x43f0004c 0x0
|
||
|
|
mww 0x43f00050 0x0
|
||
|
|
mww 0x43f00000 0x77777777
|
||
|
|
mww 0x43f00004 0x77777777
|
||
|
|
|
||
|
|
# AIPS2
|
||
|
|
mww 0x53f00040 0x0
|
||
|
|
mww 0x53f00044 0x0
|
||
|
|
mww 0x53f00048 0x0
|
||
|
|
mww 0x53f0004c 0x0
|
||
|
|
mww 0x53f00050 0x0
|
||
|
|
mww 0x53f00000 0x77777777
|
||
|
|
mww 0x53f00004 0x77777777
|
||
|
|
|
||
|
|
# Start 16 bit NorFlash Initialization on CS0
|
||
|
|
mww 0xb8002000 0x0000cc03
|
||
|
|
mww 0xb8002004 0xa0330d01
|
||
|
|
mww 0xb8002008 0x00220800
|
||
|
|
}
|
||
|
|
|
||
|
|
proc disable_mmu_and_cache {} {
|
||
|
|
# Mode Supervisor, disable FIQ, IRQ and imprecise data aborts
|
||
|
|
reg cpsr 0x1d3
|
||
|
|
|
||
|
|
# flush entire BTAC
|
||
|
|
arm mcr 15 0 7 5 6 0
|
||
|
|
# invalidate instruction and data cache
|
||
|
|
# MCR CP15, 0, R1, C7, C7, 0
|
||
|
|
arm mcr 15 0 7 7 0
|
||
|
|
|
||
|
|
# clean and invalidate cache
|
||
|
|
arm mcr 15 0 7 15 0
|
||
|
|
|
||
|
|
# disable MMU and caches
|
||
|
|
arm mcr 15 0 1 0 0 0
|
||
|
|
|
||
|
|
arm mcr 15 0 15 2 4 0
|
||
|
|
|
||
|
|
# invalidate TLBs
|
||
|
|
arm mcr 15 0 8 7 0 0
|
||
|
|
|
||
|
|
# Drain the write buffer
|
||
|
|
arm mcr 15 0 7 10 4 0
|
||
|
|
|
||
|
|
# start from AIPS 2GB region
|
||
|
|
arm mcr 15 0 15 2 4 0x40000015
|
||
|
|
}
|
||
|
|
|
||
|
|
proc kindle2_sdram_init {} {
|
||
|
|
#--------------------------------------------
|
||
|
|
# Samsung K4X1G323PC-8GC3 32Mx32 Mobile DDR SDRAM
|
||
|
|
#--------------------------------------------
|
||
|
|
# SDCLK
|
||
|
|
mww 0x43fac26c 0
|
||
|
|
|
||
|
|
# CAS
|
||
|
|
mww 0x43fac270 0
|
||
|
|
|
||
|
|
# RAS
|
||
|
|
mww 0x43fac274 0
|
||
|
|
|
||
|
|
# CS2 (CSD0)
|
||
|
|
mww 0x43fac27c 0x1000
|
||
|
|
|
||
|
|
# DQM3
|
||
|
|
mww 0x43fac284 0
|
||
|
|
|
||
|
|
# DQM2, DQM1, DQM0, SD31-SD0, A25-A0, MA10 (0x288..0x2dc)
|
||
|
|
mww 0x43fac288 0
|
||
|
|
mww 0x43fac28c 0
|
||
|
|
mww 0x43fac290 0
|
||
|
|
mww 0x43fac294 0
|
||
|
|
mww 0x43fac298 0
|
||
|
|
mww 0x43fac29c 0
|
||
|
|
mww 0x43fac2a0 0
|
||
|
|
mww 0x43fac2a4 0
|
||
|
|
mww 0x43fac2a8 0
|
||
|
|
mww 0x43fac2ac 0
|
||
|
|
mww 0x43fac2b0 0
|
||
|
|
mww 0x43fac2b4 0
|
||
|
|
mww 0x43fac2b8 0
|
||
|
|
mww 0x43fac2bc 0
|
||
|
|
mww 0x43fac2c0 0
|
||
|
|
mww 0x43fac2c4 0
|
||
|
|
mww 0x43fac2c8 0
|
||
|
|
mww 0x43fac2cc 0
|
||
|
|
mww 0x43fac2d0 0
|
||
|
|
mww 0x43fac2d4 0
|
||
|
|
mww 0x43fac2d8 0
|
||
|
|
mww 0x43fac2dc 0
|
||
|
|
|
||
|
|
# ?
|
||
|
|
mww 0xb8002000 0x00006602
|
||
|
|
mww 0xb8002004 0x00000501
|
||
|
|
mww 0xb8002008 0x00000000
|
||
|
|
|
||
|
|
# LPDDR1 Initialization script
|
||
|
|
mww 0xb8001010 0x00000002
|
||
|
|
mww 0xb8001010 0x00000004
|
||
|
|
# ESDCFG0: set timing paramters
|
||
|
|
mww 0xb8001004 0x007fff7f
|
||
|
|
# ESDCTL0: select Prechare-All mode
|
||
|
|
mww 0xb8001000 0x92100000
|
||
|
|
mww 0x80000f00 0x12344321
|
||
|
|
# ESDCTL0: Auto Refresh
|
||
|
|
mww 0xb8001000 0xa2100000
|
||
|
|
mww 0x80000000 0x12344321
|
||
|
|
mww 0x80000000 0x12344321
|
||
|
|
# ESDCTL0: Load Mode Register
|
||
|
|
mww 0xb8001000 0xb2100000
|
||
|
|
mwb 0x80000033 0xda
|
||
|
|
mwb 0x81000000 0xff
|
||
|
|
# ESDCTL0: enable Auto-Refresh
|
||
|
|
mww 0xb8001000 0x82226080
|
||
|
|
mww 0x80000000 0xdeadbeef
|
||
|
|
}
|