124 lines
5.2 KiB
C
124 lines
5.2 KiB
C
/*
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SPC5 HAL - Copyright (C) 2013 STMicroelectronics
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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/**
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* @file SPC560Dxx/spc560d_registry.h
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* @brief SPC560Dxx capabilities registry.
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*
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* @addtogroup HAL
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* @{
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*/
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#ifndef _SPC560D_REGISTRY_H_
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#define _SPC560D_REGISTRY_H_
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/*===========================================================================*/
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/* Platform capabilities. */
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/*===========================================================================*/
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/**
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* @name SPC560Dxx capabilities
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* @{
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*/
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/* DSPI attribures.*/
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#define SPC5_HAS_DSPI0 TRUE
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#define SPC5_HAS_DSPI1 TRUE
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#define SPC5_HAS_DSPI2 FALSE
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#define SPC5_HAS_DSPI3 FALSE
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#define SPC5_HAS_DSPI4 FALSE
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#define SPC5_DSPI_FIFO_DEPTH 4
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#define SPC5_DSPI0_PCTL 4
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#define SPC5_DSPI1_PCTL 5
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#define SPC5_DSPI0_TX1_DMA_CH_ID 4
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#define SPC5_DSPI0_TX2_DMA_CH_ID 5
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#define SPC5_DSPI0_RX_DMA_CH_ID 6
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#define SPC5_DSPI1_TX1_DMA_CH_ID 7
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#define SPC5_DSPI1_TX2_DMA_CH_ID 8
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#define SPC5_DSPI1_RX_DMA_CH_ID 9
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#define SPC5_DSPI0_TX1_DMA_DEV_ID 1
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#define SPC5_DSPI0_TX2_DMA_DEV_ID 0
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#define SPC5_DSPI0_RX_DMA_DEV_ID 2
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#define SPC5_DSPI1_TX1_DMA_DEV_ID 3
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#define SPC5_DSPI1_TX2_DMA_DEV_ID 0
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#define SPC5_DSPI1_RX_DMA_DEV_ID 4
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#define SPC5_DSPI0_TFFF_HANDLER vector76
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#define SPC5_DSPI0_TFFF_NUMBER 76
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#define SPC5_DSPI1_TFFF_HANDLER vector96
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#define SPC5_DSPI1_TFFF_NUMBER 96
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#define SPC5_DSPI0_ENABLE_CLOCK() \
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halSPCSetPeripheralClockMode(SPC5_DSPI0_PCTL, SPC5_SPI_DSPI0_START_PCTL)
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#define SPC5_DSPI0_DISABLE_CLOCK() \
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halSPCSetPeripheralClockMode(SPC5_DSPI0_PCTL, SPC5_SPI_DSPI0_STOP_PCTL)
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#define SPC5_DSPI1_ENABLE_CLOCK() \
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halSPCSetPeripheralClockMode(SPC5_DSPI1_PCTL, SPC5_SPI_DSPI1_START_PCTL)
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#define SPC5_DSPI1_DISABLE_CLOCK() \
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halSPCSetPeripheralClockMode(SPC5_DSPI1_PCTL, SPC5_SPI_DSPI1_STOP_PCTL)
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/* eDMA attributes.*/
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#define SPC5_HAS_EDMA TRUE
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#define SPC5_EDMA_NCHANNELS 16
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#define SPC5_EDMA_HAS_MUX TRUE
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#define SPC5_EDMA_MUX_PCTL 23
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/* LINFlex attributes.*/
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#define SPC5_HAS_LINFLEX0 TRUE
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#define SPC5_LINFLEX0_PCTL 48
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#define SPC5_LINFLEX0_RXI_HANDLER vector79
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#define SPC5_LINFLEX0_TXI_HANDLER vector80
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#define SPC5_LINFLEX0_ERR_HANDLER vector81
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#define SPC5_LINFLEX0_RXI_NUMBER 79
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#define SPC5_LINFLEX0_TXI_NUMBER 80
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#define SPC5_LINFLEX0_ERR_NUMBER 81
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#define SPC5_LINFLEX0_CLK (halSPCGetSystemClock() / \
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SPC5_PERIPHERAL1_CLK_DIV_VALUE)
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#define SPC5_HAS_LINFLEX1 TRUE
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#define SPC5_LINFLEX1_PCTL 49
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#define SPC5_LINFLEX1_RXI_HANDLER vector99
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#define SPC5_LINFLEX1_TXI_HANDLER vector100
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#define SPC5_LINFLEX1_ERR_HANDLER vector101
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#define SPC5_LINFLEX1_RXI_NUMBER 99
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#define SPC5_LINFLEX1_TXI_NUMBER 100
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#define SPC5_LINFLEX1_ERR_NUMBER 101
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#define SPC5_LINFLEX1_CLK (halSPCGetSystemClock() / \
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SPC5_PERIPHERAL1_CLK_DIV_VALUE)
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#define SPC5_HAS_LINFLEX2 TRUE
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#define SPC5_LINFLEX2_PCTL 50
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#define SPC5_LINFLEX2_RXI_HANDLER vector119
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#define SPC5_LINFLEX2_TXI_HANDLER vector120
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#define SPC5_LINFLEX2_ERR_HANDLER vector121
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#define SPC5_LINFLEX2_RXI_NUMBER 119
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#define SPC5_LINFLEX2_TXI_NUMBER 120
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#define SPC5_LINFLEX2_ERR_NUMBER 121
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#define SPC5_LINFLEX2_CLK (halSPCGetSystemClock() / \
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SPC5_PERIPHERAL1_CLK_DIV_VALUE)
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#define SPC5_HAS_LINFLEX3 FALSE
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/* SIUL attributes.*/
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#define SPC5_HAS_SIUL TRUE
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#define SPC5_SIUL_PCTL 68
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#define SPC5_SIUL_NUM_PORTS 8
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#define SPC5_SIUL_NUM_PCRS 77
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#define SPC5_SIUL_NUM_PADSELS 63
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#define SPC5_SIUL_SYSTEM_PINS 32,33
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/** @} */
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#endif /* _SPC560D_REGISTRY_H_ */
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/** @} */
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