291 lines
9.9 KiB
Plaintext
291 lines
9.9 KiB
Plaintext
/*
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ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
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2011 Giovanni Di Sirio.
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This file is part of ChibiOS/RT.
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ChibiOS/RT is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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ChibiOS/RT is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/**
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* @defgroup STM32L1xx_DRIVERS STM32L1xx Drivers
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* @details This section describes all the supported drivers on the STM32L1xx
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* platform and the implementation details of the single drivers.
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*
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* @ingroup platforms
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*/
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/**
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* @defgroup STM32L1xx_HAL STM32L1xx Initialization Support
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* @details The STM32L1xx HAL support is responsible for system initialization.
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*
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* @section stm32l1xx_hal_1 Supported HW resources
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* - PLL1.
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* - RCC.
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* - Flash.
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* .
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* @section stm32l1xx_hal_2 STM32L1xx HAL driver implementation features
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* - PLL startup and stabilization.
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* - Clock tree initialization.
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* - Clock source selection.
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* - Flash wait states initialization based on the selected clock options.
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* - SYSTICK initialization based on current clock and kernel required rate.
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* - DMA support initialization.
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* .
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* @ingroup STM32L1xx_DRIVERS
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*/
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/**
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* @defgroup STM32L1xx_ADC STM32L1xx ADC Support
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* @details The STM32L1xx ADC driver supports the ADC peripherals using DMA
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* channels for maximum performance.
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*
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* @section stm32l1xx_adc_1 Supported HW resources
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* - ADC1.
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* - DMA1.
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* .
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* @section stm32l1xx_adc_2 STM32L1xx ADC driver implementation features
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* - Clock stop for reduced power usage when the driver is in stop state.
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* - Streaming conversion using DMA for maximum performance.
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* - Programmable ADC interrupt priority level.
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* - Programmable DMA bus priority for each DMA channel.
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* - Programmable DMA interrupt priority for each DMA channel.
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* - DMA and ADC errors detection.
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* .
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* @ingroup STM32L1xx_DRIVERS
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*/
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/**
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* @defgroup STM32L1xx_DMA STM32L1xx DMA Support
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* @details This DMA helper driver is used by the other drivers in order to
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* access the shared DMA resources in a consistent way.
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*
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* @section stm32l1xx_dma_1 Supported HW resources
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* The DMA driver can support any of the following hardware resources:
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* - DMA1.
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* .
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* @section stm32l1xx_dma_2 STM32L1xx DMA driver implementation features
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* - Exports helper functions/macros to the other drivers that share the
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* DMA resource.
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* - Automatic DMA clock stop when not in use by any driver.
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* - DMA streams and interrupt vectors sharing among multiple drivers.
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* .
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* @ingroup STM32L1xx_DRIVERS
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*/
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/**
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* @defgroup STM32L1xx_EXT STM32L1xx EXT Support
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* @details The STM32L1xx EXT driver uses the EXTI peripheral.
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*
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* @section stm32l1xx_ext_1 Supported HW resources
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* - EXTI.
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* .
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* @section stm32l1xx_ext_2 STM32L1xx EXT driver implementation features
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* - Each EXTI channel can be independently enabled and programmed.
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* - Programmable EXTI interrupts priority level.
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* - Capability to work as event sources (WFE) rather than interrupt sources.
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* .
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* @ingroup STM32L1xx_DRIVERS
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*/
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/**
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* @defgroup STM32L1xx_GPT STM32L1xx GPT Support
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* @details The STM32L1xx GPT driver uses the TIMx peripherals.
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*
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* @section stm32l1xx_gpt_1 Supported HW resources
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* - TIM2.
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* - TIM3.
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* - TIM4.
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* .
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* @section stm32l1xx_gpt_2 STM32L1xx GPT driver implementation features
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* - Each timer can be independently enabled and programmed. Unused
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* peripherals are left in low power mode.
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* - Programmable TIMx interrupts priority level.
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* .
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* @ingroup STM32L1xx_DRIVERS
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*/
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/**
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* @defgroup STM32L1xx_ICU STM32L1xx ICU Support
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* @details The STM32L1xx ICU driver uses the TIMx peripherals.
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*
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* @section stm32l1xx_icu_1 Supported HW resources
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* - TIM2.
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* - TIM3.
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* - TIM4.
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* .
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* @section stm32l1xx_icu_2 STM32L1xx ICU driver implementation features
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* - Each timer can be independently enabled and programmed. Unused
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* peripherals are left in low power mode.
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* - Programmable TIMx interrupts priority level.
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* .
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* @ingroup STM32L1xx_DRIVERS
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*/
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/**
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* @defgroup STM32L1xx_PAL STM32L1xx PAL Support
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* @details The STM32L1xx PAL driver uses the GPIO peripherals.
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*
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* @section stm32l1xx_pal_1 Supported HW resources
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* - GPIOA.
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* - GPIOB.
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* - GPIOC.
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* - GPIOD.
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* - GPIOE.
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* - GPIOH.
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* .
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* @section stm32l1xx_pal_2 STM32L1xx PAL driver implementation features
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* The PAL driver implementation fully supports the following hardware
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* capabilities:
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* - 16 bits wide ports.
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* - Atomic set/reset functions.
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* - Atomic set+reset function (atomic bus operations).
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* - Output latched regardless of the pad setting.
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* - Direct read of input pads regardless of the pad setting.
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* .
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* @section stm32l1xx_pal_3 Supported PAL setup modes
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* The STM32L1xx PAL driver supports the following I/O modes:
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* - @p PAL_MODE_RESET.
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* - @p PAL_MODE_UNCONNECTED.
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* - @p PAL_MODE_INPUT.
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* - @p PAL_MODE_INPUT_PULLUP.
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* - @p PAL_MODE_INPUT_PULLDOWN.
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* - @p PAL_MODE_INPUT_ANALOG.
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* - @p PAL_MODE_OUTPUT_PUSHPULL.
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* - @p PAL_MODE_OUTPUT_OPENDRAIN.
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* - @p PAL_MODE_STM32L1xx_ALTERNATE_PUSHPULL (non standard).
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* - @p PAL_MODE_STM32L1xx_ALTERNATE_OPENDRAIN (non standard).
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* .
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* Any attempt to setup an invalid mode is ignored.
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*
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* @section stm32l1xx_pal_4 Suboptimal behavior
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* The STM32L1xx GPIO is less than optimal in several areas, the limitations
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* should be taken in account while using the PAL driver:
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* - Pad/port toggling operations are not atomic.
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* - Pad/group mode setup is not atomic.
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* .
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* @ingroup STM32L1xx_DRIVERS
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*/
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/**
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* @defgroup STM32L1xx_PWM STM32L1xx PWM Support
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* @details The STM32L1xx PWM driver uses the TIMx peripherals.
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*
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* @section stm32l1xx_pwm_1 Supported HW resources
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* - TIM1.
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* - TIM2.
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* - TIM3.
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* - TIM4.
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* - TIM5.
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* .
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* @section stm32l1xx_pwm_2 STM32L1xx PWM driver implementation features
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* - Each timer can be independently enabled and programmed. Unused
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* peripherals are left in low power mode.
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* - Four independent PWM channels per timer.
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* - Programmable TIMx interrupts priority level.
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* .
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* @ingroup STM32L1xx_DRIVERS
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*/
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/**
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* @defgroup STM32L1xx_SERIAL STM32L1xx Serial Support
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* @details The STM32L1xx Serial driver uses the USART/UART peripherals in a
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* buffered, interrupt driven, implementation.
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*
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* @section stm32l1xx_serial_1 Supported HW resources
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* The serial driver can support any of the following hardware resources:
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* - USART1.
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* - USART2.
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* - USART3 (where present).
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* - UART4 (where present).
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* - UART5 (where present).
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* .
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* @section stm32l1xx_serial_2 STM32L1xx Serial driver implementation features
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* - Clock stop for reduced power usage when the driver is in stop state.
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* - Each UART/USART can be independently enabled and programmed. Unused
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* peripherals are left in low power mode.
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* - Fully interrupt driven.
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* - Programmable priority levels for each UART/USART.
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* .
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* @ingroup STM32L1xx_DRIVERS
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*/
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/**
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* @defgroup STM32L1xx_SPI STM32L1xx SPI Support
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* @details The SPI driver supports the STM32L1xx SPI peripherals using DMA
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* channels for maximum performance.
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*
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* @section stm32l1xx_spi_1 Supported HW resources
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* - SPI1.
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* - SPI2.
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* - SPI3 (where present).
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* - DMA1.
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* - DMA2 (where present).
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* .
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* @section stm32l1xx_spi_2 STM32L1xx SPI driver implementation features
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* - Clock stop for reduced power usage when the driver is in stop state.
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* - Each SPI can be independently enabled and programmed. Unused
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* peripherals are left in low power mode.
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* - Programmable interrupt priority levels for each SPI.
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* - DMA is used for receiving and transmitting.
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* - Programmable DMA bus priority for each DMA channel.
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* - Programmable DMA interrupt priority for each DMA channel.
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* - Programmable DMA error hook.
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* .
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* @ingroup STM32L1xx_DRIVERS
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*/
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/**
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* @defgroup STM32L1xx_UART STM32L1xx UART Support
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* @details The UART driver supports the STM32L1xx USART peripherals using DMA
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* channels for maximum performance.
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*
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* @section stm32l1xx_uart_1 Supported HW resources
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* The UART driver can support any of the following hardware resources:
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* - USART1.
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* - USART2.
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* - USART3 (where present).
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* - UART4 (where present).
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* - DMA1.
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* - DMA2 (where present).
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* .
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* @section stm32l1xx_uart_2 STM32L1xx UART driver implementation features
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* - Clock stop for reduced power usage when the driver is in stop state.
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* - Each UART/USART can be independently enabled and programmed. Unused
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* peripherals are left in low power mode.
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* - Programmable interrupt priority levels for each UART/USART.
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* - DMA is used for receiving and transmitting.
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* - Programmable DMA bus priority for each DMA channel.
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* - Programmable DMA interrupt priority for each DMA channel.
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* - Programmable DMA error hook.
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* .
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* @ingroup STM32L1xx_DRIVERS
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*/
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/**
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* @defgroup STM32L1xx_USB STM32L1xx USB Support
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* @details The USB driver supports the STM32L1xx USB peripheral.
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*
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* @section stm32l1xx_usb_1 Supported HW resources
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* The USB driver can support any of the following hardware resources:
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* - USB.
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* .
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* @section stm32l1xx_usb_2 STM32L1xx USB driver implementation features
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* - Clock stop for reduced power usage when the driver is in stop state.
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* - Programmable interrupt priority levels.
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* - Each endpoint programmable in Control, Bulk and Interrupt modes.
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* .
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* @ingroup STM32L1xx_DRIVERS
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*/
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