328 lines
12 KiB
C
328 lines
12 KiB
C
/*
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ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
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2011 Giovanni Di Sirio.
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This file is part of ChibiOS/RT.
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ChibiOS/RT is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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ChibiOS/RT is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/**
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* @file DMAv2/stm32_dma.h
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* @brief Enhanced-DMA helper driver header.
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* @note This file requires definitions from the ST STM32F2xx header file
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* stm32f2xx.h.
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*
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* @addtogroup STM32_DMA
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* @{
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*/
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#ifndef _STM32_DMA_H_
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#define _STM32_DMA_H_
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/*===========================================================================*/
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/* Driver constants. */
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/*===========================================================================*/
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/**
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* @brief Total number of DMA streams.
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* @note This is the total number of streams among all the DMA units.
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*/
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#define STM32_DMA_STREAMS 16
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/**
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* @brief Mask of the ISR bits passed to the DMA callback functions.
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*/
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#define STM32_DMA_ISR_MASK 0x3D
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/**
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* @name DMA streams identifiers
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* @{
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*/
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#define STM32_DMA1_STREAM0 (&_stm32_dma_streams[0])
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#define STM32_DMA1_STREAM1 (&_stm32_dma_streams[1])
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#define STM32_DMA1_STREAM2 (&_stm32_dma_streams[2])
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#define STM32_DMA1_STREAM3 (&_stm32_dma_streams[3])
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#define STM32_DMA1_STREAM4 (&_stm32_dma_streams[4])
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#define STM32_DMA1_STREAM5 (&_stm32_dma_streams[5])
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#define STM32_DMA1_STREAM6 (&_stm32_dma_streams[6])
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#define STM32_DMA1_STREAM7 (&_stm32_dma_streams[7])
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#define STM32_DMA2_STREAM0 (&_stm32_dma_streams[8])
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#define STM32_DMA2_STREAM1 (&_stm32_dma_streams[9])
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#define STM32_DMA2_STREAM2 (&_stm32_dma_streams[10])
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#define STM32_DMA2_STREAM3 (&_stm32_dma_streams[11])
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#define STM32_DMA2_STREAM4 (&_stm32_dma_streams[12])
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#define STM32_DMA2_STREAM5 (&_stm32_dma_streams[13])
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#define STM32_DMA2_STREAM6 (&_stm32_dma_streams[14])
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#define STM32_DMA2_STREAM7 (&_stm32_dma_streams[15])
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/** @} */
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/**
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* @name CR register constants common to all DMA types
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*/
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#define STM32_DMA_CR_EN DMA_SxCR_EN
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#define STM32_DMA_CR_TEIE DMA_SxCR_TEIE
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#define STM32_DMA_CR_HTIE DMA_SxCR_HTIE
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#define STM32_DMA_CR_TCIE DMA_SxCR_TCIE
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#define STM32_DMA_CR_DIR_MASK DMA_SxCR_DIR
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#define STM32_DMA_CR_DIR_P2M 0
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#define STM32_DMA_CR_DIR_M2P DMA_SxCR_DIR_0
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#define STM32_DMA_CR_DIR_M2M DMA_SxCR_DIR_1
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#define STM32_DMA_CR_CIRC DMA_SxCR_CIRC
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#define STM32_DMA_CR_PINC DMA_SxCR_PINC
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#define STM32_DMA_CR_MINC DMA_SxCR_MINC
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#define STM32_DMA_CR_PSIZE_MASK DMA_SxCR_PSIZE
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#define STM32_DMA_CR_PSIZE_BYTE 0
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#define STM32_DMA_CR_PSIZE_HWORD DMA_SxCR_PSIZE_0
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#define STM32_DMA_CR_PSIZE_WORD DMA_SxCR_PSIZE_1
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#define STM32_DMA_CR_MSIZE_MASK DMA_SxCR_MSIZE
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#define STM32_DMA_CR_MSIZE_BYTE 0
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#define STM32_DMA_CR_MSIZE_HWORD DMA_SxCR_MSIZE_0
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#define STM32_DMA_CR_MSIZE_WORD DMA_SxCR_MSIZE_1
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#define STM32_DMA_CR_PL_MASK DMA_SxCR_PL
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#define STM32_DMA_CR_PL(n) ((n) << 16)
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/** @} */
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/**
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* @name CR register constants only found in STM32F2xx
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*/
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#define STM32_DMA_CR_DMEIE DMA_SxCR_DMEIE
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#define STM32_DMA_CR_PFCTRL DMA_SxCR_PFCTRL
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#define STM32_DMA_CR_PINCOS DMA_SxCR_PINCOS
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#define STM32_DMA_CR_DBM DMA_SxCR_DBM
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#define STM32_DMA_CR_CT DMA_SxCR_CT
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#define STM32_DMA_CR_PBURST_MASK DMA_SxCR_PBURST
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#define STM32_DMA_CR_PBURST_SINGLE 0
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#define STM32_DMA_CR_PBURST_INCR4 DMA_SxCR_PBURST_0
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#define STM32_DMA_CR_PBURST_INCR8 DMA_SxCR_PBURST_1
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#define STM32_DMA_CR_PBURST_INCR16 (DMA_SxCR_PBURST_0 | DMA_SxCR_PBURST_1)
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#define STM32_DMA_CR_MBURST_MASK DMA_SxCR_MBURST
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#define STM32_DMA_CR_MBURST_SINGLE 0
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#define STM32_DMA_CR_MBURST_INCR4 DMA_SxCR_MBURST_0
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#define STM32_DMA_CR_MBURST_INCR8 DMA_SxCR_MBURST_1
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#define STM32_DMA_CR_MBURST_INCR16 (DMA_SxCR_MBURST_0 | DMA_SxCR_MBURST_1)
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#define STM32_DMA_CR_CHSEL_MASK DMA_SxCR_CHSEL
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#define STM32_DMA_CR_CHSEL(n) ((n) << 25)
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/** @} */
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/**
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* @name FCR register constants only found in STM32F2xx
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*/
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#define STM32_DMA_FCR_FEIE DMA_SxFCR_FEIE
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#define STM32_DMA_FCR_FS_MASK DMA_SxFCR_FS
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#define STM32_DMA_FCR_DMDIS DMA_SxFCR_DMDIS
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#define STM32_DMA_FCR_FTH_MASK DMA_SxFCR_FTH
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#define STM32_DMA_FCR_FTH_1Q 0
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#define STM32_DMA_FCR_FTH_HALF DMA_SxFCR_FTH_0
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#define STM32_DMA_FCR_FTH_3Q DMA_SxFCR_FTH_1
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#define STM32_DMA_FCR_FTH_FULL (DMA_SxFCR_FTH_0 | DMA_SxFCR_FTH_1)
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/** @} */
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/**
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* @name Status flags passed to the ISR callbacks
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*/
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#define STM32_DMA_ISR_FEIF DMA_LISR_FEIF0
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#define STM32_DMA_ISR_DMEIF DMA_LISR_DMEIF0
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#define STM32_DMA_ISR_TEIF DMA_LISR_TEIF0
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#define STM32_DMA_ISR_HTIF DMA_LISR_HTIF0
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#define STM32_DMA_ISR_TCIF DMA_LISR_TCIF0
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/** @} */
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/*===========================================================================*/
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/* Driver pre-compile time settings. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Derived constants and error checks. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver data structures and types. */
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/*===========================================================================*/
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/**
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* @brief STM32 DMA stream descriptor structure.
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*/
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typedef struct {
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DMA_Channel_TypeDef *channel; /**< @brief Associated DMA channel. */
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volatile uint32_t *ifcr; /**< @brief Associated IFCR reg. */
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uint8_t ishift; /**< @brief Bits offset in xIFCR
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register. */
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uint8_t selfindex; /**< @brief Index to self in array. */
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uint8_t vector; /**< @brief Associated IRQ vector. */
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} stm32_dma_stream_t;
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/**
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* @brief STM32 DMA ISR function type.
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*
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* @param[in] p parameter for the registered function
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* @param[in] flags pre-shifted content of the xISR register, the bits
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* are aligned to bit zero
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*/
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typedef void (*stm32_dmaisr_t)(void *p, uint32_t flags);
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/*===========================================================================*/
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/* Driver macros. */
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/*===========================================================================*/
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/**
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* @brief Associates a peripheral data register to a DMA stream.
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* @note This function can be invoked in both ISR or thread context.
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*
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* @param[in] dmastp pointer to a stm32_dma_stream_t structure
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* @param[in] addr value to be written in the PAR register
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*
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* @special
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*/
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#define dmaStreamSetPeripheral(dmastp, addr) { \
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(dmastp)->stream->PAR = (uint32_t)(addr); \
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}
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/**
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* @brief Associates a memory destination to a DMA stream.
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* @note This function can be invoked in both ISR or thread context.
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*
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* @param[in] dmastp pointer to a stm32_dma_stream_t structure
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* @param[in] addr value to be written in the M0AR register
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*
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* @special
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*/
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#define dmaStreamSetMemory0(dmastp, addr) { \
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(dmastp)->stream->M0AR = (uint32_t)(addr); \
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}
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/**
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* @brief Associates an alternate memory destination to a DMA stream.
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* @note This function can be invoked in both ISR or thread context.
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*
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* @param[in] dmastp pointer to a stm32_dma_stream_t structure
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* @param[in] addr value to be written in the M1AR register
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*
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* @special
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*/
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#define dmaStreamSetMemory1(dmastp, addr) { \
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(dmastp)->stream->M1AR = (uint32_t)(addr); \
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}
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/**
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* @brief Sets the number of transfers to be performed.
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* @note This function can be invoked in both ISR or thread context.
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*
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* @param[in] dmastp pointer to a stm32_dma_stream_t structure
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* @param[in] size value to be written in the CNDTR register
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*
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* @special
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*/
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#define dmaStreamSetTransactionSize(dmastp, size) { \
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(dmastp)->stream->NDTR = (uint32_t)(size); \
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}
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/**
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* @brief Returns the number of transfers to be performed.
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* @note This function can be invoked in both ISR or thread context.
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*
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* @param[in] dmastp pointer to a stm32_dma_stream_t structure
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* @return The number of transfers to be performed.
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*
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* @special
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*/
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#define dmaStreamGetTransactionSize(dmastp) ((size_t)((dmastp)->stream->NDTR))
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/**
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* @brief Programs the stream mode settings.
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* @note This function can be invoked in both ISR or thread context.
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*
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* @param[in] dmastp pointer to a stm32_dma_stream_t structure
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* @param[in] mode value to be written in the CR register
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*
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* @special
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*/
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#define dmaStreamSetMode(dmastp, mode) { \
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(dmastp)->stream->CR = (uint32_t)(mode); \
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}
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/**
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* @brief Programs the stream FIFO settings.
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* @note This function can be invoked in both ISR or thread context.
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*
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* @param[in] dmastp pointer to a stm32_dma_stream_t structure
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* @param[in] mode value to be written in the FCR register
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*
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* @special
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*/
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#define dmaStreamSetFIFO(dmastp, mode) { \
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(dmastp)->stream->FCR = (uint32_t)(mode); \
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}
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/**
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* @brief DMA stream enable.
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* @note This function can be invoked in both ISR or thread context.
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*
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* @param[in] dmachp pointer to a stm32_dma_stream_t structure
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*
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* @special
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*/
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#define dmaStreamEnable(dmachp) { \
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(dmastp)->stream->CR |= STM32_DMA_CR_EN; \
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}
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/**
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* @brief DMA stream disable.
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* @note This function can be invoked in both ISR or thread context.
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*
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* @param[in] dmastp pointer to a stm32_dma_stream_t structure
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*
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* @special
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*/
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#define dmaStreamDisable(dmastp) { \
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(dmastp)->stream->CR &= ~STM32_DMA_CR_EN; \
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}
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/**
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* @brief DMA stream interrupt sources clear.
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* @note This function can be invoked in both ISR or thread context.
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*
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* @param[in] dmastp pointer to a stm32_dma_stream_t structure
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*
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* @special
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*/
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#define dmaStreamClearInterrupt(dmastp) { \
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*(dmastp)->ifcr = STM32_DMA_ISR_MASK << (dmastp)->ishift; \
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}
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/*===========================================================================*/
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/* External declarations. */
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/*===========================================================================*/
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#if !defined(__DOXYGEN__)
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extern const stm32_dma_stream_t _stm32_dma_streams[STM32_DMA_STREAMS];
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#endif
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#ifdef __cplusplus
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extern "C" {
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#endif
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void dmaInit(void);
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bool_t dmaStreamAllocate(const stm32_dma_stream_t *dmastp,
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uint32_t priority,
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stm32_dmaisr_t func,
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void *param);
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void dmaStreamRelease(const stm32_dma_stream_t *dmastp);
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#ifdef __cplusplus
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}
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#endif
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#endif /* _STM32_DMA_H_ */
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/** @} */
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