211 lines
6.1 KiB
C
211 lines
6.1 KiB
C
/*
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ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio.
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This file is part of ChibiOS/RT.
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ChibiOS/RT is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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ChibiOS/RT is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/**
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* @file STM32/spi_lld.h
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* @brief STM32 SPI subsystem low level driver header.
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* @addtogroup STM32_SPI
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* @{
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*/
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#ifndef _SPI_LLD_H_
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#define _SPI_LLD_H_
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#if CH_HAL_USE_SPI || defined(__DOXYGEN__)
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/*===========================================================================*/
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/* Driver pre-compile time settings. */
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/*===========================================================================*/
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/**
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* @brief SPI1 driver enable switch.
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* @details If set to @p TRUE the support for SPI1 is included.
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* @note The default is @p TRUE.
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*/
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#if !defined(USE_STM32_SPI1) || defined(__DOXYGEN__)
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#define USE_STM32_SPI1 TRUE
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#endif
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/**
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* @brief SPI2 driver enable switch.
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* @details If set to @p TRUE the support for SPI2 is included.
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* @note The default is @p TRUE.
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*/
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#if !defined(USE_STM32_SPI2) || defined(__DOXYGEN__)
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#define USE_STM32_SPI2 TRUE
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#endif
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/**
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* @brief SPI1 DMA priority (0..3|lowest..highest).
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* @note The priority level is used for both the TX and RX DMA channels but
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* because of the channels ordering the RX channel has always priority
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* over the TX channel.
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*/
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#if !defined(SPI1_DMA_PRIORITY) || defined(__DOXYGEN__)
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#define STM32_SPI1_DMA_PRIORITY 2
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#endif
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/**
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* @brief SPI2 DMA priority (0..3|lowest..highest).
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* @note The priority level is used for both the TX and RX DMA channels but
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* because of the channels ordering the RX channel has always priority
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* over the TX channel.
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*/
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#if !defined(SPI2_DMA_PRIORITY) || defined(__DOXYGEN__)
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#define STM32_SPI2_DMA_PRIORITY 2
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#endif
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/**
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* @brief SPI1 interrupt priority level setting.
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* @note @p BASEPRI_KERNEL >= @p STM32_SPI1_IRQ_PRIORITY > @p PRIORITY_PENDSV.
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*/
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#if !defined(STM32_SPI1_IRQ_PRIORITY) || defined(__DOXYGEN__)
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#define STM32_SPI1_IRQ_PRIORITY 0x60
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#endif
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/**
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* @brief SPI2 interrupt priority level setting.
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* @note @p BASEPRI_KERNEL >= @p STM32_SPI2_IRQ_PRIORITY > @p PRIORITY_PENDSV.
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*/
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#if !defined(STM32_SPI2_IRQ_PRIORITY) || defined(__DOXYGEN__)
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#define STM32_SPI2_IRQ_PRIORITY 0x60
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#endif
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/**
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* @brief SPI1 DMA error hook.
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* @note The default action for DMA errors is a system halt because DMA error
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* can only happen because programming errors.
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*/
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#if !defined(STM32_SPI1_DMA_ERROR_HOOK) || defined(__DOXYGEN__)
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#define STM32_SPI1_DMA_ERROR_HOOK() chSysHalt()
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#endif
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/**
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* @brief SPI2 DMA error hook.
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* @note The default action for DMA errors is a system halt because DMA error
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* can only happen because programming errors.
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*/
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#if !defined(STM32_SPI2_DMA_ERROR_HOOK) || defined(__DOXYGEN__)
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#define STM32_SPI2_DMA_ERROR_HOOK() chSysHalt()
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#endif
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/*===========================================================================*/
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/* Driver data structures and types. */
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/*===========================================================================*/
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/**
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* @brief Driver configuration structure.
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*/
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typedef struct {
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/**
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* @brief The chip select line port.
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*/
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ioportid_t spc_ssport;
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/**
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* @brief The chip select line pad number.
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*/
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uint16_t spc_sspad;
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/**
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* @brief SPI initialization data.
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*/
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uint16_t spc_cr1;
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} SPIConfig;
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/**
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* @brief Structure representing a SPI driver.
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*/
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typedef struct {
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/**
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* @brief Driver state.
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*/
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spistate_t spd_state;
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#if SPI_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__)
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#if CH_USE_MUTEXES || defined(__DOXYGEN__)
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/**
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* @brief Mutex protecting the bus.
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*/
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Mutex spd_mutex;
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#elif CH_USE_SEMAPHORES
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Semaphore spd_semaphore;
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#endif
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#endif /* SPI_USE_MUTUAL_EXCLUSION */
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/**
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* @brief Current configuration data.
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*/
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const SPIConfig *spd_config;
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/* End of the mandatory fields.*/
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/**
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* @brief Thread waiting for I/O completion.
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*/
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Thread *spd_thread;
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/**
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* @brief Pointer to the SPIx registers block.
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*/
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SPI_TypeDef *spd_spi;
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/**
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* @brief Pointer to the receive DMA channel registers block.
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*/
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DMA_Channel_TypeDef *spd_dmarx;
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/**
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* @brief Pointer to the transmit DMA channel registers block.
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*/
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DMA_Channel_TypeDef *spd_dmatx;
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/**
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* @brief DMA priority bit mask.
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*/
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uint32_t spd_dmaprio;
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} SPIDriver;
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/*===========================================================================*/
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/* External declarations. */
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/*===========================================================================*/
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/** @cond never*/
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#if USE_STM32_SPI1
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extern SPIDriver SPID1;
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#endif
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#if USE_STM32_SPI2
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extern SPIDriver SPID2;
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#endif
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#ifdef __cplusplus
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extern "C" {
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#endif
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void spi_lld_init(void);
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void spi_lld_start(SPIDriver *spip);
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void spi_lld_stop(SPIDriver *spip);
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void spi_lld_select(SPIDriver *spip);
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void spi_lld_unselect(SPIDriver *spip);
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void spi_lld_ignore(SPIDriver *spip, size_t n);
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void spi_lld_exchange(SPIDriver *spip, size_t n,
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const void *txbuf, void *rxbuf);
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void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf);
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void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf);
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#ifdef __cplusplus
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}
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#endif
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/** @endcond*/
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#endif /* CH_HAL_USE_SPI */
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#endif /* _SPI_LLD_H_ */
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/** @} */
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