317 lines
10 KiB
C
317 lines
10 KiB
C
/*
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ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio.
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This file is part of ChibiOS/RT.
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ChibiOS/RT is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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ChibiOS/RT is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/**
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* @file STM32/pwm_lld.c
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* @brief STM32 PWM subsystem low level driver header.
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* @addtogroup STM32_PWM
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* @{
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*/
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#include "ch.h"
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#include "hal.h"
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#if CH_HAL_USE_PWM || defined(__DOXYGEN__)
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/** @brief PWM1 driver identifier.*/
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#if defined(USE_STM32_PWM1) || defined(__DOXYGEN__)
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PWMDriver PWMD1;
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#endif
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/*===========================================================================*/
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/* Low Level Driver exported variables. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Low Level Driver local variables. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Low Level Driver local functions. */
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/*===========================================================================*/
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/**
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* @brief Stops all channels.
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*
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* @param[in] pwmp pointer to a @p PWMDriver object
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*/
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void stop_channels(PWMDriver *pwmp) {
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pwmp->pd_enabled_channels = 0; /* All channels disabled. */
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pwmp->pd_tim->CCER = 0; /* Outputs disabled. */
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pwmp->pd_tim->CCR1 = 0; /* Comparator 1 disabled. */
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pwmp->pd_tim->CCR2 = 0; /* Comparator 2 disabled. */
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pwmp->pd_tim->CCR3 = 0; /* Comparator 3 disabled. */
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pwmp->pd_tim->CCR4 = 0; /* Comparator 4 disabled. */
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pwmp->pd_tim->CCMR1 = 0; /* Channels 1 and 2 frozen. */
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pwmp->pd_tim->CCMR2 = 0; /* Channels 3 and 4 frozen. */
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}
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/*===========================================================================*/
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/* Low Level Driver interrupt handlers. */
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/*===========================================================================*/
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#if USE_STM32_PWM1
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/**
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* @brief TIM1 update interrupt handler.
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* @note It is assumed that this interrupt is only activated if the callback
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* pointer is not equal to @p NULL in order to not perform an extra
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* check in a potentially critical interrupt handler.
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*/
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CH_IRQ_HANDLER(VectorA4) {
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CH_IRQ_PROLOGUE();
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PWMD1.pd_config->pc_callback();
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CH_IRQ_EPILOGUE();
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}
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/**
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* @brief TIM1 compare interrupt handler.
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* @note It is assumed that the various sources are only activated if the
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* associated callback pointer is not equal to @p NULL in order to not
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* perform an extra check in a potentially critical interrupt handler.
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*/
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CH_IRQ_HANDLER(VectorAC) {
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uint16_t sr;
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CH_IRQ_PROLOGUE();
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sr = TIM1->SR;
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TIM1->SR &= ~(TIM_SR_CC1IF | TIM_SR_CC2IF | TIM_SR_CC3IF | TIM_SR_CC4IF);
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if ((sr & TIM_SR_CC1IF) != 0)
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PWMD1.pd_config->pc_channels[0].pcc_callback();
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if ((sr & TIM_SR_CC2IF) != 0)
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PWMD1.pd_config->pc_channels[1].pcc_callback();
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if ((sr & TIM_SR_CC3IF) != 0)
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PWMD1.pd_config->pc_channels[2].pcc_callback();
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if ((sr & TIM_SR_CC4IF) != 0)
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PWMD1.pd_config->pc_channels[3].pcc_callback();
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CH_IRQ_EPILOGUE();
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}
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#endif /* USE_STM32_PWM1 */
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/*===========================================================================*/
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/* Low Level Driver exported functions. */
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/*===========================================================================*/
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/**
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* @brief Low level PWM driver initialization.
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*/
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void pwm_lld_init(void) {
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#if USE_STM32_PWM1
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/* TIM1 reset, ensures reset state in order to avoid trouble with JTAGs.*/
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RCC->APB2RSTR = RCC_APB2RSTR_TIM1RST;
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RCC->APB2RSTR = 0;
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/* Driver initialization.*/
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pwmObjectInit(&PWMD1);
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PWMD1.pd_enabled_channels = 0;
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PWMD1.pd_tim = TIM1;
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#endif
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}
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/**
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* @brief Configures and activates the PWM peripheral.
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*
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* @param[in] pwmp pointer to a @p PWMDriver object
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*/
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void pwm_lld_start(PWMDriver *pwmp) {
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uint16_t ccer;
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if (pwmp->pd_state == PWM_STOP) {
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/* Clock activation.*/
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#if USE_STM32_PWM1
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if (&PWMD1 == pwmp) {
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NVICEnableVector(TIM1_UP_IRQn, STM32_PWM1_IRQ_PRIORITY);
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NVICEnableVector(TIM1_CC_IRQn, STM32_PWM1_IRQ_PRIORITY);
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RCC->APB2ENR |= RCC_APB2ENR_TIM1EN;
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}
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#endif
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}
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/* Reset channels.*/
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stop_channels(pwmp);
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/* Configuration or reconfiguration.*/
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pwmp->pd_tim->CR1 = 0; /* Timer stopped. */
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pwmp->pd_tim->SMCR = 0; /* Slave mode disabled. */
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pwmp->pd_tim->CR2 = pwmp->pd_config->pc_cr2;
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pwmp->pd_tim->PSC = pwmp->pd_config->pc_psc;
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pwmp->pd_tim->CNT = 0;
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pwmp->pd_tim->ARR = pwmp->pd_config->pc_arr;
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ccer = TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E;
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if (pwmp->pd_config->pc_channels[0].pcc_mode == PWM_ACTIVE_LOW)
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ccer |= TIM_CCER_CC1P;
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if (pwmp->pd_config->pc_channels[1].pcc_mode == PWM_ACTIVE_LOW)
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ccer |= TIM_CCER_CC2P;
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if (pwmp->pd_config->pc_channels[2].pcc_mode == PWM_ACTIVE_LOW)
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ccer |= TIM_CCER_CC3P;
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if (pwmp->pd_config->pc_channels[3].pcc_mode == PWM_ACTIVE_LOW)
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ccer |= TIM_CCER_CC4P;
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pwmp->pd_tim->CCER = ccer;
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pwmp->pd_tim->EGR = TIM_EGR_UG; /* Update event. */
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pwmp->pd_tim->SR = 0; /* Clear pending IRQs. */
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pwmp->pd_tim->DIER = pwmp->pd_config->pc_callback == NULL ? 0 : TIM_DIER_UIE;
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pwmp->pd_tim->CR1 = TIM_CR1_ARPE | TIM_CR1_URS |
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TIM_CR1_CEN; /* Timer configured and started.*/
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}
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/**
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* @brief Deactivates the PWM peripheral.
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*
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* @param[in] pwmp pointer to a @p PWMDriver object
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*/
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void pwm_lld_stop(PWMDriver *pwmp) {
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/* If in ready state then disables the PWM clock.*/
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if (pwmp->pd_state == PWM_READY) {
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stop_channels(pwmp);
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pwmp->pd_tim->CR1 = 0;
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pwmp->pd_tim->DIER = 0;
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#if USE_STM32_PWM1
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if (&PWMD1 == pwmp) {
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NVICDisableVector(TIM1_UP_IRQn);
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NVICDisableVector(TIM1_CC_IRQn);
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RCC->APB2ENR &= ~RCC_APB2ENR_TIM1EN;
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}
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#endif
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}
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}
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/**
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* @brief Enables a PWM channel.
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*
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* @param[in] pwmp pointer to a @p PWMDriver object
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* @param[in] channel PWM channel identifier
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* @param[in] width PWM pulse width as clock pulses number
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*/
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void pwm_lld_enable_channel(PWMDriver *pwmp,
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pwmchannel_t channel,
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pwmcnt_t width) {
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/*
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* Changes the pulse width.
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*/
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switch (channel) {
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case 0:
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pwmp->pd_tim->CCR1 = width;
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break;
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case 1:
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pwmp->pd_tim->CCR2 = width;
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break;
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case 2:
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pwmp->pd_tim->CCR3 = width;
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break;
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case 3:
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pwmp->pd_tim->CCR4 = width;
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break;
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}
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if ((pwmp->pd_enabled_channels & (1 << channel)) == 0) {
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/*
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* The channel is not enabled yet.
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*/
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pwmp->pd_enabled_channels |= (1 << channel);
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/*
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* Setup the comparator, the channel is configured as PWM mode 1 with
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* preload enabled.
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*/
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switch (channel) {
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case 0:
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pwmp->pd_tim->CCMR1 = (pwmp->pd_tim->CCMR1 & 0xFF00) |
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TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2 |
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TIM_CCMR1_OC1PE;
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pwmp->pd_tim->DIER |= pwmp->pd_config->pc_channels[0].pcc_callback == NULL
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? 0 : TIM_DIER_CC1IE;
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pwmp->pd_tim->SR = ~TIM_SR_CC1IF;
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break;
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case 1:
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pwmp->pd_tim->CCMR1 = (pwmp->pd_tim->CCMR1 & 0x00FF) |
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TIM_CCMR1_OC2M_1 | TIM_CCMR1_OC2M_2 |
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TIM_CCMR1_OC2PE;
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pwmp->pd_tim->DIER |= pwmp->pd_config->pc_channels[1].pcc_callback == NULL
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? 0 : TIM_DIER_CC2IE;
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pwmp->pd_tim->SR = ~TIM_SR_CC2IF;
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break;
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case 2:
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pwmp->pd_tim->CCMR2 = (pwmp->pd_tim->CCMR2 & 0xFF00) |
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TIM_CCMR2_OC3M_1 | TIM_CCMR2_OC3M_2 |
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TIM_CCMR2_OC3PE;
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pwmp->pd_tim->DIER |= pwmp->pd_config->pc_channels[2].pcc_callback == NULL
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? 0 : TIM_DIER_CC3IE;
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pwmp->pd_tim->SR = ~TIM_SR_CC3IF;
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break;
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case 3:
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pwmp->pd_tim->CCMR2 = (pwmp->pd_tim->CCMR2 & 0x00FF) |
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TIM_CCMR2_OC4M_1 | TIM_CCMR2_OC4M_2 |
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TIM_CCMR2_OC4PE;
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pwmp->pd_tim->DIER |= pwmp->pd_config->pc_channels[3].pcc_callback == NULL
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? 0 : TIM_DIER_CC4IE;
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pwmp->pd_tim->SR = ~TIM_SR_CC4IF;
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break;
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}
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}
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}
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/**
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* @brief Disables a PWM channel.
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* @details The channel is disabled and its output line returned to the
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* idle state.
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*
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* @param[in] pwmp pointer to a @p PWMDriver object
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* @param[in] channel PWM channel identifier
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*/
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void pwm_lld_disable_channel(PWMDriver *pwmp, pwmchannel_t channel) {
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pwmp->pd_enabled_channels &= ~(1 << channel);
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switch (channel) {
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case 0:
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pwmp->pd_tim->CCR1 = 0;
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pwmp->pd_tim->CCMR1 = pwmp->pd_tim->CCMR1 & 0xFF00;
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pwmp->pd_tim->DIER &= ~TIM_DIER_CC1IE;
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pwmp->pd_tim->SR = ~TIM_SR_CC1IF;
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break;
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case 1:
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pwmp->pd_tim->CCR2 = 0;
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pwmp->pd_tim->CCMR1 = pwmp->pd_tim->CCMR1 & 0x00FF;
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pwmp->pd_tim->DIER &= ~TIM_DIER_CC2IE;
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pwmp->pd_tim->SR = ~TIM_SR_CC2IF;
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break;
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case 2:
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pwmp->pd_tim->CCR3 = 0;
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pwmp->pd_tim->CCMR2 = pwmp->pd_tim->CCMR2 & 0xFF00;
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pwmp->pd_tim->DIER &= ~TIM_DIER_CC3IE;
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pwmp->pd_tim->SR = ~TIM_SR_CC3IF;
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break;
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case 3:
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pwmp->pd_tim->CCR4 = 0;
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pwmp->pd_tim->CCMR2 = pwmp->pd_tim->CCMR2 & 0x00FF;
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pwmp->pd_tim->DIER &= ~TIM_DIER_CC4IE;
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pwmp->pd_tim->SR = ~TIM_SR_CC4IF;
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break;
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}
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}
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#endif /* CH_HAL_USE_PWM */
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/** @} */
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