2356 lines
145 KiB
C
2356 lines
145 KiB
C
/*
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* Copyright (C) 2014 Fabio Utzig, http://fabioutzig.com
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*
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* Permission is hereby granted, free of charge, to any person obtaining
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* a copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
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* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#ifndef _MK20D5_H_
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#define _MK20D5_H_
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/*
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* ==============================================================
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* ---------- Interrupt Number Definition -----------------------
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* ==============================================================
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*/
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typedef enum IRQn
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{
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/****** Cortex-M0 Processor Exceptions Numbers ****************/
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InitialSP_IRQn = -15,
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InitialPC_IRQn = -15,
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NonMaskableInt_IRQn = -14,
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HardFault_IRQn = -13,
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MemoryManagement_IRQn = -12,
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BusFault_IRQn = -11,
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UsageFault_IRQn = -10,
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SVCall_IRQn = -5,
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DebugMonitor_IRQn = -4,
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PendSV_IRQn = -2,
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SysTick_IRQn = -1,
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/****** K20x Specific Interrupt Numbers ***********************/
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DMA0_IRQn = 0,
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DMA1_IRQn = 1,
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DMA2_IRQn = 2,
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DMA3_IRQn = 3,
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DMAError_IRQn = 4,
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DMA_IRQn = 5,
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FlashMemComplete_IRQn = 6,
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FlashMemReadCollision_IRQn = 7,
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LowVoltageWarning_IRQn = 8,
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LLWU_IRQn = 9,
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WDOG_IRQn = 10,
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I2C0_IRQn = 11,
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SPI0_IRQn = 12,
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I2S0_IRQn = 13,
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I2S1_IRQn = 14,
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UART0LON_IRQn = 15,
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UART0Status_IRQn = 16,
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UART0Error_IRQn = 17,
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UART1Status_IRQn = 18,
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UART1Error_IRQn = 19,
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UART2Status_IRQn = 20,
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UART2Error_IRQn = 21,
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ADC0_IRQn = 22,
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CMP0_IRQn = 23,
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CMP1_IRQn = 24,
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FTM0_IRQn = 25,
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FTM1_IRQn = 26,
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CMT_IRQn = 27,
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RTCAlarm_IRQn = 28,
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RTCSeconds_IRQn = 29,
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PITChannel0_IRQn = 30,
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PITChannel1_IRQn = 31,
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PITChannel2_IRQn = 32,
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PITChannel3_IRQn = 33,
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PDB_IRQn = 34,
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USB_OTG_IRQn = 35,
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USBChargerDetect_IRQn = 36,
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TSI_IRQn = 37,
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MCG_IRQn = 38,
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LowPowerTimer_IRQn = 39,
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PINA_IRQn = 40,
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PINB_IRQn = 41,
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PINC_IRQn = 42,
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PIND_IRQn = 43,
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PINE_IRQn = 44,
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SoftInitInt_IRQn = 45,
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} IRQn_Type;
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/*
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* ==========================================================================
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* ----------- Processor and Core Peripheral Section ------------------------
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* ==========================================================================
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*/
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/**
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* @brief K20x Interrupt Number Definition, according to the selected device
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* in @ref Library_configuration_section
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*/
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#define __MPU_PRESENT 0
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#define __NVIC_PRIO_BITS 4
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#define __Vendor_SysTickConfig 0
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#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
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typedef struct
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{
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__IO uint32_t SOPT1;
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__IO uint32_t SOPT1CFG;
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uint32_t RESERVED0[1023];
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__IO uint32_t SOPT2;
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uint32_t RESERVED1[1];
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__IO uint32_t SOPT4;
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__IO uint32_t SOPT5;
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uint32_t RESERVED2[1];
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__IO uint32_t SOPT7;
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uint32_t RESERVED3[2];
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__I uint32_t SDID;
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uint32_t RESERVED4[3];
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__IO uint32_t SCGC4;
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__IO uint32_t SCGC5;
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__IO uint32_t SCGC6;
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__IO uint32_t SCGC7;
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__IO uint32_t CLKDIV1;
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__IO uint32_t CLKDIV2;
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__I uint32_t FCFG1;
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__I uint32_t FCFG2;
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__I uint32_t UIDH;
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__I uint32_t UIDMH;
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__I uint32_t UIDML;
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__I uint32_t UIDL;
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} SIM_TypeDef;
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typedef struct
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{
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__IO uint8_t PE1;
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__IO uint8_t PE2;
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__IO uint8_t PE3;
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__IO uint8_t PE4;
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__IO uint8_t ME;
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__IO uint8_t F1;
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__IO uint8_t F2;
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__I uint8_t F3;
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__IO uint8_t FILT1;
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__IO uint8_t FILT2;
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} LLWU_TypeDef;
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typedef struct
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{
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__IO uint32_t PCR[32];
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__O uint32_t GPCLR;
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__O uint32_t GPCHR;
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uint32_t RESERVED0[6];
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__IO uint32_t ISFR;
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} PORT_TypeDef;
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typedef struct
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{
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__IO uint8_t C1;
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__IO uint8_t C2;
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__IO uint8_t C3;
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__IO uint8_t C4;
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__IO uint8_t C5;
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__IO uint8_t C6;
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__I uint8_t S;
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uint8_t RESERVED0[1];
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__IO uint8_t SC;
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uint8_t RESERVED1[1];
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__IO uint8_t ATCVH;
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__IO uint8_t ATCVL;
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__IO uint8_t C7;
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__IO uint8_t C8;
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} MCG_TypeDef;
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typedef struct
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{
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__IO uint8_t CR;
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} OSC_TypeDef;
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typedef struct {
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uint32_t SADDR; /* TCD Source Address */
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uint16_t SOFF; /* TCD Signed Source Address Offset */
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uint16_t ATTR; /* TCD Transfer Attributes */
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union {
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uint32_t NBYTES_MLNO; /* TCD Minor Byte Count (Minor Loop Disabled) */
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uint32_t NBYTES_MLOFFNO; /* TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled) */
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uint32_t NBYTES_MLOFFYES; /* TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled) */
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};
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uint32_t SLAST; /* TCD Last Source Address Adjustment */
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uint32_t DADDR; /* TCD Destination Address */
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uint16_t DOFF; /* TCD Signed Destination Address Offset */
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union {
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uint16_t CITER_ELINKNO; /* TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) */
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uint16_t CITER_ELINKYES; /* TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) */
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};
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uint32_t DLASTSGA; /* TCD Last Destination Address Adjustment/Scatter Gather Address */
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uint16_t CSR; /* TCD Control and Status */
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union {
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uint16_t BITER_ELINKNO; /* TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) */
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uint16_t BITER_ELINKYES; /* TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) */
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};
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} DMA_TCD_TypeDef;
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/** DMA - Peripheral register structure */
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typedef struct {
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__IO uint32_t CR; /* Control Register */
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__IO uint32_t ES; /* Error Status Register */
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__IO uint8_t RESERVED_0[4];
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__IO uint32_t ERQ; /* Enable Request Register */
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__IO uint8_t RESERVED_1[4];
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__IO uint32_t EEI; /* Enable Error Interrupt Register */
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__IO uint8_t CEEI; /* Clear Enable Error Interrupt Register */
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__IO uint8_t SEEI; /* Set Enable Error Interrupt Register */
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__IO uint8_t CERQ; /* Clear Enable Request Register */
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__IO uint8_t SERQ; /* Set Enable Request Register */
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__IO uint8_t CDNE; /* Clear DONE Status Bit Register */
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__IO uint8_t SSRT; /* Set START Bit Register */
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__IO uint8_t CERR; /* Clear Error Register */
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__IO uint8_t CINT; /* Clear Interrupt Request Register */
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__IO uint8_t RESERVED_2[4];
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__IO uint32_t INT; /* Interrupt Request Register */
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__IO uint8_t RESERVED_3[4];
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__IO uint32_t ERR; /* Error Register */
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__IO uint8_t RESERVED_4[4];
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__IO uint32_t HRS; /* Hardware Request Status Register */
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__IO uint8_t RESERVED_5[200];
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__IO uint8_t DCHPRI3; /* Channel 3 Priority Register */
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__IO uint8_t DCHPRI2; /* Channel 2 Priority Register */
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__IO uint8_t DCHPRI1; /* Channel 1 Priority Register */
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__IO uint8_t DCHPRI0; /* Channel 0 Priority Register */
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__IO uint8_t RESERVED_6[3836];
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DMA_TCD_TypeDef TCD[4];
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} DMA_TypeDef;
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typedef struct
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{
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__IO uint8_t CHCFG[4];
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} DMAMUX_TypeDef;
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/** PIT - Peripheral register structure */
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typedef struct {
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__IO uint32_t MCR; /* PIT Module Control Register */
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uint8_t RESERVED0[252];
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struct PIT_CHANNEL {
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__IO uint32_t LDVAL; /* Timer Load Value Register */
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__IO uint32_t CVAL; /* Current Timer Value Register */
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__IO uint32_t TCTRL; /* Timer Control Register */
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__IO uint32_t TFLG; /* Timer Flag Register */
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} CHANNEL[4];
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} PIT_TypeDef;
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typedef struct
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{
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__IO uint32_t SC; /* Status and Control */
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__IO uint32_t CNT; /* Counter */
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__IO uint32_t MOD; /* Modulo */
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struct FTM_Channel {
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__IO uint32_t CnSC; /* Channel Status and Control */
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__IO uint32_t CnV; /* Channel Value */
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} CHANNEL[8];
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__IO uint32_t CNTIN; /* Counter Initial Value */
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__IO uint32_t STATUS; /* Capture and Compare Status */
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__IO uint32_t MODE; /* Features Mode Selection */
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__IO uint32_t SYNC; /* Synchronization */
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__IO uint32_t OUTINIT; /* Initial State for Channels Output */
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__IO uint32_t OUTMASK; /* Output Mask */
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__IO uint32_t COMBINE; /* Function for Linked Channels */
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__IO uint32_t DEADTIME; /* Deadtime Insertion Control */
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__IO uint32_t EXTTRIG; /* FTM External Trigger */
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__IO uint32_t POL; /* Channels Polarity */
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__IO uint32_t FMS; /* Fault Mode Status */
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__IO uint32_t FILTER; /* Input Capture Filter Control */
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__IO uint32_t FLTCTRL; /* Fault Control */
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__IO uint32_t QDCTRL; /* Quadrature Decode Control and Status */
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__IO uint32_t CONF; /* Configuration */
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__IO uint32_t FTLPOL; /* FTM Fault Input Polarity */
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__IO uint32_t SYNCONF; /* Synchronization Configuration */
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__IO uint32_t INVCTRL; /* FTM Inverting Control */
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__IO uint32_t SWOCTRL; /* FTM Software Output Control */
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__IO uint32_t PWMLOAD; /* FTM PWM Load */
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} FTM_TypeDef;
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typedef struct
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{
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__IO uint32_t SC1A; // offset: 0x00
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__IO uint32_t SC1B; // offset: 0x04
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__IO uint32_t CFG1; // offset: 0x08
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__IO uint32_t CFG2; // offset: 0x0C
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__I uint32_t RA; // offset: 0x10
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__I uint32_t RB; // offset: 0x14
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__IO uint32_t CV1; // offset: 0x18
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__IO uint32_t CV2; // offset: 0x1C
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__IO uint32_t SC2; // offset: 0x20
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__IO uint32_t SC3; // offset: 0x24
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__IO uint32_t OFS; // offset: 0x28
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__IO uint32_t PG; // offset: 0x2C
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__IO uint32_t MG; // offset: 0x30
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__IO uint32_t CLPD; // offset: 0x34
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__IO uint32_t CLPS; // offset: 0x38
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__IO uint32_t CLP4; // offset: 0x3C
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__IO uint32_t CLP3; // offset: 0x40
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__IO uint32_t CLP2; // offset: 0x44
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__IO uint32_t CLP1; // offset: 0x48
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__IO uint32_t CLP0; // offset: 0x4C
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uint32_t RESERVED0[1]; // offset: 0x50
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__IO uint32_t CLMD; // offset: 0x54
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__IO uint32_t CLMS; // offset: 0x58
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__IO uint32_t CLM4; // offset: 0x5C
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__IO uint32_t CLM3; // offset: 0x60
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__IO uint32_t CLM2; // offset: 0x64
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__IO uint32_t CLM1; // offset: 0x68
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__IO uint32_t CLM0; // offset: 0x6C
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} ADC_TypeDef;
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typedef struct
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{
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__IO uint32_t CSR;
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__IO uint32_t PSR;
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__IO uint32_t CMR;
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__I uint32_t CNR;
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} LPTMR_TypeDef;
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typedef struct
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{
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__IO uint32_t GENCS;
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__IO uint32_t DATA;
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__IO uint32_t TSHD;
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} TSI_TypeDef;
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typedef struct
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{
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__IO uint32_t PDOR;
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__IO uint32_t PSOR;
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__IO uint32_t PCOR;
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__IO uint32_t PTOR;
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__IO uint32_t PDIR;
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__IO uint32_t PDDR;
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} GPIO_TypeDef;
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/** SPI - Peripheral register structure */
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typedef struct {
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__IO uint32_t MCR; /**< DSPI Module Configuration Register, offset: 0x0 */
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uint32_t RESERVED0[1];
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__IO uint32_t TCR; /**< DSPI Transfer Count Register, offset: 0x8 */
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union { /* offset: 0xC */
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__IO uint32_t CTAR[2]; /**< DSPI Clock and Transfer Attributes Register (In Master Mode), array offset: 0xC, array step: 0x4 */
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__IO uint32_t CTAR_SLAVE[1]; /**< DSPI Clock and Transfer Attributes Register (In Slave Mode), array offset: 0xC, array step: 0x4 */
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};
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uint32_t RESERVED1[6];
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__IO uint32_t SR; /**< DSPI Status Register, offset: 0x2C */
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__IO uint32_t RSER; /**< DSPI DMA/Interrupt Request Select and Enable Register, offset: 0x30 */
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union { /* offset: 0x34 */
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__IO uint32_t PUSHR; /**< DSPI PUSH TX FIFO Register In Master Mode, offset: 0x34 */
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__IO uint32_t PUSHR_SLAVE; /**< DSPI PUSH TX FIFO Register In Slave Mode, offset: 0x34 */
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};
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__I uint32_t POPR; /**< DSPI POP RX FIFO Register, offset: 0x38 */
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__I uint32_t TXFR[4]; /**< DSPI Transmit FIFO Registers, offset: 0x3C */
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uint32_t RESERVED2[12];
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__I uint32_t RXFR[4]; /**< DSPI Receive FIFO Registers, offset: 0x7C */
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} SPI_TypeDef;
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typedef struct
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{
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__IO uint8_t A1;
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__IO uint8_t F;
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__IO uint8_t C1;
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__IO uint8_t S;
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__IO uint8_t D;
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__IO uint8_t C2;
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__IO uint8_t FLT;
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__IO uint8_t RA;
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__IO uint8_t SMB;
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__IO uint8_t A2;
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__IO uint8_t SLTH;
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__IO uint8_t SLTL;
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} I2C_TypeDef;
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typedef struct
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{
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__IO uint8_t BDH;
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__IO uint8_t BDL;
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__IO uint8_t C1;
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__IO uint8_t C2;
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__I uint8_t S1;
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__IO uint8_t S2;
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__IO uint8_t C3;
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__IO uint8_t D;
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__IO uint8_t MA1;
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__IO uint8_t MA2;
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__IO uint8_t C4;
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__IO uint8_t C5;
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__I uint8_t ED;
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__IO uint8_t MODEM;
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__IO uint8_t IR;
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uint8_t RESERVED0[1];
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__IO uint8_t PFIFO;
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__IO uint8_t CFIFO;
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__IO uint8_t SFIFO;
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__IO uint8_t TWFIFO;
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__I uint8_t TCFIFO;
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__IO uint8_t RWFIFO;
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__I uint8_t RCFIFO;
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uint8_t RESERVED1[1];
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__IO uint8_t C7816;
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__IO uint8_t IE7816;
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__IO uint8_t IS7816;
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union {
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__IO uint8_t WP7816T0;
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__IO uint8_t WP7816T1;
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};
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__IO uint8_t WN7816;
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__IO uint8_t WF7816;
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__IO uint8_t ET7816;
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__IO uint8_t TL7816;
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uint8_t RESERVED2[2];
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__IO uint8_t C6;
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__IO uint8_t PCTH;
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__IO uint8_t PCTL;
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__IO uint8_t B1T;
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__IO uint8_t SDTH;
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__IO uint8_t SDTL;
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__IO uint8_t PRE;
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__IO uint8_t TPL;
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__IO uint8_t IE;
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__IO uint8_t WB;
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__IO uint8_t S3;
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__IO uint8_t S4;
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__I uint8_t RPL;
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__I uint8_t RPREL;
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__IO uint8_t CPW;
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__IO uint8_t RIDT;
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__IO uint8_t TIDT;
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} UART_TypeDef;
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typedef struct
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{
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__IO uint8_t LVDSC1;
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__IO uint8_t LVDSC2;
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__IO uint8_t REGSC;
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} PMC_TypeDef;
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typedef struct
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{
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__IO uint16_t STCTRLH;
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__IO uint16_t STCTRLL;
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__IO uint16_t TOVALH;
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__IO uint16_t TOVALL;
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__IO uint16_t WINH;
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__IO uint16_t WINL;
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__IO uint16_t REFRESH;
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__IO uint16_t UNLOCK;
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__IO uint16_t TMROUTH;
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__IO uint16_t TMROUTL;
|
|
__IO uint16_t RSTCNT;
|
|
__IO uint16_t PRESC;
|
|
} WDOG_TypeDef;
|
|
|
|
typedef struct {
|
|
__I uint8_t USB0_PERID; // 0x00
|
|
uint8_t RESERVED0[3];
|
|
__I uint8_t USB0_IDCOMP; // 0x04
|
|
uint8_t RESERVED1[3];
|
|
__I uint8_t USB0_REV; // 0x08
|
|
uint8_t RESERVED2[3];
|
|
__I uint8_t USB0_ADDINFO; // 0x0C
|
|
uint8_t RESERVED3[3];
|
|
__IO uint8_t USB0_OTGISTAT; // 0x10
|
|
uint8_t RESERVED4[3];
|
|
__IO uint8_t USB0_OTGICR; // 0x14
|
|
uint8_t RESERVED5[3];
|
|
__IO uint8_t USB0_OTGSTAT; // 0x18
|
|
uint8_t RESERVED6[3];
|
|
__IO uint8_t USB0_OTGCTL; // 0x1C
|
|
uint8_t RESERVED7[99];
|
|
__IO uint8_t USB0_ISTAT; // 0x80
|
|
uint8_t RESERVED8[3];
|
|
__IO uint8_t USB0_INTEN; // 0x84
|
|
uint8_t RESERVED9[3];
|
|
__IO uint8_t USB0_ERRSTAT; // 0x88
|
|
uint8_t RESERVED10[3];
|
|
__IO uint8_t USB0_ERREN; // 0x8C
|
|
uint8_t RESERVED11[3];
|
|
__I uint8_t USB0_STAT; // 0x90
|
|
uint8_t RESERVED12[3];
|
|
__IO uint8_t USB0_CTL; // 0x94
|
|
uint8_t RESERVED13[3];
|
|
__IO uint8_t USB0_ADDR; // 0x98
|
|
uint8_t RESERVED14[3];
|
|
__IO uint8_t USB0_BDTPAGE1; // 0x9C
|
|
uint8_t RESERVED15[3];
|
|
__IO uint8_t USB0_FRMNUML; // 0xA0
|
|
uint8_t RESERVED16[3];
|
|
__IO uint8_t USB0_FRMNUMH; // 0xA4
|
|
uint8_t RESERVED17[3];
|
|
__IO uint8_t USB0_TOKEN; // 0xA8
|
|
uint8_t RESERVED18[3];
|
|
__IO uint8_t USB0_SOFTHLD; // 0xAC
|
|
uint8_t RESERVED19[3];
|
|
__IO uint8_t USB0_BDTPAGE2; // 0xB0
|
|
uint8_t RESERVED20[3];
|
|
__IO uint8_t USB0_BDTPAGE3; // 0xB4
|
|
uint8_t RESERVED21[11];
|
|
__IO uint8_t USB0_ENDPT0; // 0xC0
|
|
uint8_t RESERVED22[3];
|
|
__IO uint8_t USB0_ENDPT1; // 0xC4
|
|
uint8_t RESERVED23[3];
|
|
__IO uint8_t USB0_ENDPT2; // 0xC8
|
|
uint8_t RESERVED24[3];
|
|
__IO uint8_t USB0_ENDPT3; // 0xCC
|
|
uint8_t RESERVED25[3];
|
|
__IO uint8_t USB0_ENDPT4; // 0xD0
|
|
uint8_t RESERVED26[3];
|
|
__IO uint8_t USB0_ENDPT5; // 0xD4
|
|
uint8_t RESERVED27[3];
|
|
__IO uint8_t USB0_ENDPT6; // 0xD8
|
|
uint8_t RESERVED28[3];
|
|
__IO uint8_t USB0_ENDPT7; // 0xDC
|
|
uint8_t RESERVED29[3];
|
|
__IO uint8_t USB0_ENDPT8; // 0xE0
|
|
uint8_t RESERVED30[3];
|
|
__IO uint8_t USB0_ENDPT9; // 0xE4
|
|
uint8_t RESERVED31[3];
|
|
__IO uint8_t USB0_ENDPT10; // 0xE8
|
|
uint8_t RESERVED32[3];
|
|
__IO uint8_t USB0_ENDPT11; // 0xEC
|
|
uint8_t RESERVED33[3];
|
|
__IO uint8_t USB0_ENDPT12; // 0xF0
|
|
uint8_t RESERVED34[3];
|
|
__IO uint8_t USB0_ENDPT13; // 0xF4
|
|
uint8_t RESERVED35[3];
|
|
__IO uint8_t USB0_ENDPT14; // 0xF8
|
|
uint8_t RESERVED36[3];
|
|
__IO uint8_t USB0_ENDPT15; // 0xFC
|
|
uint8_t RESERVED37[3];
|
|
__IO uint8_t USB0_USBCTRL; // 0x100
|
|
uint8_t RESERVED38[3];
|
|
__I uint8_t USB0_OBSERVE; // 0x104
|
|
uint8_t RESERVED39[3];
|
|
__IO uint8_t USB0_CONTROL; // 0x108
|
|
uint8_t RESERVED40[3];
|
|
__IO uint8_t USB0_USBTRC0; // 0x10C
|
|
uint8_t RESERVED41[7];
|
|
__IO uint8_t USB0_USBFRMADJUST; // 0x114
|
|
} USBOTG_TypeDef;
|
|
|
|
/****************************************************************/
|
|
/* Peripheral memory map */
|
|
/****************************************************************/
|
|
#define DMA_BASE ((uint32_t)0x40008000)
|
|
#define DMAMUX_BASE ((uint32_t)0x40021000)
|
|
#define SPI0_BASE ((uint32_t)0x4002C000)
|
|
#define PIT_BASE ((uint32_t)0x40037000)
|
|
#define FTM0_BASE ((uint32_t)0x40038000)
|
|
#define FTM1_BASE ((uint32_t)0x40039000)
|
|
#define ADC0_BASE ((uint32_t)0x4003B000)
|
|
#define LPTMR0_BASE ((uint32_t)0x40040000)
|
|
#define TSI0_BASE ((uint32_t)0x40045000)
|
|
#define SIM_BASE ((uint32_t)0x40047000)
|
|
#define PORTA_BASE ((uint32_t)0x40049000)
|
|
#define PORTB_BASE ((uint32_t)0x4004A000)
|
|
#define PORTC_BASE ((uint32_t)0x4004B000)
|
|
#define PORTD_BASE ((uint32_t)0x4004C000)
|
|
#define PORTE_BASE ((uint32_t)0x4004D000)
|
|
#define WDOG_BASE ((uint32_t)0x40052000)
|
|
#define MCG_BASE ((uint32_t)0x40064000)
|
|
#define OSC0_BASE ((uint32_t)0x40065000)
|
|
#define I2C0_BASE ((uint32_t)0x40066000)
|
|
#define UART0_BASE ((uint32_t)0x4006A000)
|
|
#define UART1_BASE ((uint32_t)0x4006B000)
|
|
#define UART2_BASE ((uint32_t)0x4006C000)
|
|
#define USBOTG_BASE ((uint32_t)0x40072000)
|
|
#define LLWU_BASE ((uint32_t)0x4007C000)
|
|
#define PMC_BASE ((uint32_t)0x4007D000)
|
|
#define GPIOA_BASE ((uint32_t)0x400FF000)
|
|
#define GPIOB_BASE ((uint32_t)0x400FF040)
|
|
#define GPIOC_BASE ((uint32_t)0x400FF080)
|
|
#define GPIOD_BASE ((uint32_t)0x400FF0C0)
|
|
#define GPIOE_BASE ((uint32_t)0x400FF100)
|
|
|
|
/****************************************************************/
|
|
/* Peripheral declaration */
|
|
/****************************************************************/
|
|
#define DMA ((DMA_TypeDef *) DMA_BASE)
|
|
#define DMAMUX ((DMAMUX_TypeDef *) DMAMUX_BASE)
|
|
#define PIT ((PIT_TypeDef *) PIT_BASE)
|
|
#define FTM0 ((FTM_TypeDef *) FTM0_BASE)
|
|
#define FTM1 ((FTM_TypeDef *) FTM1_BASE)
|
|
#define ADC0 ((ADC_TypeDef *) ADC0_BASE)
|
|
#define LPTMR0 ((LPTMR_TypeDef *) LPTMR0_BASE)
|
|
#define TSI0 ((TSI_TypeDef *) TSI0_BASE)
|
|
#define SIM ((SIM_TypeDef *) SIM_BASE)
|
|
#define LLWU ((LLWU_TypeDef *) LLWU_BASE)
|
|
#define PMC ((PMC_TypeDef *) PMC_BASE)
|
|
#define PORTA ((PORT_TypeDef *) PORTA_BASE)
|
|
#define PORTB ((PORT_TypeDef *) PORTB_BASE)
|
|
#define PORTC ((PORT_TypeDef *) PORTC_BASE)
|
|
#define PORTD ((PORT_TypeDef *) PORTD_BASE)
|
|
#define PORTE ((PORT_TypeDef *) PORTE_BASE)
|
|
#define WDOG ((WDOG_TypeDef *) WDOG_BASE)
|
|
#define USBOTG ((USBOTG_TypeDef *) USBOTG_BASE)
|
|
#define MCG ((MCG_TypeDef *) MCG_BASE)
|
|
#define OSC ((OSC_TypeDef *) OSC0_BASE)
|
|
#define SPI0 ((SPI_TypeDef *) SPI0_BASE)
|
|
#define I2C0 ((I2C_TypeDef *) I2C0_BASE)
|
|
#define UART0 ((UART_TypeDef *) UART0_BASE)
|
|
#define UART1 ((UART_TypeDef *) UART1_BASE)
|
|
#define UART2 ((UART_TypeDef *) UART2_BASE)
|
|
#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
|
|
#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
|
|
#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
|
|
#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
|
|
#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
|
|
|
|
/****************************************************************/
|
|
/* Peripheral Registers Bits Definition */
|
|
/****************************************************************/
|
|
|
|
/****************************************************************/
|
|
/* */
|
|
/* System Integration Module (SIM) */
|
|
/* */
|
|
/****************************************************************/
|
|
/********* Bits definition for SIM_SOPT1 register *************/
|
|
#define SIM_SOPT1_USBREGEN ((uint32_t)0x80000000) /*!< USB voltage regulator enable */
|
|
#define SIM_SOPT1_USBSSTBY ((uint32_t)0x40000000) /*!< USB voltage regulator in standby mode during Stop, VLPS, LLS and VLLS modes */
|
|
#define SIM_SOPT1_USBVSTBY ((uint32_t)0x20000000) /*!< USB voltage regulator in standby mode during VLPR and VLPW modes */
|
|
#define SIM_SOPT1_OSC32KSEL_SHIFT 18 /*!< 32K oscillator clock select (shift) */
|
|
#define SIM_SOPT1_OSC32KSEL_MASK ((uint32_t)((uint32_t)0x3 << SIM_SOPT1_OSC32KSEL_SHIFT)) /*!< 32K oscillator clock select (mask) */
|
|
#define SIM_SOPT1_OSC32KSEL(x) ((uint32_t)(((uint32_t)(x) << SIM_SOPT1_OSC32KSEL_SHIFT) & SIM_SOPT1_OSC32KSEL_MASK)) /*!< 32K oscillator clock select */
|
|
#define SIM_SOPT1_RAMSIZE_SHIFT 12
|
|
#define SIM_SOPT1_RAMSIZE_MASK ((uint32_t)((uint32_t)0xf << SIM_SOPT1_RAMSIZE_SHIFT))
|
|
#define SIM_SOPT1_RAMSIZE(x) ((uint32_t)(((uint32_t)(x) << SIM_SOPT1_RAMSIZE_SHIFT) & SIM_SOPT1_RAMSIZE_MASK))
|
|
|
|
/******* Bits definition for SIM_SOPT1CFG register ************/
|
|
#define SIM_SOPT1CFG_USSWE ((uint32_t)0x04000000) /*!< USB voltage regulator stop standby write enable */
|
|
#define SIM_SOPT1CFG_UVSWE ((uint32_t)0x02000000) /*!< USB voltage regulator VLP standby write enable */
|
|
#define SIM_SOPT1CFG_URWE ((uint32_t)0x01000000) /*!< USB voltage regulator voltage regulator write enable */
|
|
|
|
/******* Bits definition for SIM_SOPT2 register ************/
|
|
#define SIM_SOPT2_USBSRC ((uint32_t)0x00040000) /*!< USB clock source select */
|
|
#define SIM_SOPT2_PLLFLLSEL ((uint32_t)0x00010000) /*!< PLL/FLL clock select */
|
|
#define SIM_SOPT2_TRACECLKSEL ((uint32_t)0x00001000)
|
|
#define SIM_SOPT2_PTD7PAD ((uint32_t)0x00000800)
|
|
#define SIM_SOPT2_CLKOUTSEL_SHIFT 5
|
|
#define SIM_SOPT2_CLKOUTSEL_MASK ((uint32_t)((uint32_t)0x7 << SIM_SOPT2_CLKOUTSEL_SHIFT))
|
|
#define SIM_SOPT2_CLKOUTSEL(x) ((uint32_t)(((uint32_t)(x) << SIM_SOPT2_CLKOUTSEL_SHIFT) & SIM_SOPT2_CLKOUTSEL_MASK))
|
|
#define SIM_SOPT2_RTCCLKOUTSEL ((uint32_t)0x00000010) /*!< RTC clock out select */
|
|
|
|
/******* Bits definition for SIM_SCGC4 register ************/
|
|
#define SIM_SCGC4_VREF ((uint32_t)0x00100000) /*!< VREF Clock Gate Control */
|
|
#define SIM_SCGC4_CMP ((uint32_t)0x00080000) /*!< Comparator Clock Gate Control */
|
|
#define SIM_SCGC4_USBOTG ((uint32_t)0x00040000) /*!< USB Clock Gate Control */
|
|
#define SIM_SCGC4_UART2 ((uint32_t)0x00001000) /*!< UART2 Clock Gate Control */
|
|
#define SIM_SCGC4_UART1 ((uint32_t)0x00000800) /*!< UART1 Clock Gate Control */
|
|
#define SIM_SCGC4_UART0 ((uint32_t)0x00000400) /*!< UART0 Clock Gate Control */
|
|
#define SIM_SCGC4_I2C0 ((uint32_t)0x00000040) /*!< I2C0 Clock Gate Control */
|
|
#define SIM_SCGC4_CMT ((uint32_t)0x00000004) /*!< CMT Clock Gate Control */
|
|
#define SIM_SCGC4_EMW ((uint32_t)0x00000002) /*!< EWM Clock Gate Control */
|
|
|
|
/******* Bits definition for SIM_SCGC5 register ************/
|
|
#define SIM_SCGC5_PORTE ((uint32_t)0x00002000) /*!< Port E Clock Gate Control */
|
|
#define SIM_SCGC5_PORTD ((uint32_t)0x00001000) /*!< Port D Clock Gate Control */
|
|
#define SIM_SCGC5_PORTC ((uint32_t)0x00000800) /*!< Port C Clock Gate Control */
|
|
#define SIM_SCGC5_PORTB ((uint32_t)0x00000400) /*!< Port B Clock Gate Control */
|
|
#define SIM_SCGC5_PORTA ((uint32_t)0x00000200) /*!< Port A Clock Gate Control */
|
|
#define SIM_SCGC5_TSI ((uint32_t)0x00000020) /*!< TSI Access Control */
|
|
#define SIM_SCGC5_LPTIMER ((uint32_t)0x00000001) /*!< Low Power Timer Access Control */
|
|
|
|
/******* Bits definition for SIM_SCGC6 register ************/
|
|
#define SIM_SCGC6_RTC ((uint32_t)0x20000000) /*!< RTC Access Control */
|
|
#define SIM_SCGC6_ADC0 ((uint32_t)0x08000000) /*!< ADC0 Clock Gate Control */
|
|
#define SIM_SCGC6_FTM1 ((uint32_t)0x02000000) /*!< FTM1 Clock Gate Control */
|
|
#define SIM_SCGC6_FTM0 ((uint32_t)0x01000000) /*!< FTM0 Clock Gate Control */
|
|
#define SIM_SCGC6_PIT ((uint32_t)0x00800000) /*!< PIT Clock Gate Control */
|
|
#define SIM_SCGC6_PDB ((uint32_t)0x00400000) /*!< PDB Clock Gate Control */
|
|
#define SIM_SCGC6_USBDCD ((uint32_t)0x00200000) /*!< USB DCD Clock Gate Control */
|
|
#define SIM_SCGC6_CRC ((uint32_t)0x00040000) /*!< Low Power Timer Access Control */
|
|
#define SIM_SCGC6_I2S ((uint32_t)0x00008000) /*!< CRC Clock Gate Control */
|
|
#define SIM_SCGC6_SPI0 ((uint32_t)0x00001000) /*!< SPI0 Clock Gate Control */
|
|
#define SIM_SCGC6_DMAMUX ((uint32_t)0x00000002) /*!< DMA Mux Clock Gate Control */
|
|
#define SIM_SCGC6_FTFL ((uint32_t)0x00000001) /*!< Flash Memory Clock Gate Control */
|
|
|
|
/******* Bits definition for SIM_SCGC6 register ************/
|
|
#define SIM_SCGC7_DMA ((uint32_t)0x00000002) /*!< DMA Clock Gate Control */
|
|
|
|
/****** Bits definition for SIM_CLKDIV1 register ***********/
|
|
#define SIM_CLKDIV1_OUTDIV1_SHIFT 28
|
|
#define SIM_CLKDIV1_OUTDIV1_MASK ((uint32_t)((uint32_t)0xF << SIM_CLKDIV1_OUTDIV1_SHIFT))
|
|
#define SIM_CLKDIV1_OUTDIV1(x) ((uint32_t)(((uint32_t)(x) << SIM_CLKDIV1_OUTDIV1_SHIFT) & SIM_CLKDIV1_OUTDIV1_MASK))
|
|
#define SIM_CLKDIV1_OUTDIV2_SHIFT 24
|
|
#define SIM_CLKDIV1_OUTDIV2_MASK ((uint32_t)((uint32_t)0xF << SIM_CLKDIV1_OUTDIV2_SHIFT))
|
|
#define SIM_CLKDIV1_OUTDIV2(x) ((uint32_t)(((uint32_t)(x) << SIM_CLKDIV1_OUTDIV2_SHIFT) & SIM_CLKDIV1_OUTDIV2_MASK))
|
|
#define SIM_CLKDIV1_OUTDIV4_SHIFT 16
|
|
#define SIM_CLKDIV1_OUTDIV4_MASK ((uint32_t)((uint32_t)0x7 << SIM_CLKDIV1_OUTDIV4_SHIFT))
|
|
#define SIM_CLKDIV1_OUTDIV4(x) ((uint32_t)(((uint32_t)(x) << SIM_CLKDIV1_OUTDIV4_SHIFT) & SIM_CLKDIV1_OUTDIV4_MASK))
|
|
|
|
/****** Bits definition for SIM_CLKDIV2 register ***********/
|
|
#define SIM_CLKDIV2_USBDIV_SHIFT 1
|
|
#define SIM_CLKDIV2_USBDIV_MASK ((uint32_t)((uint32_t)0x7 << SIM_CLKDIV2_USBDIV_SHIFT))
|
|
#define SIM_CLKDIV2_USBDIV(x) ((uint32_t)(((uint32_t)(x) << SIM_CLKDIV2_USBDIV_SHIFT) & SIM_CLKDIV2_USBDIV_MASK))
|
|
#define SIM_CLKDIV2_USBFRAC ((uint32_t)0x00000001)
|
|
|
|
/****************************************************************/
|
|
/* */
|
|
/* Low-Leakage Wakeup Unit (LLWU) */
|
|
/* */
|
|
/****************************************************************/
|
|
/********** Bits definition for LLWU_PE1 register *************/
|
|
#define LLWU_PE1_WUPE3_SHIFT 6 /*!< Wakeup Pin Enable for LLWU_P3 (shift) */
|
|
#define LLWU_PE1_WUPE3_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE1_WUPE3_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P3 (mask) */
|
|
#define LLWU_PE1_WUPE3(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE1_WUPE3_SHIFT) & LLWU_PE1_WUPE3_MASK)) /*!< Wakeup Pin Enable for LLWU_P3 */
|
|
#define LLWU_PE1_WUPE2_SHIFT 4 /*!< Wakeup Pin Enable for LLWU_P2 (shift) */
|
|
#define LLWU_PE1_WUPE2_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE1_WUPE2_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P2 (mask) */
|
|
#define LLWU_PE1_WUPE2(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE1_WUPE2_SHIFT) & LLWU_PE1_WUPE2_MASK)) /*!< Wakeup Pin Enable for LLWU_P2 */
|
|
#define LLWU_PE1_WUPE1_SHIFT 2 /*!< Wakeup Pin Enable for LLWU_P1 (shift) */
|
|
#define LLWU_PE1_WUPE1_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE1_WUPE1_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P1 (mask) */
|
|
#define LLWU_PE1_WUPE1(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE1_WUPE1_SHIFT) & LLWU_PE1_WUPE1_MASK)) /*!< Wakeup Pin Enable for LLWU_P1 */
|
|
#define LLWU_PE1_WUPE0_SHIFT 0 /*!< Wakeup Pin Enable for LLWU_P0 (shift) */
|
|
#define LLWU_PE1_WUPE0_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE1_WUPE0_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P0 (mask) */
|
|
#define LLWU_PE1_WUPE0(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE1_WUPE0_SHIFT) & LLWU_PE1_WUPE0_MASK)) /*!< Wakeup Pin Enable for LLWU_P0 */
|
|
|
|
/********** Bits definition for LLWU_PE2 register *************/
|
|
#define LLWU_PE2_WUPE7_SHIFT 6 /*!< Wakeup Pin Enable for LLWU_P7 (shift) */
|
|
#define LLWU_PE2_WUPE7_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE2_WUPE7_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P7 (mask) */
|
|
#define LLWU_PE2_WUPE7(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE2_WUPE7_SHIFT) & LLWU_PE2_WUPE7_MASK)) /*!< Wakeup Pin Enable for LLWU_P7 */
|
|
#define LLWU_PE2_WUPE6_SHIFT 4 /*!< Wakeup Pin Enable for LLWU_P6 (shift) */
|
|
#define LLWU_PE2_WUPE6_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE2_WUPE6_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P6 (mask) */
|
|
#define LLWU_PE2_WUPE6(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE2_WUPE6_SHIFT) & LLWU_PE2_WUPE6_MASK)) /*!< Wakeup Pin Enable for LLWU_P6 */
|
|
#define LLWU_PE2_WUPE5_SHIFT 2 /*!< Wakeup Pin Enable for LLWU_P5 (shift) */
|
|
#define LLWU_PE2_WUPE5_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE2_WUPE5_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P5 (mask) */
|
|
#define LLWU_PE2_WUPE5(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE2_WUPE5_SHIFT) & LLWU_PE2_WUPE5_MASK)) /*!< Wakeup Pin Enable for LLWU_P5 */
|
|
#define LLWU_PE2_WUPE4_SHIFT 0 /*!< Wakeup Pin Enable for LLWU_P4 (shift) */
|
|
#define LLWU_PE2_WUPE4_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE2_WUPE4_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P4 (mask) */
|
|
#define LLWU_PE2_WUPE4(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE2_WUPE4_SHIFT) & LLWU_PE2_WUPE4_MASK)) /*!< Wakeup Pin Enable for LLWU_P4 */
|
|
|
|
/********** Bits definition for LLWU_PE3 register *************/
|
|
#define LLWU_PE3_WUPE11_SHIFT 6 /*!< Wakeup Pin Enable for LLWU_P11 (shift) */
|
|
#define LLWU_PE3_WUPE11_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE3_WUPE11_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P11 (mask) */
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#define LLWU_PE3_WUPE11(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE3_WUPE11_SHIFT) & LLWU_PE3_WUPE11_MASK)) /*!< Wakeup Pin Enable for LLWU_P11 */
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#define LLWU_PE3_WUPE10_SHIFT 4 /*!< Wakeup Pin Enable for LLWU_P10 (shift) */
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#define LLWU_PE3_WUPE10_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE3_WUPE10_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P10 (mask) */
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#define LLWU_PE3_WUPE10(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE3_WUPE10_SHIFT) & LLWU_PE3_WUPE10_MASK)) /*!< Wakeup Pin Enable for LLWU_P10 */
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#define LLWU_PE3_WUPE13_SHIFT 2 /*!< Wakeup Pin Enable for LLWU_P9 (shift) */
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#define LLWU_PE3_WUPE13_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE3_WUPE13_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P9 (mask) */
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#define LLWU_PE3_WUPE13(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE3_WUPE13_SHIFT) & LLWU_PE3_WUPE13_MASK)) /*!< Wakeup Pin Enable for LLWU_P9 */
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#define LLWU_PE3_WUPE8_SHIFT 0 /*!< Wakeup Pin Enable for LLWU_P8 (shift) */
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#define LLWU_PE3_WUPE8_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE3_WUPE8_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P8 (mask) */
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#define LLWU_PE3_WUPE8(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE3_WUPE8_SHIFT) & LLWU_PE3_WUPE8_MASK)) /*!< Wakeup Pin Enable for LLWU_P8 */
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/********** Bits definition for LLWU_PE4 register *************/
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#define LLWU_PE4_WUPE15_SHIFT 6 /*!< Wakeup Pin Enable for LLWU_P15 (shift) */
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#define LLWU_PE4_WUPE15_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE4_WUPE15_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P15 (mask) */
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#define LLWU_PE4_WUPE15(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE4_WUPE15_SHIFT) & LLWU_PE4_WUPE15_MASK)) /*!< Wakeup Pin Enable for LLWU_P15 */
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#define LLWU_PE4_WUPE14_SHIFT 4 /*!< Wakeup Pin Enable for LLWU_P14 (shift) */
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#define LLWU_PE4_WUPE14_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE4_WUPE14_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P14 (mask) */
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#define LLWU_PE4_WUPE14(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE4_WUPE14_SHIFT) & LLWU_PE4_WUPE14_MASK)) /*!< Wakeup Pin Enable for LLWU_P14 */
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#define LLWU_PE4_WUPE13_SHIFT 2 /*!< Wakeup Pin Enable for LLWU_P13 (shift) */
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#define LLWU_PE4_WUPE13_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE4_WUPE13_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P13 (mask) */
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#define LLWU_PE4_WUPE13(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE4_WUPE13_SHIFT) & LLWU_PE4_WUPE13_MASK)) /*!< Wakeup Pin Enable for LLWU_P13 */
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#define LLWU_PE4_WUPE12_SHIFT 0 /*!< Wakeup Pin Enable for LLWU_P12 (shift) */
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#define LLWU_PE4_WUPE12_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE4_WUPE12_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P12 (mask) */
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#define LLWU_PE4_WUPE12(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE4_WUPE12_SHIFT) & LLWU_PE4_WUPE12_MASK)) /*!< Wakeup Pin Enable for LLWU_P12 */
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/********** Bits definition for LLWU_ME register *************/
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#define LLWU_ME_WUME7 ((uint8_t)((uint8_t)1 << 7)) /*!< Wakeup Module Enable for Module 7 */
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#define LLWU_ME_WUME6 ((uint8_t)((uint8_t)1 << 6)) /*!< Wakeup Module Enable for Module 6 */
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#define LLWU_ME_WUME5 ((uint8_t)((uint8_t)1 << 5)) /*!< Wakeup Module Enable for Module 5 */
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#define LLWU_ME_WUME4 ((uint8_t)((uint8_t)1 << 4)) /*!< Wakeup Module Enable for Module 4 */
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#define LLWU_ME_WUME3 ((uint8_t)((uint8_t)1 << 3)) /*!< Wakeup Module Enable for Module 3 */
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#define LLWU_ME_WUME2 ((uint8_t)((uint8_t)1 << 2)) /*!< Wakeup Module Enable for Module 2 */
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#define LLWU_ME_WUME1 ((uint8_t)((uint8_t)1 << 1)) /*!< Wakeup Module Enable for Module 1 */
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#define LLWU_ME_WUME0 ((uint8_t)((uint8_t)1 << 0)) /*!< Wakeup Module Enable for Module 0 */
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/********** Bits definition for LLWU_F1 register *************/
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#define LLWU_F1_WUF7 ((uint8_t)((uint8_t)1 << 7)) /*!< Wakeup Flag for LLWU_P7 */
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#define LLWU_F1_WUF6 ((uint8_t)((uint8_t)1 << 6)) /*!< Wakeup Flag for LLWU_P6 */
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#define LLWU_F1_WUF5 ((uint8_t)((uint8_t)1 << 5)) /*!< Wakeup Flag for LLWU_P5 */
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#define LLWU_F1_WUF4 ((uint8_t)((uint8_t)1 << 4)) /*!< Wakeup Flag for LLWU_P4 */
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#define LLWU_F1_WUF3 ((uint8_t)((uint8_t)1 << 3)) /*!< Wakeup Flag for LLWU_P3 */
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#define LLWU_F1_WUF2 ((uint8_t)((uint8_t)1 << 2)) /*!< Wakeup Flag for LLWU_P2 */
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#define LLWU_F1_WUF1 ((uint8_t)((uint8_t)1 << 1)) /*!< Wakeup Flag for LLWU_P1 */
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#define LLWU_F1_WUF0 ((uint8_t)((uint8_t)1 << 0)) /*!< Wakeup Flag for LLWU_P0 */
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/********** Bits definition for LLWU_F2 register *************/
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#define LLWU_F2_WUF15 ((uint8_t)((uint8_t)1 << 7)) /*!< Wakeup Flag for LLWU_P15 */
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#define LLWU_F2_WUF14 ((uint8_t)((uint8_t)1 << 6)) /*!< Wakeup Flag for LLWU_P14 */
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#define LLWU_F2_WUF13 ((uint8_t)((uint8_t)1 << 5)) /*!< Wakeup Flag for LLWU_P13 */
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#define LLWU_F2_WUF12 ((uint8_t)((uint8_t)1 << 4)) /*!< Wakeup Flag for LLWU_P12 */
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#define LLWU_F2_WUF11 ((uint8_t)((uint8_t)1 << 3)) /*!< Wakeup Flag for LLWU_P11 */
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#define LLWU_F2_WUF10 ((uint8_t)((uint8_t)1 << 2)) /*!< Wakeup Flag for LLWU_P10 */
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#define LLWU_F2_WUF9 ((uint8_t)((uint8_t)1 << 1)) /*!< Wakeup Flag for LLWU_P9 */
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#define LLWU_F2_WUF8 ((uint8_t)((uint8_t)1 << 0)) /*!< Wakeup Flag for LLWU_P8 */
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/********** Bits definition for LLWU_F3 register *************/
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#define LLWU_F3_MWUF7 ((uint8_t)((uint8_t)1 << 7)) /*!< Wakeup Flag for Module 7 */
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#define LLWU_F3_MWUF6 ((uint8_t)((uint8_t)1 << 6)) /*!< Wakeup Flag for Module 6 */
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#define LLWU_F3_MWUF5 ((uint8_t)((uint8_t)1 << 5)) /*!< Wakeup Flag for Module 5 */
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#define LLWU_F3_MWUF4 ((uint8_t)((uint8_t)1 << 4)) /*!< Wakeup Flag for Module 4 */
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#define LLWU_F3_MWUF3 ((uint8_t)((uint8_t)1 << 3)) /*!< Wakeup Flag for Module 3 */
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#define LLWU_F3_MWUF2 ((uint8_t)((uint8_t)1 << 2)) /*!< Wakeup Flag for Module 2 */
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#define LLWU_F3_MWUF1 ((uint8_t)((uint8_t)1 << 1)) /*!< Wakeup Flag for Module 1 */
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#define LLWU_F3_MWUF0 ((uint8_t)((uint8_t)1 << 0)) /*!< Wakeup Flag for Module 0 */
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/********** Bits definition for LLWU_FILT1 register *************/
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#define LLWU_FILT1_FILTF ((uint8_t)((uint8_t)1 << 7)) /*!< Filter Detect Flag */
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#define LLWU_FILT1_FILTE_SHIFT 5 /*!< Digital Filter on External Pin (shift) */
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#define LLWU_FILT1_FILTE_MASK ((uint8_t)((uint8_t)0x03 << LLWU_FILT1_FILTE_SHIFT)) /*!< Digital Filter on External Pin (mask) */
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#define LLWU_FILT1_FILTE(x) ((uint8_t)(((uint8_t)(x) << LLWU_FILT1_FILTE_SHIFT) & LLWU_FILT1_FILTE_MASK)) /*!< Digital Filter on External Pin */
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#define LLWU_FILT1_FILTE_DISABLED LLWU_FILT1_FILTE(0) /*!< Filter disabled */
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#define LLWU_FILT1_FILTE_POSEDGE LLWU_FILT1_FILTE(1) /*!< Filter posedge detect enabled */
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#define LLWU_FILT1_FILTE_NEGEDGE LLWU_FILT1_FILTE(2) /*!< Filter negedge detect enabled */
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#define LLWU_FILT1_FILTE_ANYEDGE LLWU_FILT1_FILTE(3) /*!< Filter any edge detect enabled */
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#define LLWU_FILT1_FILTSEL_SHIFT 0 /*!< Filter Pin Select (LLWU_P0 ... LLWU_P15) (shift) */
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#define LLWU_FILT1_FILTSEL_MASK ((uint8_t)((uint8_t)0x0F << LLWU_FILT1_FILTSEL_SHIFT)) /*!< Filter Pin Select (LLWU_P0 ... LLWU_P15) (mask) */
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#define LLWU_FILT1_FILTSEL(x) ((uint8_t)(((uint8_t)(x) << LLWU_FILT1_FILTSEL_SHIFT) & LLWU_FILT1_FILTSEL_MASK)) /*!< Filter Pin Select (LLWU_P0 ... LLWU_P15) */
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/********** Bits definition for LLWU_FILT2 register *************/
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#define LLWU_FILT2_FILTF ((uint8_t)((uint8_t)1 << 7)) /*!< Filter Detect Flag */
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#define LLWU_FILT2_FILTE_SHIFT 5 /*!< Digital Filter on External Pin (shift) */
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#define LLWU_FILT2_FILTE_MASK ((uint8_t)((uint8_t)0x03 << LLWU_FILT2_FILTE_SHIFT)) /*!< Digital Filter on External Pin (mask) */
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#define LLWU_FILT2_FILTE(x) ((uint8_t)(((uint8_t)(x) << LLWU_FILT2_FILTE_SHIFT) & LLWU_FILT2_FILTE_MASK)) /*!< Digital Filter on External Pin */
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#define LLWU_FILT2_FILTE_DISABLED LLWU_FILT2_FILTE(0) /*!< Filter disabled */
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#define LLWU_FILT2_FILTE_POSEDGE LLWU_FILT2_FILTE(1) /*!< Filter posedge detect enabled */
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#define LLWU_FILT2_FILTE_NEGEDGE LLWU_FILT2_FILTE(2) /*!< Filter negedge detect enabled */
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#define LLWU_FILT2_FILTE_ANYEDGE LLWU_FILT2_FILTE(3) /*!< Filter any edge detect enabled */
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#define LLWU_FILT2_FILTSEL_SHIFT 0 /*!< Filter Pin Select (LLWU_P0 ... LLWU_P15) (shift) */
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#define LLWU_FILT2_FILTSEL_MASK ((uint8_t)((uint8_t)0x0F << LLWU_FILT2_FILTSEL_SHIFT)) /*!< Filter Pin Select (LLWU_P0 ... LLWU_P15) (mask) */
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#define LLWU_FILT2_FILTSEL(x) ((uint8_t)(((uint8_t)(x) << LLWU_FILT2_FILTSEL_SHIFT) & LLWU_FILT2_FILTSEL_MASK)) /*!< Filter Pin Select (LLWU_P0 ... LLWU_P15) */
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/****************************************************************/
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/* */
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/* Port Control and interrupts (PORT) */
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/* */
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/****************************************************************/
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/******** Bits definition for PORTx_PCRn register *************/
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#define PORTx_PCRn_ISF ((uint32_t)0x01000000) /*!< Interrupt Status Flag */
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#define PORTx_PCRn_IRQC_SHIFT 16
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#define PORTx_PCRn_IRQC_MASK ((uint32_t)((uint32_t)0xF << PORTx_PCRn_IRQC_SHIFT))
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#define PORTx_PCRn_IRQC(x) ((uint32_t)(((uint32_t)(x) << PORTx_PCRn_IRQC_SHIFT) & PORTx_PCRn_IRQC_MASK))
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#define PORTx_PCRn_LK ((uint32_t)0x00008000) /*!< Lock Register */
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#define PORTx_PCRn_MUX_SHIFT 8 /*!< Pin Mux Control (shift) */
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#define PORTx_PCRn_MUX_MASK ((uint32_t)((uint32_t)0x7 << PORTx_PCRn_MUX_SHIFT)) /*!< Pin Mux Control (mask) */
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#define PORTx_PCRn_MUX(x) ((uint32_t)(((uint32_t)(x) << PORTx_PCRn_MUX_SHIFT) & PORTx_PCRn_MUX_MASK)) /*!< Pin Mux Control */
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#define PORTx_PCRn_DSE ((uint32_t)0x00000040) /*!< Drive Strength Enable */
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#define PORTx_PCRn_ODE ((uint32_t)0x00000020) /*!< Open Drain Enable */
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#define PORTx_PCRn_PFE ((uint32_t)0x00000010) /*!< Passive Filter Enable */
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#define PORTx_PCRn_SRE ((uint32_t)0x00000004) /*!< Slew Rate Enable */
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#define PORTx_PCRn_PE ((uint32_t)0x00000002) /*!< Pull Enable */
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#define PORTx_PCRn_PS ((uint32_t)0x00000001) /*!< Pull Select */
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/****************************************************************/
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/* */
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/* Oscillator (OSC) */
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/* */
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/****************************************************************/
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/*********** Bits definition for OSC_CR register **************/
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#define OSC_CR_ERCLKEN ((uint8_t)0x80) /*!< External Reference Enable */
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#define OSC_CR_EREFSTEN ((uint8_t)0x20) /*!< External Reference Stop Enable */
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#define OSC_CR_SC2P ((uint8_t)0x08) /*!< Oscillator 2pF Capacitor Load Configure */
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#define OSC_CR_SC4P ((uint8_t)0x04) /*!< Oscillator 4pF Capacitor Load Configure */
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#define OSC_CR_SC8P ((uint8_t)0x02) /*!< Oscillator 8pF Capacitor Load Configure */
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#define OSC_CR_SC16P ((uint8_t)0x01) /*!< Oscillator 16pF Capacitor Load Configure */
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/****************************************************************/
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/* */
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/* Direct Memory Access (DMA) */
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/* */
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/****************************************************************/
|
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/* ----------------------------------------------------------------------------
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-- DMA - Register accessor macros
|
|
---------------------------------------------------------------------------- */
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/*!
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* @addtogroup DMA_Register_Accessor_Macros DMA - Register accessor macros
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* @{
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*/
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/* DMA - Register accessors */
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#define DMA_CR_REG(base) ((base)->CR)
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#define DMA_ES_REG(base) ((base)->ES)
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#define DMA_ERQ_REG(base) ((base)->ERQ)
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#define DMA_EEI_REG(base) ((base)->EEI)
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#define DMA_CEEI_REG(base) ((base)->CEEI)
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#define DMA_SEEI_REG(base) ((base)->SEEI)
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#define DMA_CERQ_REG(base) ((base)->CERQ)
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#define DMA_SERQ_REG(base) ((base)->SERQ)
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#define DMA_CDNE_REG(base) ((base)->CDNE)
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#define DMA_SSRT_REG(base) ((base)->SSRT)
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#define DMA_CERR_REG(base) ((base)->CERR)
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#define DMA_CINT_REG(base) ((base)->CINT)
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#define DMA_INT_REG(base) ((base)->INT)
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#define DMA_ERR_REG(base) ((base)->ERR)
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#define DMA_HRS_REG(base) ((base)->HRS)
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#define DMA_DCHPRI3_REG(base) ((base)->DCHPRI3)
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#define DMA_DCHPRI2_REG(base) ((base)->DCHPRI2)
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#define DMA_DCHPRI1_REG(base) ((base)->DCHPRI1)
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#define DMA_DCHPRI0_REG(base) ((base)->DCHPRI0)
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#define DMA_SADDR_REG(base,index) ((base)->TCD[index].SADDR)
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#define DMA_SOFF_REG(base,index) ((base)->TCD[index].SOFF)
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#define DMA_ATTR_REG(base,index) ((base)->TCD[index].ATTR)
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#define DMA_NBYTES_MLNO_REG(base,index) ((base)->TCD[index].NBYTES_MLNO)
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#define DMA_NBYTES_MLOFFNO_REG(base,index) ((base)->TCD[index].NBYTES_MLOFFNO)
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#define DMA_NBYTES_MLOFFYES_REG(base,index) ((base)->TCD[index].NBYTES_MLOFFYES)
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#define DMA_SLAST_REG(base,index) ((base)->TCD[index].SLAST)
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#define DMA_DADDR_REG(base,index) ((base)->TCD[index].DADDR)
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#define DMA_DOFF_REG(base,index) ((base)->TCD[index].DOFF)
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#define DMA_CITER_ELINKNO_REG(base,index) ((base)->TCD[index].CITER_ELINKNO)
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#define DMA_CITER_ELINKYES_REG(base,index) ((base)->TCD[index].CITER_ELINKYES)
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#define DMA_DLAST_SGA_REG(base,index) ((base)->TCD[index].DLAST_SGA)
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#define DMA_CSR_REG(base,index) ((base)->TCD[index].CSR)
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#define DMA_BITER_ELINKNO_REG(base,index) ((base)->TCD[index].BITER_ELINKNO)
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#define DMA_BITER_ELINKYES_REG(base,index) ((base)->TCD[index].BITER_ELINKYES)
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/*!
|
|
* @}
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*/ /* end of group DMA_Register_Accessor_Macros */
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|
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|
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/* ----------------------------------------------------------------------------
|
|
-- DMA Register Masks
|
|
---------------------------------------------------------------------------- */
|
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|
|
/*!
|
|
* @addtogroup DMA_Register_Masks DMA Register Masks
|
|
* @{
|
|
*/
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|
|
/* CR Bit Fields */
|
|
#define DMA_CR_EDBG_MASK 0x2u
|
|
#define DMA_CR_EDBG_SHIFT 1
|
|
#define DMA_CR_ERCA_MASK 0x4u
|
|
#define DMA_CR_ERCA_SHIFT 2
|
|
#define DMA_CR_HOE_MASK 0x10u
|
|
#define DMA_CR_HOE_SHIFT 4
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|
#define DMA_CR_HALT_MASK 0x20u
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|
#define DMA_CR_HALT_SHIFT 5
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#define DMA_CR_CLM_MASK 0x40u
|
|
#define DMA_CR_CLM_SHIFT 6
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|
#define DMA_CR_EMLM_MASK 0x80u
|
|
#define DMA_CR_EMLM_SHIFT 7
|
|
#define DMA_CR_ECX_MASK 0x10000u
|
|
#define DMA_CR_ECX_SHIFT 16
|
|
#define DMA_CR_CX_MASK 0x20000u
|
|
#define DMA_CR_CX_SHIFT 17
|
|
/* ES Bit Fields */
|
|
#define DMA_ES_DBE_MASK 0x1u
|
|
#define DMA_ES_DBE_SHIFT 0
|
|
#define DMA_ES_SBE_MASK 0x2u
|
|
#define DMA_ES_SBE_SHIFT 1
|
|
#define DMA_ES_SGE_MASK 0x4u
|
|
#define DMA_ES_SGE_SHIFT 2
|
|
#define DMA_ES_NCE_MASK 0x8u
|
|
#define DMA_ES_NCE_SHIFT 3
|
|
#define DMA_ES_DOE_MASK 0x10u
|
|
#define DMA_ES_DOE_SHIFT 4
|
|
#define DMA_ES_DAE_MASK 0x20u
|
|
#define DMA_ES_DAE_SHIFT 5
|
|
#define DMA_ES_SOE_MASK 0x40u
|
|
#define DMA_ES_SOE_SHIFT 6
|
|
#define DMA_ES_SAE_MASK 0x80u
|
|
#define DMA_ES_SAE_SHIFT 7
|
|
#define DMA_ES_ERRCHN_MASK 0xF00u
|
|
#define DMA_ES_ERRCHN_SHIFT 8
|
|
#define DMA_ES_ERRCHN(x) (((uint32_t)(((uint32_t)(x))<<DMA_ES_ERRCHN_SHIFT))&DMA_ES_ERRCHN_MASK)
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|
#define DMA_ES_CPE_MASK 0x4000u
|
|
#define DMA_ES_CPE_SHIFT 14
|
|
#define DMA_ES_ECX_MASK 0x10000u
|
|
#define DMA_ES_ECX_SHIFT 16
|
|
#define DMA_ES_VLD_MASK 0x80000000u
|
|
#define DMA_ES_VLD_SHIFT 31
|
|
/* ERQ Bit Fields */
|
|
#define DMA_ERQ_ERQ0_MASK 0x1u
|
|
#define DMA_ERQ_ERQ0_SHIFT 0
|
|
#define DMA_ERQ_ERQ1_MASK 0x2u
|
|
#define DMA_ERQ_ERQ1_SHIFT 1
|
|
#define DMA_ERQ_ERQ2_MASK 0x4u
|
|
#define DMA_ERQ_ERQ2_SHIFT 2
|
|
#define DMA_ERQ_ERQ3_MASK 0x8u
|
|
#define DMA_ERQ_ERQ3_SHIFT 3
|
|
/* EEI Bit Fields */
|
|
#define DMA_EEI_EEI0_MASK 0x1u
|
|
#define DMA_EEI_EEI0_SHIFT 0
|
|
#define DMA_EEI_EEI1_MASK 0x2u
|
|
#define DMA_EEI_EEI1_SHIFT 1
|
|
#define DMA_EEI_EEI2_MASK 0x4u
|
|
#define DMA_EEI_EEI2_SHIFT 2
|
|
#define DMA_EEI_EEI3_MASK 0x8u
|
|
#define DMA_EEI_EEI3_SHIFT 3
|
|
/* CEEI Bit Fields */
|
|
#define DMA_CEEI_CEEI_MASK 0xFu
|
|
#define DMA_CEEI_CEEI_SHIFT 0
|
|
#define DMA_CEEI_CEEI(x) (((uint8_t)(((uint8_t)(x))<<DMA_CEEI_CEEI_SHIFT))&DMA_CEEI_CEEI_MASK)
|
|
#define DMA_CEEI_CAEE_MASK 0x40u
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#define DMA_CEEI_CAEE_SHIFT 6
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#define DMA_CEEI_NOP_MASK 0x80u
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#define DMA_CEEI_NOP_SHIFT 7
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/* SEEI Bit Fields */
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#define DMA_SEEI_SEEI_MASK 0xFu
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#define DMA_SEEI_SEEI_SHIFT 0
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#define DMA_SEEI_SEEI(x) (((uint8_t)(((uint8_t)(x))<<DMA_SEEI_SEEI_SHIFT))&DMA_SEEI_SEEI_MASK)
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#define DMA_SEEI_SAEE_MASK 0x40u
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#define DMA_SEEI_SAEE_SHIFT 6
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#define DMA_SEEI_NOP_MASK 0x80u
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#define DMA_SEEI_NOP_SHIFT 7
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/* CERQ Bit Fields */
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#define DMA_CERQ_CERQ_MASK 0xFu
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#define DMA_CERQ_CERQ_SHIFT 0
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#define DMA_CERQ_CERQ(x) (((uint8_t)(((uint8_t)(x))<<DMA_CERQ_CERQ_SHIFT))&DMA_CERQ_CERQ_MASK)
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#define DMA_CERQ_CAER_MASK 0x40u
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#define DMA_CERQ_CAER_SHIFT 6
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#define DMA_CERQ_NOP_MASK 0x80u
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#define DMA_CERQ_NOP_SHIFT 7
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/* SERQ Bit Fields */
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#define DMA_SERQ_SERQ_MASK 0xFu
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#define DMA_SERQ_SERQ_SHIFT 0
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#define DMA_SERQ_SERQ(x) (((uint8_t)(((uint8_t)(x))<<DMA_SERQ_SERQ_SHIFT))&DMA_SERQ_SERQ_MASK)
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#define DMA_SERQ_SAER_MASK 0x40u
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#define DMA_SERQ_SAER_SHIFT 6
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#define DMA_SERQ_NOP_MASK 0x80u
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#define DMA_SERQ_NOP_SHIFT 7
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/* CDNE Bit Fields */
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#define DMA_CDNE_CDNE_MASK 0xFu
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#define DMA_CDNE_CDNE_SHIFT 0
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#define DMA_CDNE_CDNE(x) (((uint8_t)(((uint8_t)(x))<<DMA_CDNE_CDNE_SHIFT))&DMA_CDNE_CDNE_MASK)
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#define DMA_CDNE_CADN_MASK 0x40u
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#define DMA_CDNE_CADN_SHIFT 6
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#define DMA_CDNE_NOP_MASK 0x80u
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#define DMA_CDNE_NOP_SHIFT 7
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/* SSRT Bit Fields */
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#define DMA_SSRT_SSRT_MASK 0xFu
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#define DMA_SSRT_SSRT_SHIFT 0
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#define DMA_SSRT_SSRT(x) (((uint8_t)(((uint8_t)(x))<<DMA_SSRT_SSRT_SHIFT))&DMA_SSRT_SSRT_MASK)
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#define DMA_SSRT_SAST_MASK 0x40u
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#define DMA_SSRT_SAST_SHIFT 6
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#define DMA_SSRT_NOP_MASK 0x80u
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#define DMA_SSRT_NOP_SHIFT 7
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/* CERR Bit Fields */
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#define DMA_CERR_CERR_MASK 0xFu
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#define DMA_CERR_CERR_SHIFT 0
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#define DMA_CERR_CERR(x) (((uint8_t)(((uint8_t)(x))<<DMA_CERR_CERR_SHIFT))&DMA_CERR_CERR_MASK)
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#define DMA_CERR_CAEI_MASK 0x40u
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#define DMA_CERR_CAEI_SHIFT 6
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#define DMA_CERR_NOP_MASK 0x80u
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#define DMA_CERR_NOP_SHIFT 7
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/* CINT Bit Fields */
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#define DMA_CINT_CINT_MASK 0xFu
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#define DMA_CINT_CINT_SHIFT 0
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#define DMA_CINT_CINT(x) (((uint8_t)(((uint8_t)(x))<<DMA_CINT_CINT_SHIFT))&DMA_CINT_CINT_MASK)
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#define DMA_CINT_CAIR_MASK 0x40u
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#define DMA_CINT_CAIR_SHIFT 6
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#define DMA_CINT_NOP_MASK 0x80u
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#define DMA_CINT_NOP_SHIFT 7
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/* INT Bit Fields */
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#define DMA_INT_INT0_MASK 0x1u
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#define DMA_INT_INT0_SHIFT 0
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#define DMA_INT_INT1_MASK 0x2u
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#define DMA_INT_INT1_SHIFT 1
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#define DMA_INT_INT2_MASK 0x4u
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#define DMA_INT_INT2_SHIFT 2
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#define DMA_INT_INT3_MASK 0x8u
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#define DMA_INT_INT3_SHIFT 3
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/* ERR Bit Fields */
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#define DMA_ERR_ERR0_MASK 0x1u
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#define DMA_ERR_ERR0_SHIFT 0
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#define DMA_ERR_ERR1_MASK 0x2u
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#define DMA_ERR_ERR1_SHIFT 1
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#define DMA_ERR_ERR2_MASK 0x4u
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#define DMA_ERR_ERR2_SHIFT 2
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#define DMA_ERR_ERR3_MASK 0x8u
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#define DMA_ERR_ERR3_SHIFT 3
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/* HRS Bit Fields */
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#define DMA_HRS_HRS0_MASK 0x1u
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#define DMA_HRS_HRS0_SHIFT 0
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#define DMA_HRS_HRS1_MASK 0x2u
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#define DMA_HRS_HRS1_SHIFT 1
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#define DMA_HRS_HRS2_MASK 0x4u
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#define DMA_HRS_HRS2_SHIFT 2
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#define DMA_HRS_HRS3_MASK 0x8u
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#define DMA_HRS_HRS3_SHIFT 3
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/* DCHPRI3 Bit Fields */
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#define DMA_DCHPRI3_CHPRI_MASK 0xFu
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#define DMA_DCHPRI3_CHPRI_SHIFT 0
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#define DMA_DCHPRI3_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI3_CHPRI_SHIFT))&DMA_DCHPRI3_CHPRI_MASK)
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#define DMA_DCHPRI3_DPA_MASK 0x40u
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#define DMA_DCHPRI3_DPA_SHIFT 6
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#define DMA_DCHPRI3_ECP_MASK 0x80u
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#define DMA_DCHPRI3_ECP_SHIFT 7
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/* DCHPRI2 Bit Fields */
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#define DMA_DCHPRI2_CHPRI_MASK 0xFu
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#define DMA_DCHPRI2_CHPRI_SHIFT 0
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#define DMA_DCHPRI2_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI2_CHPRI_SHIFT))&DMA_DCHPRI2_CHPRI_MASK)
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#define DMA_DCHPRI2_DPA_MASK 0x40u
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#define DMA_DCHPRI2_DPA_SHIFT 6
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#define DMA_DCHPRI2_ECP_MASK 0x80u
|
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#define DMA_DCHPRI2_ECP_SHIFT 7
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/* DCHPRI1 Bit Fields */
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#define DMA_DCHPRI1_CHPRI_MASK 0xFu
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#define DMA_DCHPRI1_CHPRI_SHIFT 0
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#define DMA_DCHPRI1_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI1_CHPRI_SHIFT))&DMA_DCHPRI1_CHPRI_MASK)
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#define DMA_DCHPRI1_DPA_MASK 0x40u
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|
#define DMA_DCHPRI1_DPA_SHIFT 6
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#define DMA_DCHPRI1_ECP_MASK 0x80u
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#define DMA_DCHPRI1_ECP_SHIFT 7
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/* DCHPRI0 Bit Fields */
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#define DMA_DCHPRI0_CHPRI_MASK 0xFu
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#define DMA_DCHPRI0_CHPRI_SHIFT 0
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#define DMA_DCHPRI0_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI0_CHPRI_SHIFT))&DMA_DCHPRI0_CHPRI_MASK)
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#define DMA_DCHPRI0_DPA_MASK 0x40u
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|
#define DMA_DCHPRI0_DPA_SHIFT 6
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#define DMA_DCHPRI0_ECP_MASK 0x80u
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|
#define DMA_DCHPRI0_ECP_SHIFT 7
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/* SADDR Bit Fields */
|
|
#define DMA_SADDR_SADDR_MASK 0xFFFFFFFFu
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#define DMA_SADDR_SADDR_SHIFT 0
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|
#define DMA_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x))<<DMA_SADDR_SADDR_SHIFT))&DMA_SADDR_SADDR_MASK)
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/* SOFF Bit Fields */
|
|
#define DMA_SOFF_SOFF_MASK 0xFFFFu
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#define DMA_SOFF_SOFF_SHIFT 0
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#define DMA_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x))<<DMA_SOFF_SOFF_SHIFT))&DMA_SOFF_SOFF_MASK)
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/* ATTR Bit Fields */
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|
#define DMA_ATTR_DSIZE_MASK 0x7u
|
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#define DMA_ATTR_DSIZE_SHIFT 0
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#define DMA_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_DSIZE_SHIFT))&DMA_ATTR_DSIZE_MASK)
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|
#define DMA_ATTR_DMOD_MASK 0xF8u
|
|
#define DMA_ATTR_DMOD_SHIFT 3
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|
#define DMA_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_DMOD_SHIFT))&DMA_ATTR_DMOD_MASK)
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#define DMA_ATTR_SSIZE_MASK 0x700u
|
|
#define DMA_ATTR_SSIZE_SHIFT 8
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#define DMA_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_SSIZE_SHIFT))&DMA_ATTR_SSIZE_MASK)
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#define DMA_ATTR_SMOD_MASK 0xF800u
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#define DMA_ATTR_SMOD_SHIFT 11
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#define DMA_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_SMOD_SHIFT))&DMA_ATTR_SMOD_MASK)
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/* NBYTES_MLNO Bit Fields */
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#define DMA_NBYTES_MLNO_NBYTES_MASK 0xFFFFFFFFu
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#define DMA_NBYTES_MLNO_NBYTES_SHIFT 0
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#define DMA_NBYTES_MLNO_NBYTES(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLNO_NBYTES_SHIFT))&DMA_NBYTES_MLNO_NBYTES_MASK)
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/* NBYTES_MLOFFNO Bit Fields */
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#define DMA_NBYTES_MLOFFNO_NBYTES_MASK 0x3FFFFFFFu
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#define DMA_NBYTES_MLOFFNO_NBYTES_SHIFT 0
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#define DMA_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFNO_NBYTES_SHIFT))&DMA_NBYTES_MLOFFNO_NBYTES_MASK)
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#define DMA_NBYTES_MLOFFNO_DMLOE_MASK 0x40000000u
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#define DMA_NBYTES_MLOFFNO_DMLOE_SHIFT 30
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#define DMA_NBYTES_MLOFFNO_SMLOE_MASK 0x80000000u
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#define DMA_NBYTES_MLOFFNO_SMLOE_SHIFT 31
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/* NBYTES_MLOFFYES Bit Fields */
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#define DMA_NBYTES_MLOFFYES_NBYTES_MASK 0x3FFu
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#define DMA_NBYTES_MLOFFYES_NBYTES_SHIFT 0
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#define DMA_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFYES_NBYTES_SHIFT))&DMA_NBYTES_MLOFFYES_NBYTES_MASK)
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#define DMA_NBYTES_MLOFFYES_MLOFF_MASK 0x3FFFFC00u
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#define DMA_NBYTES_MLOFFYES_MLOFF_SHIFT 10
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#define DMA_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFYES_MLOFF_SHIFT))&DMA_NBYTES_MLOFFYES_MLOFF_MASK)
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#define DMA_NBYTES_MLOFFYES_DMLOE_MASK 0x40000000u
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#define DMA_NBYTES_MLOFFYES_DMLOE_SHIFT 30
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#define DMA_NBYTES_MLOFFYES_SMLOE_MASK 0x80000000u
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#define DMA_NBYTES_MLOFFYES_SMLOE_SHIFT 31
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/* SLAST Bit Fields */
|
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#define DMA_SLAST_SLAST_MASK 0xFFFFFFFFu
|
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#define DMA_SLAST_SLAST_SHIFT 0
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#define DMA_SLAST_SLAST(x) (((uint32_t)(((uint32_t)(x))<<DMA_SLAST_SLAST_SHIFT))&DMA_SLAST_SLAST_MASK)
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/* DADDR Bit Fields */
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#define DMA_DADDR_DADDR_MASK 0xFFFFFFFFu
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#define DMA_DADDR_DADDR_SHIFT 0
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#define DMA_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x))<<DMA_DADDR_DADDR_SHIFT))&DMA_DADDR_DADDR_MASK)
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/* DOFF Bit Fields */
|
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#define DMA_DOFF_DOFF_MASK 0xFFFFu
|
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#define DMA_DOFF_DOFF_SHIFT 0
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#define DMA_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x))<<DMA_DOFF_DOFF_SHIFT))&DMA_DOFF_DOFF_MASK)
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/* CITER_ELINKNO Bit Fields */
|
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#define DMA_CITER_ELINKNO_CITER_MASK 0x7FFFu
|
|
#define DMA_CITER_ELINKNO_CITER_SHIFT 0
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#define DMA_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKNO_CITER_SHIFT))&DMA_CITER_ELINKNO_CITER_MASK)
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#define DMA_CITER_ELINKNO_ELINK_MASK 0x8000u
|
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#define DMA_CITER_ELINKNO_ELINK_SHIFT 15
|
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/* CITER_ELINKYES Bit Fields */
|
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#define DMA_CITER_ELINKYES_CITER_MASK 0x1FFu
|
|
#define DMA_CITER_ELINKYES_CITER_SHIFT 0
|
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#define DMA_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKYES_CITER_SHIFT))&DMA_CITER_ELINKYES_CITER_MASK)
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#define DMA_CITER_ELINKYES_LINKCH_MASK 0x1E00u
|
|
#define DMA_CITER_ELINKYES_LINKCH_SHIFT 9
|
|
#define DMA_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKYES_LINKCH_SHIFT))&DMA_CITER_ELINKYES_LINKCH_MASK)
|
|
#define DMA_CITER_ELINKYES_ELINK_MASK 0x8000u
|
|
#define DMA_CITER_ELINKYES_ELINK_SHIFT 15
|
|
/* DLAST_SGA Bit Fields */
|
|
#define DMA_DLAST_SGA_DLASTSGA_MASK 0xFFFFFFFFu
|
|
#define DMA_DLAST_SGA_DLASTSGA_SHIFT 0
|
|
#define DMA_DLAST_SGA_DLASTSGA(x) (((uint32_t)(((uint32_t)(x))<<DMA_DLAST_SGA_DLASTSGA_SHIFT))&DMA_DLAST_SGA_DLASTSGA_MASK)
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|
/* CSR Bit Fields */
|
|
#define DMA_CSR_START_MASK 0x1u
|
|
#define DMA_CSR_START_SHIFT 0
|
|
#define DMA_CSR_INTMAJOR_MASK 0x2u
|
|
#define DMA_CSR_INTMAJOR_SHIFT 1
|
|
#define DMA_CSR_INTHALF_MASK 0x4u
|
|
#define DMA_CSR_INTHALF_SHIFT 2
|
|
#define DMA_CSR_DREQ_MASK 0x8u
|
|
#define DMA_CSR_DREQ_SHIFT 3
|
|
#define DMA_CSR_ESG_MASK 0x10u
|
|
#define DMA_CSR_ESG_SHIFT 4
|
|
#define DMA_CSR_MAJORELINK_MASK 0x20u
|
|
#define DMA_CSR_MAJORELINK_SHIFT 5
|
|
#define DMA_CSR_ACTIVE_MASK 0x40u
|
|
#define DMA_CSR_ACTIVE_SHIFT 6
|
|
#define DMA_CSR_DONE_MASK 0x80u
|
|
#define DMA_CSR_DONE_SHIFT 7
|
|
#define DMA_CSR_MAJORLINKCH_MASK 0xF00u
|
|
#define DMA_CSR_MAJORLINKCH_SHIFT 8
|
|
#define DMA_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x))<<DMA_CSR_MAJORLINKCH_SHIFT))&DMA_CSR_MAJORLINKCH_MASK)
|
|
#define DMA_CSR_BWC_MASK 0xC000u
|
|
#define DMA_CSR_BWC_SHIFT 14
|
|
#define DMA_CSR_BWC(x) (((uint16_t)(((uint16_t)(x))<<DMA_CSR_BWC_SHIFT))&DMA_CSR_BWC_MASK)
|
|
/* BITER_ELINKNO Bit Fields */
|
|
#define DMA_BITER_ELINKNO_BITER_MASK 0x7FFFu
|
|
#define DMA_BITER_ELINKNO_BITER_SHIFT 0
|
|
#define DMA_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKNO_BITER_SHIFT))&DMA_BITER_ELINKNO_BITER_MASK)
|
|
#define DMA_BITER_ELINKNO_ELINK_MASK 0x8000u
|
|
#define DMA_BITER_ELINKNO_ELINK_SHIFT 15
|
|
/* BITER_ELINKYES Bit Fields */
|
|
#define DMA_BITER_ELINKYES_BITER_MASK 0x1FFu
|
|
#define DMA_BITER_ELINKYES_BITER_SHIFT 0
|
|
#define DMA_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKYES_BITER_SHIFT))&DMA_BITER_ELINKYES_BITER_MASK)
|
|
#define DMA_BITER_ELINKYES_LINKCH_MASK 0x1E00u
|
|
#define DMA_BITER_ELINKYES_LINKCH_SHIFT 9
|
|
#define DMA_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKYES_LINKCH_SHIFT))&DMA_BITER_ELINKYES_LINKCH_MASK)
|
|
#define DMA_BITER_ELINKYES_ELINK_MASK 0x8000u
|
|
#define DMA_BITER_ELINKYES_ELINK_SHIFT 15
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group DMA_Register_Masks */
|
|
|
|
|
|
/* DMA - Peripheral instance base addresses */
|
|
/** Peripheral DMA base pointer */
|
|
#define DMA_BASE_PTR ((DMA_MemMapPtr)0x40008000u)
|
|
/** Array initializer of DMA peripheral base pointers */
|
|
#define DMA_BASE_PTRS { DMA_BASE_PTR }
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- DMA - Register accessor macros
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup DMA_Register_Accessor_Macros DMA - Register accessor macros
|
|
* @{
|
|
*/
|
|
|
|
|
|
/* DMA - Register instance definitions */
|
|
/* DMA */
|
|
#define DMA_CR DMA_CR_REG(DMA_BASE_PTR)
|
|
#define DMA_ES DMA_ES_REG(DMA_BASE_PTR)
|
|
#define DMA_ERQ DMA_ERQ_REG(DMA_BASE_PTR)
|
|
#define DMA_EEI DMA_EEI_REG(DMA_BASE_PTR)
|
|
#define DMA_CEEI DMA_CEEI_REG(DMA_BASE_PTR)
|
|
#define DMA_SEEI DMA_SEEI_REG(DMA_BASE_PTR)
|
|
#define DMA_CERQ DMA_CERQ_REG(DMA_BASE_PTR)
|
|
#define DMA_SERQ DMA_SERQ_REG(DMA_BASE_PTR)
|
|
#define DMA_CDNE DMA_CDNE_REG(DMA_BASE_PTR)
|
|
#define DMA_SSRT DMA_SSRT_REG(DMA_BASE_PTR)
|
|
#define DMA_CERR DMA_CERR_REG(DMA_BASE_PTR)
|
|
#define DMA_CINT DMA_CINT_REG(DMA_BASE_PTR)
|
|
#define DMA_INT DMA_INT_REG(DMA_BASE_PTR)
|
|
#define DMA_ERR DMA_ERR_REG(DMA_BASE_PTR)
|
|
#define DMA_HRS DMA_HRS_REG(DMA_BASE_PTR)
|
|
#define DMA_DCHPRI3 DMA_DCHPRI3_REG(DMA_BASE_PTR)
|
|
#define DMA_DCHPRI2 DMA_DCHPRI2_REG(DMA_BASE_PTR)
|
|
#define DMA_DCHPRI1 DMA_DCHPRI1_REG(DMA_BASE_PTR)
|
|
#define DMA_DCHPRI0 DMA_DCHPRI0_REG(DMA_BASE_PTR)
|
|
#define DMA_TCD0_SADDR DMA_SADDR_REG(DMA_BASE_PTR,0)
|
|
#define DMA_TCD0_SOFF DMA_SOFF_REG(DMA_BASE_PTR,0)
|
|
#define DMA_TCD0_ATTR DMA_ATTR_REG(DMA_BASE_PTR,0)
|
|
#define DMA_TCD0_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA_BASE_PTR,0)
|
|
#define DMA_TCD0_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA_BASE_PTR,0)
|
|
#define DMA_TCD0_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA_BASE_PTR,0)
|
|
#define DMA_TCD0_SLAST DMA_SLAST_REG(DMA_BASE_PTR,0)
|
|
#define DMA_TCD0_DADDR DMA_DADDR_REG(DMA_BASE_PTR,0)
|
|
#define DMA_TCD0_DOFF DMA_DOFF_REG(DMA_BASE_PTR,0)
|
|
#define DMA_TCD0_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA_BASE_PTR,0)
|
|
#define DMA_TCD0_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA_BASE_PTR,0)
|
|
#define DMA_TCD0_DLASTSGA DMA_DLAST_SGA_REG(DMA_BASE_PTR,0)
|
|
#define DMA_TCD0_CSR DMA_CSR_REG(DMA_BASE_PTR,0)
|
|
#define DMA_TCD0_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA_BASE_PTR,0)
|
|
#define DMA_TCD0_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA_BASE_PTR,0)
|
|
#define DMA_TCD1_SADDR DMA_SADDR_REG(DMA_BASE_PTR,1)
|
|
#define DMA_TCD1_SOFF DMA_SOFF_REG(DMA_BASE_PTR,1)
|
|
#define DMA_TCD1_ATTR DMA_ATTR_REG(DMA_BASE_PTR,1)
|
|
#define DMA_TCD1_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA_BASE_PTR,1)
|
|
#define DMA_TCD1_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA_BASE_PTR,1)
|
|
#define DMA_TCD1_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA_BASE_PTR,1)
|
|
#define DMA_TCD1_SLAST DMA_SLAST_REG(DMA_BASE_PTR,1)
|
|
#define DMA_TCD1_DADDR DMA_DADDR_REG(DMA_BASE_PTR,1)
|
|
#define DMA_TCD1_DOFF DMA_DOFF_REG(DMA_BASE_PTR,1)
|
|
#define DMA_TCD1_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA_BASE_PTR,1)
|
|
#define DMA_TCD1_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA_BASE_PTR,1)
|
|
#define DMA_TCD1_DLASTSGA DMA_DLAST_SGA_REG(DMA_BASE_PTR,1)
|
|
#define DMA_TCD1_CSR DMA_CSR_REG(DMA_BASE_PTR,1)
|
|
#define DMA_TCD1_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA_BASE_PTR,1)
|
|
#define DMA_TCD1_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA_BASE_PTR,1)
|
|
#define DMA_TCD2_SADDR DMA_SADDR_REG(DMA_BASE_PTR,2)
|
|
#define DMA_TCD2_SOFF DMA_SOFF_REG(DMA_BASE_PTR,2)
|
|
#define DMA_TCD2_ATTR DMA_ATTR_REG(DMA_BASE_PTR,2)
|
|
#define DMA_TCD2_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA_BASE_PTR,2)
|
|
#define DMA_TCD2_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA_BASE_PTR,2)
|
|
#define DMA_TCD2_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA_BASE_PTR,2)
|
|
#define DMA_TCD2_SLAST DMA_SLAST_REG(DMA_BASE_PTR,2)
|
|
#define DMA_TCD2_DADDR DMA_DADDR_REG(DMA_BASE_PTR,2)
|
|
#define DMA_TCD2_DOFF DMA_DOFF_REG(DMA_BASE_PTR,2)
|
|
#define DMA_TCD2_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA_BASE_PTR,2)
|
|
#define DMA_TCD2_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA_BASE_PTR,2)
|
|
#define DMA_TCD2_DLASTSGA DMA_DLAST_SGA_REG(DMA_BASE_PTR,2)
|
|
#define DMA_TCD2_CSR DMA_CSR_REG(DMA_BASE_PTR,2)
|
|
#define DMA_TCD2_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA_BASE_PTR,2)
|
|
#define DMA_TCD2_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA_BASE_PTR,2)
|
|
#define DMA_TCD3_SADDR DMA_SADDR_REG(DMA_BASE_PTR,3)
|
|
#define DMA_TCD3_SOFF DMA_SOFF_REG(DMA_BASE_PTR,3)
|
|
#define DMA_TCD3_ATTR DMA_ATTR_REG(DMA_BASE_PTR,3)
|
|
#define DMA_TCD3_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA_BASE_PTR,3)
|
|
#define DMA_TCD3_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA_BASE_PTR,3)
|
|
#define DMA_TCD3_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA_BASE_PTR,3)
|
|
#define DMA_TCD3_SLAST DMA_SLAST_REG(DMA_BASE_PTR,3)
|
|
#define DMA_TCD3_DADDR DMA_DADDR_REG(DMA_BASE_PTR,3)
|
|
#define DMA_TCD3_DOFF DMA_DOFF_REG(DMA_BASE_PTR,3)
|
|
#define DMA_TCD3_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA_BASE_PTR,3)
|
|
#define DMA_TCD3_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA_BASE_PTR,3)
|
|
#define DMA_TCD3_DLASTSGA DMA_DLAST_SGA_REG(DMA_BASE_PTR,3)
|
|
#define DMA_TCD3_CSR DMA_CSR_REG(DMA_BASE_PTR,3)
|
|
#define DMA_TCD3_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA_BASE_PTR,3)
|
|
#define DMA_TCD3_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA_BASE_PTR,3)
|
|
|
|
/* DMA - Register array accessors */
|
|
#define DMA_SADDR(index) DMA_SADDR_REG(DMA_BASE_PTR,index)
|
|
#define DMA_SOFF(index) DMA_SOFF_REG(DMA_BASE_PTR,index)
|
|
#define DMA_ATTR(index) DMA_ATTR_REG(DMA_BASE_PTR,index)
|
|
#define DMA_NBYTES_MLNO(index) DMA_NBYTES_MLNO_REG(DMA_BASE_PTR,index)
|
|
#define DMA_NBYTES_MLOFFNO(index) DMA_NBYTES_MLOFFNO_REG(DMA_BASE_PTR,index)
|
|
#define DMA_NBYTES_MLOFFYES(index) DMA_NBYTES_MLOFFYES_REG(DMA_BASE_PTR,index)
|
|
#define DMA_SLAST(index) DMA_SLAST_REG(DMA_BASE_PTR,index)
|
|
#define DMA_DADDR(index) DMA_DADDR_REG(DMA_BASE_PTR,index)
|
|
#define DMA_DOFF(index) DMA_DOFF_REG(DMA_BASE_PTR,index)
|
|
#define DMA_CITER_ELINKNO(index) DMA_CITER_ELINKNO_REG(DMA_BASE_PTR,index)
|
|
#define DMA_CITER_ELINKYES(index) DMA_CITER_ELINKYES_REG(DMA_BASE_PTR,index)
|
|
#define DMA_DLAST_SGA(index) DMA_DLAST_SGA_REG(DMA_BASE_PTR,index)
|
|
#define DMA_CSR(index) DMA_CSR_REG(DMA_BASE_PTR,index)
|
|
#define DMA_BITER_ELINKNO(index) DMA_BITER_ELINKNO_REG(DMA_BASE_PTR,index)
|
|
#define DMA_BITER_ELINKYES(index) DMA_BITER_ELINKYES_REG(DMA_BASE_PTR,index)
|
|
|
|
/****************************************************************/
|
|
/* */
|
|
/* Direct Memory Access Multiplexer (DMAMUX) */
|
|
/* */
|
|
/****************************************************************/
|
|
/******** Bits definition for DMAMUX_CHCFGn register **********/
|
|
#define DMAMUX_CHCFGn_ENBL ((uint8_t)((uint8_t)1 << 7)) /*!< DMA Channel Enable */
|
|
#define DMAMUX_CHCFGn_TRIG ((uint8_t)((uint8_t)1 << 6)) /*!< DMA Channel Trigger Enable */
|
|
#define DMAMUX_CHCFGn_SOURCE_SHIFT 0 /*!< DMA Channel Source (Slot) (shift) */
|
|
#define DMAMUX_CHCFGn_SOURCE_MASK ((uint8_t)((uint8_t)0x3F << DMAMUX_CHCFGn_SOURCE_SHIFT)) /*!< DMA Channel Source (Slot) (mask) */
|
|
#define DMAMUX_CHCFGn_SOURCE(x) ((uint8_t)(((uint8_t)(x) << DMAMUX_CHCFGn_SOURCE_SHIFT) & DMAMUX_CHCFGn_SOURCE_MASK)) /*!< DMA Channel Source (Slot) */
|
|
|
|
/****************************************************************/
|
|
/* */
|
|
/* FlexTimer Module (FTM) */
|
|
/* */
|
|
/****************************************************************/
|
|
|
|
/* SC Bit Fields */
|
|
#define FTM_SC_PS_MASK 0x7u
|
|
#define FTM_SC_PS_SHIFT 0
|
|
#define FTM_SC_PS(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_PS_SHIFT))&FTM_SC_PS_MASK)
|
|
#define FTM_SC_CLKS_MASK 0x18u
|
|
#define FTM_SC_CLKS_SHIFT 3
|
|
#define FTM_SC_CLKS(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_CLKS_SHIFT))&FTM_SC_CLKS_MASK)
|
|
#define FTM_SC_CPWMS 0x20u
|
|
#define FTM_SC_TOIE 0x40u
|
|
#define FTM_SC_TOF 0x80u
|
|
/* CNT Bit Fields */
|
|
#define FTM_CNT_COUNT_MASK 0xFFFFu
|
|
#define FTM_CNT_COUNT_SHIFT 0
|
|
#define FTM_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x))<<FTM_CNT_COUNT_SHIFT))&FTM_CNT_COUNT_MASK)
|
|
/* MOD Bit Fields */
|
|
#define FTM_MOD_MOD_MASK 0xFFFFu
|
|
#define FTM_MOD_MOD_SHIFT 0
|
|
#define FTM_MOD_MOD(x) (((uint32_t)(((uint32_t)(x))<<FTM_MOD_MOD_SHIFT))&FTM_MOD_MOD_MASK)
|
|
/* CnSC Bit Fields */
|
|
#define FTM_CnSC_DMA 0x1u
|
|
#define FTM_CnSC_ELSA 0x4u
|
|
#define FTM_CnSC_ELSB 0x8u
|
|
#define FTM_CnSC_MSA 0x10u
|
|
#define FTM_CnSC_MSB 0x20u
|
|
#define FTM_CnSC_CHIE 0x40u
|
|
#define FTM_CnSC_CHF 0x80u
|
|
/* CnV Bit Fields */
|
|
#define FTM_CnV_VAL_MASK 0xFFFFu
|
|
#define FTM_CnV_VAL_SHIFT 0
|
|
#define FTM_CnV_VAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_CnV_VAL_SHIFT))&FTM_CnV_VAL_MASK)
|
|
/* CNTIN Bit Fields */
|
|
#define FTM_CNTIN_INIT_MASK 0xFFFFu
|
|
#define FTM_CNTIN_INIT_SHIFT 0
|
|
#define FTM_CNTIN_INIT(x) (((uint32_t)(((uint32_t)(x))<<FTM_CNTIN_INIT_SHIFT))&FTM_CNTIN_INIT_MASK)
|
|
/* STATUS Bit Fields */
|
|
#define FTM_STATUS_CH0F_MASK 0x1u
|
|
#define FTM_STATUS_CH0F_SHIFT 0
|
|
#define FTM_STATUS_CH1F_MASK 0x2u
|
|
#define FTM_STATUS_CH1F_SHIFT 1
|
|
#define FTM_STATUS_CH2F_MASK 0x4u
|
|
#define FTM_STATUS_CH2F_SHIFT 2
|
|
#define FTM_STATUS_CH3F_MASK 0x8u
|
|
#define FTM_STATUS_CH3F_SHIFT 3
|
|
#define FTM_STATUS_CH4F_MASK 0x10u
|
|
#define FTM_STATUS_CH4F_SHIFT 4
|
|
#define FTM_STATUS_CH5F_MASK 0x20u
|
|
#define FTM_STATUS_CH5F_SHIFT 5
|
|
#define FTM_STATUS_CH6F_MASK 0x40u
|
|
#define FTM_STATUS_CH6F_SHIFT 6
|
|
#define FTM_STATUS_CH7F_MASK 0x80u
|
|
#define FTM_STATUS_CH7F_SHIFT 7
|
|
/* MODE Bit Fields */
|
|
#define FTM_MODE_FTMEN_MASK 0x1u
|
|
#define FTM_MODE_FTMEN_SHIFT 0
|
|
#define FTM_MODE_INIT_MASK 0x2u
|
|
#define FTM_MODE_INIT_SHIFT 1
|
|
#define FTM_MODE_WPDIS_MASK 0x4u
|
|
#define FTM_MODE_WPDIS_SHIFT 2
|
|
#define FTM_MODE_PWMSYNC_MASK 0x8u
|
|
#define FTM_MODE_PWMSYNC_SHIFT 3
|
|
#define FTM_MODE_CAPTEST_MASK 0x10u
|
|
#define FTM_MODE_CAPTEST_SHIFT 4
|
|
#define FTM_MODE_FAULTM_MASK 0x60u
|
|
#define FTM_MODE_FAULTM_SHIFT 5
|
|
#define FTM_MODE_FAULTM(x) (((uint32_t)(((uint32_t)(x))<<FTM_MODE_FAULTM_SHIFT))&FTM_MODE_FAULTM_MASK)
|
|
#define FTM_MODE_FAULTIE_MASK 0x80u
|
|
#define FTM_MODE_FAULTIE_SHIFT 7
|
|
/* SYNC Bit Fields */
|
|
#define FTM_SYNC_CNTMIN_MASK 0x1u
|
|
#define FTM_SYNC_CNTMIN_SHIFT 0
|
|
#define FTM_SYNC_CNTMAX_MASK 0x2u
|
|
#define FTM_SYNC_CNTMAX_SHIFT 1
|
|
#define FTM_SYNC_REINIT_MASK 0x4u
|
|
#define FTM_SYNC_REINIT_SHIFT 2
|
|
#define FTM_SYNC_SYNCHOM_MASK 0x8u
|
|
#define FTM_SYNC_SYNCHOM_SHIFT 3
|
|
#define FTM_SYNC_TRIG0_MASK 0x10u
|
|
#define FTM_SYNC_TRIG0_SHIFT 4
|
|
#define FTM_SYNC_TRIG1_MASK 0x20u
|
|
#define FTM_SYNC_TRIG1_SHIFT 5
|
|
#define FTM_SYNC_TRIG2_MASK 0x40u
|
|
#define FTM_SYNC_TRIG2_SHIFT 6
|
|
#define FTM_SYNC_SWSYNC_MASK 0x80u
|
|
#define FTM_SYNC_SWSYNC_SHIFT 7
|
|
/* OUTINIT Bit Fields */
|
|
#define FTM_OUTINIT_CH0OI_MASK 0x1u
|
|
#define FTM_OUTINIT_CH0OI_SHIFT 0
|
|
#define FTM_OUTINIT_CH1OI_MASK 0x2u
|
|
#define FTM_OUTINIT_CH1OI_SHIFT 1
|
|
#define FTM_OUTINIT_CH2OI_MASK 0x4u
|
|
#define FTM_OUTINIT_CH2OI_SHIFT 2
|
|
#define FTM_OUTINIT_CH3OI_MASK 0x8u
|
|
#define FTM_OUTINIT_CH3OI_SHIFT 3
|
|
#define FTM_OUTINIT_CH4OI_MASK 0x10u
|
|
#define FTM_OUTINIT_CH4OI_SHIFT 4
|
|
#define FTM_OUTINIT_CH5OI_MASK 0x20u
|
|
#define FTM_OUTINIT_CH5OI_SHIFT 5
|
|
#define FTM_OUTINIT_CH6OI_MASK 0x40u
|
|
#define FTM_OUTINIT_CH6OI_SHIFT 6
|
|
#define FTM_OUTINIT_CH7OI_MASK 0x80u
|
|
#define FTM_OUTINIT_CH7OI_SHIFT 7
|
|
/* OUTMASK Bit Fields */
|
|
#define FTM_OUTMASK_CH0OM_MASK 0x1u
|
|
#define FTM_OUTMASK_CH0OM_SHIFT 0
|
|
#define FTM_OUTMASK_CH1OM_MASK 0x2u
|
|
#define FTM_OUTMASK_CH1OM_SHIFT 1
|
|
#define FTM_OUTMASK_CH2OM_MASK 0x4u
|
|
#define FTM_OUTMASK_CH2OM_SHIFT 2
|
|
#define FTM_OUTMASK_CH3OM_MASK 0x8u
|
|
#define FTM_OUTMASK_CH3OM_SHIFT 3
|
|
#define FTM_OUTMASK_CH4OM_MASK 0x10u
|
|
#define FTM_OUTMASK_CH4OM_SHIFT 4
|
|
#define FTM_OUTMASK_CH5OM_MASK 0x20u
|
|
#define FTM_OUTMASK_CH5OM_SHIFT 5
|
|
#define FTM_OUTMASK_CH6OM_MASK 0x40u
|
|
#define FTM_OUTMASK_CH6OM_SHIFT 6
|
|
#define FTM_OUTMASK_CH7OM_MASK 0x80u
|
|
#define FTM_OUTMASK_CH7OM_SHIFT 7
|
|
/* COMBINE Bit Fields */
|
|
#define FTM_COMBINE_COMBINE0_MASK 0x1u
|
|
#define FTM_COMBINE_COMBINE0_SHIFT 0
|
|
#define FTM_COMBINE_COMP0_MASK 0x2u
|
|
#define FTM_COMBINE_COMP0_SHIFT 1
|
|
#define FTM_COMBINE_DECAPEN0_MASK 0x4u
|
|
#define FTM_COMBINE_DECAPEN0_SHIFT 2
|
|
#define FTM_COMBINE_DECAP0_MASK 0x8u
|
|
#define FTM_COMBINE_DECAP0_SHIFT 3
|
|
#define FTM_COMBINE_DTEN0_MASK 0x10u
|
|
#define FTM_COMBINE_DTEN0_SHIFT 4
|
|
#define FTM_COMBINE_SYNCEN0_MASK 0x20u
|
|
#define FTM_COMBINE_SYNCEN0_SHIFT 5
|
|
#define FTM_COMBINE_FAULTEN0_MASK 0x40u
|
|
#define FTM_COMBINE_FAULTEN0_SHIFT 6
|
|
#define FTM_COMBINE_COMBINE1_MASK 0x100u
|
|
#define FTM_COMBINE_COMBINE1_SHIFT 8
|
|
#define FTM_COMBINE_COMP1_MASK 0x200u
|
|
#define FTM_COMBINE_COMP1_SHIFT 9
|
|
#define FTM_COMBINE_DECAPEN1_MASK 0x400u
|
|
#define FTM_COMBINE_DECAPEN1_SHIFT 10
|
|
#define FTM_COMBINE_DECAP1_MASK 0x800u
|
|
#define FTM_COMBINE_DECAP1_SHIFT 11
|
|
#define FTM_COMBINE_DTEN1_MASK 0x1000u
|
|
#define FTM_COMBINE_DTEN1_SHIFT 12
|
|
#define FTM_COMBINE_SYNCEN1_MASK 0x2000u
|
|
#define FTM_COMBINE_SYNCEN1_SHIFT 13
|
|
#define FTM_COMBINE_FAULTEN1_MASK 0x4000u
|
|
#define FTM_COMBINE_FAULTEN1_SHIFT 14
|
|
#define FTM_COMBINE_COMBINE2_MASK 0x10000u
|
|
#define FTM_COMBINE_COMBINE2_SHIFT 16
|
|
#define FTM_COMBINE_COMP2_MASK 0x20000u
|
|
#define FTM_COMBINE_COMP2_SHIFT 17
|
|
#define FTM_COMBINE_DECAPEN2_MASK 0x40000u
|
|
#define FTM_COMBINE_DECAPEN2_SHIFT 18
|
|
#define FTM_COMBINE_DECAP2_MASK 0x80000u
|
|
#define FTM_COMBINE_DECAP2_SHIFT 19
|
|
#define FTM_COMBINE_DTEN2_MASK 0x100000u
|
|
#define FTM_COMBINE_DTEN2_SHIFT 20
|
|
#define FTM_COMBINE_SYNCEN2_MASK 0x200000u
|
|
#define FTM_COMBINE_SYNCEN2_SHIFT 21
|
|
#define FTM_COMBINE_FAULTEN2_MASK 0x400000u
|
|
#define FTM_COMBINE_FAULTEN2_SHIFT 22
|
|
#define FTM_COMBINE_COMBINE3_MASK 0x1000000u
|
|
#define FTM_COMBINE_COMBINE3_SHIFT 24
|
|
#define FTM_COMBINE_COMP3_MASK 0x2000000u
|
|
#define FTM_COMBINE_COMP3_SHIFT 25
|
|
#define FTM_COMBINE_DECAPEN3_MASK 0x4000000u
|
|
#define FTM_COMBINE_DECAPEN3_SHIFT 26
|
|
#define FTM_COMBINE_DECAP3_MASK 0x8000000u
|
|
#define FTM_COMBINE_DECAP3_SHIFT 27
|
|
#define FTM_COMBINE_DTEN3_MASK 0x10000000u
|
|
#define FTM_COMBINE_DTEN3_SHIFT 28
|
|
#define FTM_COMBINE_SYNCEN3_MASK 0x20000000u
|
|
#define FTM_COMBINE_SYNCEN3_SHIFT 29
|
|
#define FTM_COMBINE_FAULTEN3_MASK 0x40000000u
|
|
#define FTM_COMBINE_FAULTEN3_SHIFT 30
|
|
/* DEADTIME Bit Fields */
|
|
#define FTM_DEADTIME_DTVAL_MASK 0x3Fu
|
|
#define FTM_DEADTIME_DTVAL_SHIFT 0
|
|
#define FTM_DEADTIME_DTVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_DEADTIME_DTVAL_SHIFT))&FTM_DEADTIME_DTVAL_MASK)
|
|
#define FTM_DEADTIME_DTPS_MASK 0xC0u
|
|
#define FTM_DEADTIME_DTPS_SHIFT 6
|
|
#define FTM_DEADTIME_DTPS(x) (((uint32_t)(((uint32_t)(x))<<FTM_DEADTIME_DTPS_SHIFT))&FTM_DEADTIME_DTPS_MASK)
|
|
/* EXTTRIG Bit Fields */
|
|
#define FTM_EXTTRIG_CH2TRIG_MASK 0x1u
|
|
#define FTM_EXTTRIG_CH2TRIG_SHIFT 0
|
|
#define FTM_EXTTRIG_CH3TRIG_MASK 0x2u
|
|
#define FTM_EXTTRIG_CH3TRIG_SHIFT 1
|
|
#define FTM_EXTTRIG_CH4TRIG_MASK 0x4u
|
|
#define FTM_EXTTRIG_CH4TRIG_SHIFT 2
|
|
#define FTM_EXTTRIG_CH5TRIG_MASK 0x8u
|
|
#define FTM_EXTTRIG_CH5TRIG_SHIFT 3
|
|
#define FTM_EXTTRIG_CH0TRIG_MASK 0x10u
|
|
#define FTM_EXTTRIG_CH0TRIG_SHIFT 4
|
|
#define FTM_EXTTRIG_CH1TRIG_MASK 0x20u
|
|
#define FTM_EXTTRIG_CH1TRIG_SHIFT 5
|
|
#define FTM_EXTTRIG_INITTRIGEN_MASK 0x40u
|
|
#define FTM_EXTTRIG_INITTRIGEN_SHIFT 6
|
|
#define FTM_EXTTRIG_TRIGF_MASK 0x80u
|
|
#define FTM_EXTTRIG_TRIGF_SHIFT 7
|
|
/* POL Bit Fields */
|
|
#define FTM_POL_POL0_MASK 0x1u
|
|
#define FTM_POL_POL0_SHIFT 0
|
|
#define FTM_POL_POL1_MASK 0x2u
|
|
#define FTM_POL_POL1_SHIFT 1
|
|
#define FTM_POL_POL2_MASK 0x4u
|
|
#define FTM_POL_POL2_SHIFT 2
|
|
#define FTM_POL_POL3_MASK 0x8u
|
|
#define FTM_POL_POL3_SHIFT 3
|
|
#define FTM_POL_POL4_MASK 0x10u
|
|
#define FTM_POL_POL4_SHIFT 4
|
|
#define FTM_POL_POL5_MASK 0x20u
|
|
#define FTM_POL_POL5_SHIFT 5
|
|
#define FTM_POL_POL6_MASK 0x40u
|
|
#define FTM_POL_POL6_SHIFT 6
|
|
#define FTM_POL_POL7_MASK 0x80u
|
|
#define FTM_POL_POL7_SHIFT 7
|
|
/* FMS Bit Fields */
|
|
#define FTM_FMS_FAULTF0_MASK 0x1u
|
|
#define FTM_FMS_FAULTF0_SHIFT 0
|
|
#define FTM_FMS_FAULTF1_MASK 0x2u
|
|
#define FTM_FMS_FAULTF1_SHIFT 1
|
|
#define FTM_FMS_FAULTF2_MASK 0x4u
|
|
#define FTM_FMS_FAULTF2_SHIFT 2
|
|
#define FTM_FMS_FAULTF3_MASK 0x8u
|
|
#define FTM_FMS_FAULTF3_SHIFT 3
|
|
#define FTM_FMS_FAULTIN_MASK 0x20u
|
|
#define FTM_FMS_FAULTIN_SHIFT 5
|
|
#define FTM_FMS_WPEN_MASK 0x40u
|
|
#define FTM_FMS_WPEN_SHIFT 6
|
|
#define FTM_FMS_FAULTF_MASK 0x80u
|
|
#define FTM_FMS_FAULTF_SHIFT 7
|
|
/* FILTER Bit Fields */
|
|
#define FTM_FILTER_CH0FVAL_MASK 0xFu
|
|
#define FTM_FILTER_CH0FVAL_SHIFT 0
|
|
#define FTM_FILTER_CH0FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH0FVAL_SHIFT))&FTM_FILTER_CH0FVAL_MASK)
|
|
#define FTM_FILTER_CH1FVAL_MASK 0xF0u
|
|
#define FTM_FILTER_CH1FVAL_SHIFT 4
|
|
#define FTM_FILTER_CH1FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH1FVAL_SHIFT))&FTM_FILTER_CH1FVAL_MASK)
|
|
#define FTM_FILTER_CH2FVAL_MASK 0xF00u
|
|
#define FTM_FILTER_CH2FVAL_SHIFT 8
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#define FTM_FILTER_CH2FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH2FVAL_SHIFT))&FTM_FILTER_CH2FVAL_MASK)
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#define FTM_FILTER_CH3FVAL_MASK 0xF000u
|
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#define FTM_FILTER_CH3FVAL_SHIFT 12
|
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#define FTM_FILTER_CH3FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH3FVAL_SHIFT))&FTM_FILTER_CH3FVAL_MASK)
|
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/* FLTCTRL Bit Fields */
|
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#define FTM_FLTCTRL_FAULT0EN_MASK 0x1u
|
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#define FTM_FLTCTRL_FAULT0EN_SHIFT 0
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#define FTM_FLTCTRL_FAULT1EN_MASK 0x2u
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#define FTM_FLTCTRL_FAULT1EN_SHIFT 1
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#define FTM_FLTCTRL_FAULT2EN_MASK 0x4u
|
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#define FTM_FLTCTRL_FAULT2EN_SHIFT 2
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#define FTM_FLTCTRL_FAULT3EN_MASK 0x8u
|
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#define FTM_FLTCTRL_FAULT3EN_SHIFT 3
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#define FTM_FLTCTRL_FFLTR0EN_MASK 0x10u
|
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#define FTM_FLTCTRL_FFLTR0EN_SHIFT 4
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#define FTM_FLTCTRL_FFLTR1EN_MASK 0x20u
|
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#define FTM_FLTCTRL_FFLTR1EN_SHIFT 5
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#define FTM_FLTCTRL_FFLTR2EN_MASK 0x40u
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#define FTM_FLTCTRL_FFLTR2EN_SHIFT 6
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#define FTM_FLTCTRL_FFLTR3EN_MASK 0x80u
|
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#define FTM_FLTCTRL_FFLTR3EN_SHIFT 7
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#define FTM_FLTCTRL_FFVAL_MASK 0xF00u
|
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#define FTM_FLTCTRL_FFVAL_SHIFT 8
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#define FTM_FLTCTRL_FFVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FFVAL_SHIFT))&FTM_FLTCTRL_FFVAL_MASK)
|
|
/* QDCTRL Bit Fields */
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#define FTM_QDCTRL_QUADEN_MASK 0x1u
|
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#define FTM_QDCTRL_QUADEN_SHIFT 0
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#define FTM_QDCTRL_TOFDIR_MASK 0x2u
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#define FTM_QDCTRL_TOFDIR_SHIFT 1
|
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#define FTM_QDCTRL_QUADIR_MASK 0x4u
|
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#define FTM_QDCTRL_QUADIR_SHIFT 2
|
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#define FTM_QDCTRL_QUADMODE_MASK 0x8u
|
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#define FTM_QDCTRL_QUADMODE_SHIFT 3
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#define FTM_QDCTRL_PHBPOL_MASK 0x10u
|
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#define FTM_QDCTRL_PHBPOL_SHIFT 4
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#define FTM_QDCTRL_PHAPOL_MASK 0x20u
|
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#define FTM_QDCTRL_PHAPOL_SHIFT 5
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#define FTM_QDCTRL_PHBFLTREN_MASK 0x40u
|
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#define FTM_QDCTRL_PHBFLTREN_SHIFT 6
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#define FTM_QDCTRL_PHAFLTREN_MASK 0x80u
|
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#define FTM_QDCTRL_PHAFLTREN_SHIFT 7
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/* CONF Bit Fields */
|
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#define FTM_CONF_NUMTOF_MASK 0x1Fu
|
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#define FTM_CONF_NUMTOF_SHIFT 0
|
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#define FTM_CONF_NUMTOF(x) (((uint32_t)(((uint32_t)(x))<<FTM_CONF_NUMTOF_SHIFT))&FTM_CONF_NUMTOF_MASK)
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#define FTM_CONF_BDMMODE_MASK 0xC0u
|
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#define FTM_CONF_BDMMODE_SHIFT 6
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#define FTM_CONF_BDMMODE(x) (((uint32_t)(((uint32_t)(x))<<FTM_CONF_BDMMODE_SHIFT))&FTM_CONF_BDMMODE_MASK)
|
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#define FTM_CONF_GTBEEN_MASK 0x200u
|
|
#define FTM_CONF_GTBEEN_SHIFT 9
|
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#define FTM_CONF_GTBEOUT_MASK 0x400u
|
|
#define FTM_CONF_GTBEOUT_SHIFT 10
|
|
/* FLTPOL Bit Fields */
|
|
#define FTM_FLTPOL_FLT0POL_MASK 0x1u
|
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#define FTM_FLTPOL_FLT0POL_SHIFT 0
|
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#define FTM_FLTPOL_FLT1POL_MASK 0x2u
|
|
#define FTM_FLTPOL_FLT1POL_SHIFT 1
|
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#define FTM_FLTPOL_FLT2POL_MASK 0x4u
|
|
#define FTM_FLTPOL_FLT2POL_SHIFT 2
|
|
#define FTM_FLTPOL_FLT3POL_MASK 0x8u
|
|
#define FTM_FLTPOL_FLT3POL_SHIFT 3
|
|
/* SYNCONF Bit Fields */
|
|
#define FTM_SYNCONF_HWTRIGMODE_MASK 0x1u
|
|
#define FTM_SYNCONF_HWTRIGMODE_SHIFT 0
|
|
#define FTM_SYNCONF_CNTINC_MASK 0x4u
|
|
#define FTM_SYNCONF_CNTINC_SHIFT 2
|
|
#define FTM_SYNCONF_INVC_MASK 0x10u
|
|
#define FTM_SYNCONF_INVC_SHIFT 4
|
|
#define FTM_SYNCONF_SWOC_MASK 0x20u
|
|
#define FTM_SYNCONF_SWOC_SHIFT 5
|
|
#define FTM_SYNCONF_SYNCMODE_MASK 0x80u
|
|
#define FTM_SYNCONF_SYNCMODE_SHIFT 7
|
|
#define FTM_SYNCONF_SWRSTCNT_MASK 0x100u
|
|
#define FTM_SYNCONF_SWRSTCNT_SHIFT 8
|
|
#define FTM_SYNCONF_SWWRBUF_MASK 0x200u
|
|
#define FTM_SYNCONF_SWWRBUF_SHIFT 9
|
|
#define FTM_SYNCONF_SWOM_MASK 0x400u
|
|
#define FTM_SYNCONF_SWOM_SHIFT 10
|
|
#define FTM_SYNCONF_SWINVC_MASK 0x800u
|
|
#define FTM_SYNCONF_SWINVC_SHIFT 11
|
|
#define FTM_SYNCONF_SWSOC_MASK 0x1000u
|
|
#define FTM_SYNCONF_SWSOC_SHIFT 12
|
|
#define FTM_SYNCONF_HWRSTCNT_MASK 0x10000u
|
|
#define FTM_SYNCONF_HWRSTCNT_SHIFT 16
|
|
#define FTM_SYNCONF_HWWRBUF_MASK 0x20000u
|
|
#define FTM_SYNCONF_HWWRBUF_SHIFT 17
|
|
#define FTM_SYNCONF_HWOM_MASK 0x40000u
|
|
#define FTM_SYNCONF_HWOM_SHIFT 18
|
|
#define FTM_SYNCONF_HWINVC_MASK 0x80000u
|
|
#define FTM_SYNCONF_HWINVC_SHIFT 19
|
|
#define FTM_SYNCONF_HWSOC_MASK 0x100000u
|
|
#define FTM_SYNCONF_HWSOC_SHIFT 20
|
|
/* INVCTRL Bit Fields */
|
|
#define FTM_INVCTRL_INV0EN_MASK 0x1u
|
|
#define FTM_INVCTRL_INV0EN_SHIFT 0
|
|
#define FTM_INVCTRL_INV1EN_MASK 0x2u
|
|
#define FTM_INVCTRL_INV1EN_SHIFT 1
|
|
#define FTM_INVCTRL_INV2EN_MASK 0x4u
|
|
#define FTM_INVCTRL_INV2EN_SHIFT 2
|
|
#define FTM_INVCTRL_INV3EN_MASK 0x8u
|
|
#define FTM_INVCTRL_INV3EN_SHIFT 3
|
|
/* SWOCTRL Bit Fields */
|
|
#define FTM_SWOCTRL_CH0OC_MASK 0x1u
|
|
#define FTM_SWOCTRL_CH0OC_SHIFT 0
|
|
#define FTM_SWOCTRL_CH1OC_MASK 0x2u
|
|
#define FTM_SWOCTRL_CH1OC_SHIFT 1
|
|
#define FTM_SWOCTRL_CH2OC_MASK 0x4u
|
|
#define FTM_SWOCTRL_CH2OC_SHIFT 2
|
|
#define FTM_SWOCTRL_CH3OC_MASK 0x8u
|
|
#define FTM_SWOCTRL_CH3OC_SHIFT 3
|
|
#define FTM_SWOCTRL_CH4OC_MASK 0x10u
|
|
#define FTM_SWOCTRL_CH4OC_SHIFT 4
|
|
#define FTM_SWOCTRL_CH5OC_MASK 0x20u
|
|
#define FTM_SWOCTRL_CH5OC_SHIFT 5
|
|
#define FTM_SWOCTRL_CH6OC_MASK 0x40u
|
|
#define FTM_SWOCTRL_CH6OC_SHIFT 6
|
|
#define FTM_SWOCTRL_CH7OC_MASK 0x80u
|
|
#define FTM_SWOCTRL_CH7OC_SHIFT 7
|
|
#define FTM_SWOCTRL_CH0OCV_MASK 0x100u
|
|
#define FTM_SWOCTRL_CH0OCV_SHIFT 8
|
|
#define FTM_SWOCTRL_CH1OCV_MASK 0x200u
|
|
#define FTM_SWOCTRL_CH1OCV_SHIFT 9
|
|
#define FTM_SWOCTRL_CH2OCV_MASK 0x400u
|
|
#define FTM_SWOCTRL_CH2OCV_SHIFT 10
|
|
#define FTM_SWOCTRL_CH3OCV_MASK 0x800u
|
|
#define FTM_SWOCTRL_CH3OCV_SHIFT 11
|
|
#define FTM_SWOCTRL_CH4OCV_MASK 0x1000u
|
|
#define FTM_SWOCTRL_CH4OCV_SHIFT 12
|
|
#define FTM_SWOCTRL_CH5OCV_MASK 0x2000u
|
|
#define FTM_SWOCTRL_CH5OCV_SHIFT 13
|
|
#define FTM_SWOCTRL_CH6OCV_MASK 0x4000u
|
|
#define FTM_SWOCTRL_CH6OCV_SHIFT 14
|
|
#define FTM_SWOCTRL_CH7OCV_MASK 0x8000u
|
|
#define FTM_SWOCTRL_CH7OCV_SHIFT 15
|
|
/* PWMLOAD Bit Fields */
|
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#define FTM_PWMLOAD_CH0SEL_MASK 0x1u
|
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#define FTM_PWMLOAD_CH0SEL_SHIFT 0
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#define FTM_PWMLOAD_CH1SEL_MASK 0x2u
|
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#define FTM_PWMLOAD_CH1SEL_SHIFT 1
|
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#define FTM_PWMLOAD_CH2SEL_MASK 0x4u
|
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#define FTM_PWMLOAD_CH2SEL_SHIFT 2
|
|
#define FTM_PWMLOAD_CH3SEL_MASK 0x8u
|
|
#define FTM_PWMLOAD_CH3SEL_SHIFT 3
|
|
#define FTM_PWMLOAD_CH4SEL_MASK 0x10u
|
|
#define FTM_PWMLOAD_CH4SEL_SHIFT 4
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#define FTM_PWMLOAD_CH5SEL_MASK 0x20u
|
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#define FTM_PWMLOAD_CH5SEL_SHIFT 5
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#define FTM_PWMLOAD_CH6SEL_MASK 0x40u
|
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#define FTM_PWMLOAD_CH6SEL_SHIFT 6
|
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#define FTM_PWMLOAD_CH7SEL_MASK 0x80u
|
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#define FTM_PWMLOAD_CH7SEL_SHIFT 7
|
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#define FTM_PWMLOAD_LDOK_MASK 0x200u
|
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#define FTM_PWMLOAD_LDOK_SHIFT 9
|
|
|
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/****************************************************************/
|
|
/* */
|
|
/* Periodic Interrupt Timer (PIT) */
|
|
/* */
|
|
/****************************************************************/
|
|
/* MCR Bit Fields */
|
|
#define PIT_MCR_FRZ 0x1u
|
|
#define PIT_MCR_MDIS 0x2u
|
|
/* LDVAL Bit Fields */
|
|
#define PIT_LDVAL_TSV_MASK 0xFFFFFFFFu
|
|
#define PIT_LDVAL_TSV_SHIFT 0
|
|
#define PIT_LDVAL_TSV(x) (((uint32_t)(((uint32_t)(x))<<PIT_LDVAL_TSV_SHIFT))&PIT_LDVAL_TSV_MASK)
|
|
/* CVAL Bit Fields */
|
|
#define PIT_CVAL_TVL_MASK 0xFFFFFFFFu
|
|
#define PIT_CVAL_TVL_SHIFT 0
|
|
#define PIT_CVAL_TVL(x) (((uint32_t)(((uint32_t)(x))<<PIT_CVAL_TVL_SHIFT))&PIT_CVAL_TVL_MASK)
|
|
/* TCTRL Bit Fields */
|
|
#define PIT_TCTRL_TEN 0x1u
|
|
#define PIT_TCTRL_TIE 0x2u
|
|
/* TFLG Bit Fields */
|
|
#define PIT_TFLG_TIF 0x1u
|
|
|
|
/****************************************************************/
|
|
/* */
|
|
/* Analog-to-Digital Converter (ADC) */
|
|
/* */
|
|
/****************************************************************/
|
|
/*********** Bits definition for ADCx_SC1n register ***********/
|
|
#define ADCx_SC1n_COCO ((uint32_t)((uint32_t)1 << 7)) /*!< Conversion Complete Flag */
|
|
#define ADCx_SC1n_AIEN ((uint32_t)((uint32_t)1 << 6)) /*!< Interrupt Enable */
|
|
#define ADCx_SC1n_DIFF ((uint32_t)((uint32_t)1 << 5)) /*!< Differential Mode Enable */
|
|
#define ADCx_SC1n_ADCH_SHIFT 0 /*!< Input channel select (shift) */
|
|
#define ADCx_SC1n_ADCH_MASK ((uint32_t)((uint32_t)0x1F << ADCx_SC1n_ADCH_SHIFT)) /*!< Input channel select (mask) */
|
|
#define ADCx_SC1n_ADCH(x) ((uint32_t)(((uint32_t)(x) << ADCx_SC1n_ADCH_SHIFT) & ADCx_SC1n_ADCH_MASK)) /*!< Input channel select */
|
|
|
|
/*********** Bits definition for ADCx_CFG1 register ***********/
|
|
#define ADCx_CFG1_ADLPC ((uint32_t)((uint32_t)1 << 7)) /*!< Low-Power Configuration */
|
|
#define ADCx_CFG1_ADIV_SHIFT 5 /*!< Clock Divide Select (shift) */
|
|
#define ADCx_CFG1_ADIV_MASK ((uint32_t)((uint32_t)0x03 << ADCx_CFG1_ADIV_SHIFT)) /*!< Clock Divide Select (mask) */
|
|
#define ADCx_CFG1_ADIV(x) ((uint32_t)(((uint32_t)(x) << ADCx_CFG1_ADIV_SHIFT) & ADCx_CFG1_ADIV_MASK)) /*!< Clock Divide Select */
|
|
#define ADCx_CFG1_ADLSMP ((uint32_t)((uint32_t)1 << 4)) /*!< Sample time configuration */
|
|
#define ADCx_CFG1_MODE_SHIFT 2 /*!< Conversion mode (resolution) selection (shift) */
|
|
#define ADCx_CFG1_MODE_MASK ((uint32_t)((uint32_t)0x03 << ADCx_CFG1_MODE_SHIFT)) /*!< Conversion mode (resolution) selection (mask) */
|
|
#define ADCx_CFG1_MODE(x) ((uint32_t)(((uint32_t)(x) << ADCx_CFG1_MODE_SHIFT) & ADCx_CFG1_MODE_MASK)) /*!< Conversion mode (resolution) selection */
|
|
#define ADCx_CFG1_ADICLK_SHIFT 0 /*!< Input Clock Select (shift) */
|
|
#define ADCx_CFG1_ADICLK_MASK ((uint32_t)((uint32_t)0x03 << ADCx_CFG1_ADICLK_SHIFT)) /*!< Input Clock Select (mask) */
|
|
#define ADCx_CFG1_ADICLK(x) ((uint32_t)(((uint32_t)(x) << ADCx_CFG1_ADICLK_SHIFT) & ADCx_CFG1_ADICLK_MASK)) /*!< Input Clock Select */
|
|
|
|
/*********** Bits definition for ADCx_CFG2 register ***********/
|
|
#define ADCx_CFG2_MUXSEL ((uint32_t)((uint32_t)1 << 4)) /*!< ADC Mux Select */
|
|
#define ADCx_CFG2_ADACKEN ((uint32_t)((uint32_t)1 << 3)) /*!< Asynchronous Clock Output Enable */
|
|
#define ADCx_CFG2_ADHSC ((uint32_t)((uint32_t)1 << 2)) /*!< High-Speed Configuration */
|
|
#define ADCx_CFG2_ADLSTS_SHIFT 0 /*!< Long Sample Time Select (shift) */
|
|
#define ADCx_CFG2_ADLSTS_MASK ((uint32_t)((uint32_t)0x03 << ADCx_CFG2_ADLSTS_SHIFT)) /*!< Long Sample Time Select (mask) */
|
|
#define ADCx_CFG2_ADLSTS(x) ((uint32_t)(((uint32_t)(x) << ADCx_CFG2_ADLSTS_SHIFT) & ADCx_CFG2_ADLSTS_MASK)) /*!< Long Sample Time Select */
|
|
|
|
/*********** Bits definition for ADCx_SC2 register ***********/
|
|
#define ADCx_SC2_ADACT ((uint32_t)((uint32_t)1 << 7)) /*!< Conversion Active */
|
|
#define ADCx_SC2_ADTRG ((uint32_t)((uint32_t)1 << 6)) /*!< Conversion Trigger Select */
|
|
#define ADCx_SC2_ACFE ((uint32_t)((uint32_t)1 << 5)) /*!< Compare Function Enable */
|
|
#define ADCx_SC2_ACFGT ((uint32_t)((uint32_t)1 << 4)) /*!< Compare Function Greater Than Enable */
|
|
#define ADCx_SC2_ACREN ((uint32_t)((uint32_t)1 << 3)) /*!< Compare Function Range Enable */
|
|
#define ADCx_SC2_DMAEN ((uint32_t)((uint32_t)1 << 2)) /*!< DMA Enable */
|
|
#define ADCx_SC2_REFSEL_SHIFT 0 /*!< Voltage Reference Selection (shift) */
|
|
#define ADCx_SC2_REFSEL_MASK ((uint32_t)((uint32_t)0x03 << ADCx_SC2_REFSEL_SHIFT)) /*!< Voltage Reference Selection (mask) */
|
|
#define ADCx_SC2_REFSEL(x) ((uint32_t)(((uint32_t)(x) << ADCx_SC2_REFSEL_SHIFT) & ADCx_SC2_REFSEL_MASK)) /*!< Voltage Reference Selection */
|
|
|
|
/*********** Bits definition for ADCx_SC3 register ***********/
|
|
#define ADCx_SC3_CAL ((uint32_t)((uint32_t)1 << 7)) /*!< Calibration */
|
|
#define ADCx_SC3_CALF ((uint32_t)((uint32_t)1 << 6)) /*!< Calibration Failed Flag */
|
|
#define ADCx_SC3_ADCO ((uint32_t)((uint32_t)1 << 3)) /*!< Continuous Conversion Enable */
|
|
#define ADCx_SC3_AVGE ((uint32_t)((uint32_t)1 << 2)) /*!< Hardware Average Enable */
|
|
#define ADCx_SC3_AVGS_SHIFT 0 /*!< Hardware Average Select (shift) */
|
|
#define ADCx_SC3_AVGS_MASK ((uint32_t)((uint32_t)0x03 << ADCx_SC3_AVGS_SHIFT)) /*!< Hardware Average Select (mask) */
|
|
#define ADCx_SC3_AVGS(x) ((uint32_t)(((uint32_t)(x) << ADCx_SC3_AVGS_SHIFT) & ADCx_SC3_AVGS_MASK)) /*!< Hardware Average Select */
|
|
|
|
/****************************************************************/
|
|
/* */
|
|
/* Low-Power Timer (LPTMR) */
|
|
/* */
|
|
/****************************************************************/
|
|
/********** Bits definition for LPTMRx_CSR register ***********/
|
|
#define LPTMRx_CSR_TCF ((uint32_t)((uint32_t)1 << 7)) /*!< Timer Compare Flag */
|
|
#define LPTMRx_CSR_TIE ((uint32_t)((uint32_t)1 << 6)) /*!< Timer Interrupt Enable */
|
|
#define LPTMRx_CSR_TPS_SHIFT 4 /*!< Timer Pin Select (shift) */
|
|
#define LPTMRx_CSR_TPS_MASK ((uint32_t)((uint32_t)0x03 << LPTMRx_CSR_TPS_SHIFT)) /*!< Timer Pin Select (mask) */
|
|
#define LPTMRx_CSR_TPS(x) ((uint32_t)(((uint32_t)(x) << LPTMRx_CSR_TPS_SHIFT) & LPTMRx_CSR_TPS_MASK)) /*!< Timer Pin Select */
|
|
#define LPTMRx_CSR_TPP ((uint32_t)((uint32_t)1 << 3)) /*!< Timer Pin Polarity */
|
|
#define LPTMRx_CSR_TFC ((uint32_t)((uint32_t)1 << 2)) /*!< Timer Free-Running Counter */
|
|
#define LPTMRx_CSR_TMS ((uint32_t)((uint32_t)1 << 1)) /*!< Timer Mode Select */
|
|
#define LPTMRx_CSR_TEN ((uint32_t)((uint32_t)1 << 0)) /*!< Timer Enable */
|
|
|
|
/********** Bits definition for LPTMRx_PSR register ***********/
|
|
#define LPTMRx_PSR_PRESCALE_SHIFT 3 /*!< Prescale Value (shift) */
|
|
#define LPTMRx_PSR_PRESCALE_MASK ((uint32_t)((uint32_t)0x0F << LPTMRx_PSR_PRESCALE_SHIFT)) /*!< Prescale Value (mask) */
|
|
#define LPTMRx_PSR_PRESCALE(x) ((uint32_t)(((uint32_t)(x) << LPTMRx_PSR_PRESCALE_SHIFT) & LPTMRx_PSR_PRESCALE_MASK)) /*!< Prescale Value */
|
|
#define LPTMRx_PSR_PBYP ((uint32_t)((uint32_t)1 << 2)) /*!< Prescaler Bypass */
|
|
#define LPTMRx_PSR_PCS_SHIFT 0 /*!< Prescaler Clock Select (shift) */
|
|
#define LPTMRx_PSR_PCS_MASK ((uint32_t)((uint32_t)0x03 << LPTMRx_PSR_PCS_SHIFT)) /*!< Prescaler Clock Select (mask) */
|
|
#define LPTMRx_PSR_PCS(x) ((uint32_t)(((uint32_t)(x) << LPTMRx_PSR_PCS_SHIFT) & LPTMRx_PSR_PCS_MASK)) /*!< Prescaler Clock Select */
|
|
|
|
/********** Bits definition for LPTMRx_CMR register ***********/
|
|
#define LPTMRx_CMR_COMPARE_SHIFT 0 /*!< Compare Value (shift) */
|
|
#define LPTMRx_CMR_COMPARE_MASK ((uint32_t)((uint32_t)0xFFFF << LPTMRx_CMR_COMPARE_SHIFT)) /*!< Compare Value (mask) */
|
|
#define LPTMRx_CMR_COMPARE(x) ((uint32_t)(((uint32_t)(x) << LPTMRx_CMR_COMPARE_SHIFT) & LPTMRx_CMR_COMPARE_MASK)) /*!< Compare Value */
|
|
|
|
/********** Bits definition for LPTMRx_CNR register ***********/
|
|
#define LPTMRx_CNR_COUNTER_SHIFT 0 /*!< Counter Value (shift) */
|
|
#define LPTMRx_CNR_COUNTER_MASK ((uint32_t)((uint32_t)0xFFFF << LPTMRx_CNR_COUNTER_SHIFT)) /*!< Counter Value (mask) */
|
|
#define LPTMRx_CNR_COUNTER(x) ((uint32_t)(((uint32_t)(x) << LPTMRx_CNR_COUNTER_SHIFT) & LPTMRx_CNR_COUNTER_MASK)) /*!< Counter Value */
|
|
|
|
/****************************************************************/
|
|
/* */
|
|
/* Touch Sensing Input (TSI) */
|
|
/* */
|
|
/****************************************************************/
|
|
/********** Bits definition for TSIx_GENCS register ***********/
|
|
#define TSIx_GENCS_OUTRGF ((uint32_t)((uint32_t)1 << 31)) /*!< Out of Range Flag */
|
|
#define TSIx_GENCS_ESOR ((uint32_t)((uint32_t)1 << 28)) /*!< End-of-scan/Out-of-Range Interrupt Selection */
|
|
#define TSIx_GENCS_MODE_SHIFT 24 /*!< TSI analog modes setup and status bits (shift) */
|
|
#define TSIx_GENCS_MODE_MASK ((uint32_t)((uint32_t)0x0F << TSIx_GENCS_MODE_SHIFT)) /*!< TSI analog modes setup and status bits (mask) */
|
|
#define TSIx_GENCS_MODE(x) ((uint32_t)(((uint32_t)(x) << TSIx_GENCS_MODE_SHIFT) & TSIx_GENCS_MODE_MASK)) /*!< TSI analog modes setup and status bits */
|
|
#define TSIx_GENCS_REFCHRG_SHIFT 21 /*!< Reference oscillator charge/discharge current (shift) */
|
|
#define TSIx_GENCS_REFCHRG_MASK ((uint32_t)((uint32_t)0x07 << TSIx_GENCS_REFCHRG_SHIFT)) /*!< Reference oscillator charge/discharge current (mask) */
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#define TSIx_GENCS_REFCHRG(x) ((uint32_t)(((uint32_t)(x) << TSIx_GENCS_REFCHRG_SHIFT) & TSIx_GENCS_REFCHRG_MASK)) /*!< Reference oscillator charge/discharge current */
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#define TSIx_GENCS_DVOLT_SHIFT 19 /*!< Oscillator voltage rails (shift) */
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#define TSIx_GENCS_DVOLT_MASK ((uint32_t)((uint32_t)0x03 << TSIx_GENCS_DVOLT_SHIFT)) /*!< Oscillator voltage rails (mask) */
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#define TSIx_GENCS_DVOLT(x) ((uint32_t)(((uint32_t)(x) << TSIx_GENCS_DVOLT_SHIFT) & TSIx_GENCS_DVOLT_MASK)) /*!< Oscillator voltage rails */
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#define TSIx_GENCS_EXTCHRG_SHIFT 16 /*!< Electrode oscillator charge/discharge current (shift) */
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#define TSIx_GENCS_EXTCHRG_MASK ((uint32_t)((uint32_t)0x07 << TSIx_GENCS_EXTCHRG_SHIFT)) /*!< Electrode oscillator charge/discharge current (mask) */
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#define TSIx_GENCS_EXTCHRG(x) ((uint32_t)(((uint32_t)(x) << TSIx_GENCS_EXTCHRG_SHIFT) & TSIx_GENCS_EXTCHRG_MASK)) /*!< Electrode oscillator charge/discharge current */
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#define TSIx_GENCS_PS_SHIFT 13 /*!< Electrode oscillator prescaler (shift) */
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#define TSIx_GENCS_PS_MASK ((uint32_t)((uint32_t)0x07 << TSIx_GENCS_PS_SHIFT)) /*!< Electrode oscillator prescaler (mask) */
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#define TSIx_GENCS_PS(x) ((uint32_t)(((uint32_t)(x) << TSIx_GENCS_PS_SHIFT) & TSIx_GENCS_PS_MASK)) /*!< Electrode oscillator prescaler */
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#define TSIx_GENCS_NSCN_SHIFT 8 /*!< Number of scans per electrode minus 1 (shift) */
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#define TSIx_GENCS_NSCN_MASK ((uint32_t)((uint32_t)0x1F << TSIx_GENCS_NSCN_SHIFT)) /*!< Number of scans per electrode minus 1 (mask) */
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#define TSIx_GENCS_NSCN(x) ((uint32_t)(((uint32_t)(x) << TSIx_GENCS_NSCN_SHIFT) & TSIx_GENCS_NSCN_MASK)) /*!< Number of scans per electrode minus 1 */
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#define TSIx_GENCS_TSIEN ((uint32_t)((uint32_t)1 << 7)) /*!< TSI Module Enable */
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#define TSIx_GENCS_TSIIEN ((uint32_t)((uint32_t)1 << 6)) /*!< TSI Interrupt Enable */
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#define TSIx_GENCS_STPE ((uint32_t)((uint32_t)1 << 5)) /*!< TSI STOP Enable */
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#define TSIx_GENCS_STM ((uint32_t)((uint32_t)1 << 4)) /*!< Scan Trigger Mode (0=software; 1=hardware) */
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#define TSIx_GENCS_SCNIP ((uint32_t)((uint32_t)1 << 3)) /*!< Scan in Progress Status */
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#define TSIx_GENCS_EOSF ((uint32_t)((uint32_t)1 << 2)) /*!< End of Scan Flag */
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#define TSIx_GENCS_CURSW ((uint32_t)((uint32_t)1 << 1)) /*!< Swap electrode and reference current sources */
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/********** Bits definition for TSIx_DATA register ************/
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#define TSIx_DATA_TSICH_SHIFT 28 /*!< Specify channel to be measured (shift) */
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#define TSIx_DATA_TSICH_MASK ((uint32_t)((uint32_t)0x0F << TSIx_DATA_TSICH_SHIFT)) /*!< Specify channel to be measured (mask) */
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#define TSIx_DATA_TSICH(x) ((uint32_t)(((uint32_t)(x) << TSIx_DATA_TSICH_SHIFT) & TSIx_DATA_TSICH_MASK)) /*!< Specify channel to be measured */
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#define TSIx_DATA_DMAEN ((uint32_t)((uint32_t)1 << 23)) /*!< DMA Transfer Enabled */
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#define TSIx_DATA_SWTS ((uint32_t)((uint32_t)1 << 22)) /*!< Software Trigger Start */
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#define TSIx_DATA_TSICNT_SHIFT 0 /*!< TSI Conversion Counter Value (shift) */
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#define TSIx_DATA_TSICNT_MASK ((uint32_t)((uint32_t)0xFFFF << TSIx_DATA_TSICNT_SHIFT)) /*!< TSI Conversion Counter Value (mask) */
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#define TSIx_DATA_TSICNT(x) ((uint32_t)(((uint32_t)(x) << TSIx_DATA_TSICNT_SHIFT) & TSIx_DATA_TSICNT_MASK)) /*!< TSI Conversion Counter Value */
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/********** Bits definition for TSIx_TSHD register ************/
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#define TSIx_TSHD_THRESH_SHIFT 16 /*!< TSI Wakeup Channel High-Threshold (shift) */
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#define TSIx_TSHD_THRESH_MASK ((uint32_t)((uint32_t)0xFFFF << TSIx_TSHD_THRESH_SHIFT)) /*!< TSI Wakeup Channel High-Threshold (mask) */
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#define TSIx_TSHD_THRESH(x) ((uint32_t)(((uint32_t)(x) << TSIx_TSHD_THRESH_SHIFT) & TSIx_TSHD_THRESH_MASK)) /*!< TSI Wakeup Channel High-Threshold */
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#define TSIx_TSHD_THRESL_SHIFT 0 /*!< TSI Wakeup Channel Low-Threshold (shift) */
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#define TSIx_TSHD_THRESL_MASK ((uint32_t)((uint32_t)0xFFFF << TSIx_TSHD_THRESL_SHIFT)) /*!< TSI Wakeup Channel Low-Threshold (mask) */
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#define TSIx_TSHD_THRESL(x) ((uint32_t)(((uint32_t)(x) << TSIx_TSHD_THRESL_SHIFT) & TSIx_TSHD_THRESL_MASK)) /*!< TSI Wakeup Channel Low-Threshold */
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/****************************************************************/
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/* */
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/* Multipurpose Clock Generator (MCG) */
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/* */
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/****************************************************************/
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/*********** Bits definition for MCG_C1 register **************/
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#define MCG_C1_CLKS_SHIFT 6 /*!< Clock source select (shift) */
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#define MCG_C1_CLKS_MASK ((uint8_t)((uint8_t)0x3 << MCG_C1_CLKS_SHIFT)) /*!< Clock source select (mask) */
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#define MCG_C1_CLKS(x) ((uint8_t)(((uint8_t)(x) << MCG_C1_CLKS_SHIFT) & MCG_C1_CLKS_MASK)) /*!< Clock source select */
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#define MCG_C1_CLKS_FLLPLL MCG_C1_CLKS(0) /*!< Select output of FLL or PLL, depending on PLLS control bit */
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#define MCG_C1_CLKS_IRCLK MCG_C1_CLKS(1) /*!< Select internal reference clock */
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#define MCG_C1_CLKS_ERCLK MCG_C1_CLKS(2) /*!< Select external reference clock */
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#define MCG_C1_FRDIV_SHIFT 3 /*!< FLL External Reference Divider (shift) */
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#define MCG_C1_FRDIV_MASK ((uint8_t)((uint8_t)0x7 << MCG_C1_FRDIV_SHIFT)) /*!< FLL External Reference Divider (mask) */
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#define MCG_C1_FRDIV(x) ((uint8_t)(((uint8_t)(x) << MCG_C1_FRDIV_SHIFT) & MCG_C1_FRDIV_MASK)) /*!< FLL External Reference Divider */
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#define MCG_C1_IREFS ((uint8_t)0x04) /*!< Internal Reference Select (0=ERCLK; 1=slow IRCLK) */
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#define MCG_C1_IRCLKEN ((uint8_t)0x02) /*!< Internal Reference Clock Enable */
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#define MCG_C1_IREFSTEN ((uint8_t)0x01) /*!< Internal Reference Stop Enable */
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/*********** Bits definition for MCG_C2 register **************/
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#define MCG_C2_LOCRE0 ((uint8_t)0x80) /*!< Loss of Clock Reset Enable */
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#define MCG_C2_RANGE0_SHIFT 4 /*!< Frequency Range Select (shift) */
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#define MCG_C2_RANGE0_MASK ((uint8_t)((uint8_t)0x3 << MCG_C2_RANGE0_SHIFT)) /*!< Frequency Range Select (mask) */
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#define MCG_C2_RANGE0(x) ((uint8_t)(((uint8_t)(x) << MCG_C2_RANGE0_SHIFT) & MCG_C2_RANGE0_MASK)) /*!< Frequency Range Select */
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#define MCG_C2_HGO0 ((uint8_t)0x08) /*!< High Gain Oscillator Select (0=low power; 1=high gain) */
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#define MCG_C2_EREFS0 ((uint8_t)0x04) /*!< External Reference Select (0=clock; 1=oscillator) */
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#define MCG_C2_LP ((uint8_t)0x02) /*!< Low Power Select (1=FLL/PLL disabled in bypass modes) */
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#define MCG_C2_IRCS ((uint8_t)0x01) /*!< Internal Reference Clock Select (0=slow; 1=fast) */
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/*********** Bits definition for MCG_C4 register **************/
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#define MCG_C4_DMX32 ((uint8_t)0x80) /*!< DCO Maximum Frequency with 32.768 kHz Reference */
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#define MCG_C4_DRST_DRS_SHIFT 5 /*!< DCO Range Select (shift) */
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#define MCG_C4_DRST_DRS_MASK ((uint8_t)((uint8_t)0x3 << MCG_C4_DRST_DRS_SHIFT)) /*!< DCO Range Select (mask) */
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#define MCG_C4_DRST_DRS(x) ((uint8_t)(((uint8_t)(x) << MCG_C4_DRST_DRS_SHIFT) & MCG_C4_DRST_DRS_MASK)) /*!< DCO Range Select */
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#define MCG_C4_FCTRIM_SHIFT 1 /*!< Fast Internal Reference Clock Trim Setting (shift) */
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#define MCG_C4_FCTRIM_MASK ((uint8_t)((uint8_t)0xF << MCG_C4_FCTRIM_SHIFT)) /*!< Fast Internal Reference Clock Trim Setting (mask) */
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#define MCG_C4_FCTRIM(x) ((uint8_t)(((uint8_t)(x) << MCG_C4_FCTRIM_SHIFT) & MCG_C4_FCTRIM_MASK)) /*!< Fast Internal Reference Clock Trim Setting */
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#define MCG_C4_SCFTRIM ((uint8_t)0x01) /*!< Slow Internal Reference Clock Fine Trim */
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/*********** Bits definition for MCG_C5 register **************/
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#define MCG_C5_PLLCLKEN0 ((uint8_t)0x40) /*!< PLL Clock Enable */
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#define MCG_C5_PLLSTEN0 ((uint8_t)0x20) /*!< PLL Stop Enable */
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#define MCG_C5_PRDIV0_MASK ((uint8_t)0x1F) /*!< PLL External Reference Divider (mask) */
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#define MCG_C5_PRDIV0(x) ((uint8_t)((uint8_t)(x) & MCG_C5_PRDIV0_MASK)) /*!< PLL External Reference Divider */
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/*********** Bits definition for MCG_C6 register **************/
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#define MCG_C6_LOLIE0 ((uint8_t)0x80) /*!< Loss of Lock Interrupt Enable */
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#define MCG_C6_PLLS ((uint8_t)0x40) /*!< PLL Select */
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#define MCG_C6_CME0 ((uint8_t)0x20) /*!< Clock Monitor Enable */
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#define MCG_C6_VDIV0_MASK ((uint8_t)0x1F) /*!< VCO 0 Divider (mask) */
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#define MCG_C6_VDIV0(x) ((uint8_t)((uint8_t)(x) & MCG_C6_VDIV0_MASK)) /*!< VCO 0 Divider */
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/************ Bits definition for MCG_S register **************/
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#define MCG_S_LOLS ((uint8_t)0x80) /*!< Loss of Lock Status */
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#define MCG_S_LOCK0 ((uint8_t)0x40) /*!< Lock Status */
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#define MCG_S_PLLST ((uint8_t)0x20) /*!< PLL Select Status */
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#define MCG_S_IREFST ((uint8_t)0x10) /*!< Internal Reference Status */
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#define MCG_S_CLKST_SHIFT 2 /*!< Clock Mode Status (shift) */
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#define MCG_S_CLKST_MASK ((uint8_t)((uint8_t)0x3 << MCG_S_CLKST_SHIFT)) /*!< Clock Mode Status (mask) */
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#define MCG_S_CLKST(x) ((uint8_t)(((uint8_t)(x) << MCG_S_CLKST_SHIFT) & MCG_S_CLKST_MASK)) /*!< Clock Mode Status */
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#define MCG_S_CLKST_FLL MCG_S_CLKST(0) /*!< Output of the FLL is selected */
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#define MCG_S_CLKST_IRCLK MCG_S_CLKST(1) /*!< Internal reference clock is selected */
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#define MCG_S_CLKST_ERCLK MCG_S_CLKST(2) /*!< External reference clock is selected */
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#define MCG_S_CLKST_PLL MCG_S_CLKST(3) /*!< Output of the PLL is selected */
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#define MCG_S_OSCINIT0 ((uint8_t)0x02) /*!< OSC Initialization */
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#define MCG_S_IRCST ((uint8_t)0x01) /*!< Internal Reference Clock Status */
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/************ Bits definition for MCG_SC register **************/
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#define MCG_SC_ATME ((uint8_t)0x80) /*!< Automatic Trim Machine Enable */
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#define MCG_SC_ATMS ((uint8_t)0x40) /*!< Automatic Trim Machine Select */
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#define MCG_SC_ATMF ((uint8_t)0x20) /*!< Automatic Trim Machine Fail Flag */
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#define MCG_SC_FLTPRSRV ((uint8_t)0x10) /*!< FLL Filter Preserve Enable */
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#define MCG_SC_FCRDIV_SHIFT 1 /*!< Fast Clock Internal Reference Divider (shift) */
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#define MCG_SC_FCRDIV_MASK ((uint8_t)((uint8_t)0x7 << MCG_SC_FCRDIV_SHIFT)) /*!< Fast Clock Internal Reference Divider (mask) */
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#define MCG_SC_FCRDIV(x) ((uint8_t)(((uint8_t)(x) << MCG_SC_FCRDIV_SHIFT) & MCG_SC_FCRDIV_MASK)) /*!< Fast Clock Internal Reference Divider */
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#define MCG_SC_FCRDIV_DIV1 MCG_SC_FCRDIV(0) /*!< Divide Factor is 1 */
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#define MCG_SC_FCRDIV_DIV2 MCG_SC_FCRDIV(1) /*!< Divide Factor is 2 */
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#define MCG_SC_FCRDIV_DIV4 MCG_SC_FCRDIV(2) /*!< Divide Factor is 4 */
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#define MCG_SC_FCRDIV_DIV8 MCG_SC_FCRDIV(3) /*!< Divide Factor is 8 */
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#define MCG_SC_FCRDIV_DIV16 MCG_SC_FCRDIV(4) /*!< Divide Factor is 16 */
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#define MCG_SC_FCRDIV_DIV32 MCG_SC_FCRDIV(5) /*!< Divide Factor is 32 */
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#define MCG_SC_FCRDIV_DIV64 MCG_SC_FCRDIV(6) /*!< Divide Factor is 64 */
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#define MCG_SC_FCRDIV_DIV128 MCG_SC_FCRDIV(7) /*!< Divide Factor is 128 */
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#define MCG_SC_LOCS0 ((uint8_t)0x01) /*!< OSC0 Loss of Clock Status */
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/************ Bits definition for MCG_C7 register **************/
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#define MCG_C7_OSCSEL ((uint8_t)0x01) /*!< MCG OSC Clock Select */
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/************ Bits definition for MCG_C8 register **************/
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#define MCG_C8_LOCRE1 ((uint8_t)0x80) /*!< PLL Loss of Clock Reset Enable */
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#define MCG_C8_LOLRE ((uint8_t)0x40) /*!< PLL Loss of Lock Reset Enable */
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#define MCG_C8_CME1 ((uint8_t)0x20) /*!< PLL Clock Monitor Enable */
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#define MCG_C8_LOCS1 ((uint8_t)0x01) /*!< RTC Loss of Clock Status */
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/****************************************************************/
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/* */
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/* Serial Peripheral Interface (SPI) */
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/* */
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/****************************************************************/
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/*********** Bits definition for SPIx_MCR register *************/
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#define SPIx_MCR_MSTR ((uint32_t)0x80000000) // Master/Slave Mode Select
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#define SPIx_MCR_CONT_SCKE ((uint32_t)0x40000000) // Continuous SCK Enable
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#define SPIx_MCR_DCONF(n) (((n) & 3) << 28) // DSPI Configuration
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#define SPIx_MCR_FRZ ((uint32_t)0x08000000) // Freeze
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#define SPIx_MCR_MTFE ((uint32_t)0x04000000) // Modified Timing Format Enable
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#define SPIx_MCR_ROOE ((uint32_t)0x01000000) // Receive FIFO Overflow Overwrite Enable
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#define SPIx_MCR_PCSIS(n) (((n) & 0x1F) << 16) // Peripheral Chip Select x Inactive State
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#define SPIx_MCR_DOZE ((uint32_t)0x00008000) // Doze Enable
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#define SPIx_MCR_MDIS ((uint32_t)0x00004000) // Module Disable
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#define SPIx_MCR_DIS_TXF ((uint32_t)0x00002000) // Disable Transmit FIFO
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#define SPIx_MCR_DIS_RXF ((uint32_t)0x00001000) // Disable Receive FIFO
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#define SPIx_MCR_CLR_TXF ((uint32_t)0x00000800) // Clear the TX FIFO and counter
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#define SPIx_MCR_CLR_RXF ((uint32_t)0x00000400) // Clear the RX FIFO and counter
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#define SPIx_MCR_SMPL_PT(n) (((n) & 3) << 8) // Sample Point
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#define SPIx_MCR_HALT ((uint32_t)0x00000001) // Halt
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/*********** Bits definition for SPIx_TCR register *************/
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#define SPIx_TCR_TCNT(n) (((n) & 0xffff) << 16) // DSPI Transfer Count Register
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/*********** Bits definition for SPIx_CTARn register *************/
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#define SPIx_CTARn_DBR ((uint32_t)0x80000000) // Double Baud Rate
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#define SPIx_CTARn_FMSZ_SHIFT 27 // Frame Size Shift
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#define SPIx_CTARn_FMSZ_MASK 0xF // Frame Size Mask
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#define SPIx_CTARn_FMSZ(n) (((n) & 15) << 27) // Frame Size (+1)
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#define SPIx_CTARn_CPOL ((uint32_t)0x04000000) // Clock Polarity
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#define SPIx_CTARn_CPHA ((uint32_t)0x02000000) // Clock Phase
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#define SPIx_CTARn_LSBFE ((uint32_t)0x01000000) // LSB First
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#define SPIx_CTARn_PCSSCK(n) (((n) & 3) << 22) // PCS to SCK Delay Prescaler
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#define SPIx_CTARn_PASC(n) (((n) & 3) << 20) // After SCK Delay Prescaler
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#define SPIx_CTARn_PDT(n) (((n) & 3) << 18) // Delay after Transfer Prescaler
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#define SPIx_CTARn_PBR(n) (((n) & 3) << 16) // Baud Rate Prescaler
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#define SPIx_CTARn_CSSCK(n) (((n) & 15) << 12) // PCS to SCK Delay Scaler
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#define SPIx_CTARn_ASC(n) (((n) & 15) << 8) // After SCK Delay Scaler
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#define SPIx_CTARn_DT(n) (((n) & 15) << 4) // Delay After Transfer Scaler
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#define SPIx_CTARn_BR(n) (((n) & 15) << 0) // Baud Rate Scaler
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/*********** Bits definition for SPIx_CTARn_SLAVE register *************/
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#define SPIx_CTARn_SLAVE_FMSZ(n) (((n) & 15) << 27) // Frame Size (+1)
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#define SPIx_CTARn_SLAVE_CPOL ((uint32_t)0x04000000) // Clock Polarity
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#define SPIx_CTARn_SLAVE_CPHA ((uint32_t)0x02000000) // Clock Phase
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/*********** Bits definition for SPIx_SR register *************/
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#define SPIx_SR_TCF ((uint32_t)0x80000000) // Transfer Complete Flag
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#define SPIx_SR_TXRXS ((uint32_t)0x40000000) // TX and RX Status
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#define SPIx_SR_EOQF ((uint32_t)0x10000000) // End of Queue Flag
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#define SPIx_SR_TFUF ((uint32_t)0x08000000) // Transmit FIFO Underflow Flag
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#define SPIx_SR_TFFF ((uint32_t)0x02000000) // Transmit FIFO Fill Flag
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#define SPIx_SR_RFOF ((uint32_t)0x00080000) // Receive FIFO Overflow Flag
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#define SPIx_SR_RFDF ((uint32_t)0x00020000) // Receive FIFO Drain Flag
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#define SPIx_SR_TXCTR (((n) & 15) << 12) // TX FIFO Counter
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#define SPIx_SR_TXNXPTR (((n) & 15) << 8) // Transmit Next Pointer
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#define SPIx_SR_RXCTR (((n) & 15) << 4) // RX FIFO Counter
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#define SPIx_SR_POPNXTPTR ((n) & 15) // POP Next Pointer
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/*********** Bits definition for SPIx_SR register *************/
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#define SPIx_RSER_TCF_RE ((uint32_t)0x80000000) // Transmission Complete Request Enable
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#define SPIx_RSER_EOQF_RE ((uint32_t)0x10000000) // DSPI Finished Request Request Enable
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#define SPIx_RSER_TFUF_RE ((uint32_t)0x08000000) // Transmit FIFO Underflow Request Enable
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#define SPIx_RSER_TFFF_RE ((uint32_t)0x02000000) // Transmit FIFO Fill Request Enable
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#define SPIx_RSER_TFFF_DIRS ((uint32_t)0x01000000) // Transmit FIFO FIll Dma or Interrupt Request Select
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#define SPIx_RSER_RFOF_RE ((uint32_t)0x00080000) // Receive FIFO Overflow Request Enable
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#define SPIx_RSER_RFDF_RE ((uint32_t)0x00020000) // Receive FIFO Drain Request Enable
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#define SPIx_RSER_RFDF_DIRS ((uint32_t)0x00010000) // Receive FIFO Drain DMA or Interrupt Request Select
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/*********** Bits definition for SPIx_PUSHR register *************/
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#define SPIx_PUSHR_CONT ((uint32_t)0x80000000) // Continuous Peripheral Chip Select Enable
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#define SPIx_PUSHR_CTAS(n) (((n) & 7) << 28) // Clock and Transfer Attributes Select
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#define SPIx_PUSHR_EOQ ((uint32_t)0x08000000) // End Of Queue
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#define SPIx_PUSHR_CTCNT ((uint32_t)0x04000000) // Clear Transfer Counter
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#define SPIx_PUSHR_PCS(n) (((n) & 31) << 16) // Peripheral Chip Select
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#define SPIx_PUSHR_TXDATA(n) ((n) & 0xffff) // Transmit Data
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/*********** Bits definition for SPIx_PUSHR_SLAVE register *************/
|
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#define SPIx_PUSHR_SLAVE_TXDATA(n) (((n) & 0xffff) << 0) // Transmit Data in slave mode
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/*********** Bits definition for SPIx_POPR register *************/
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#define SPIx_POPR_RXDATA(n) (((n) & 0xffff) << 16) // Received Data
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/*********** Bits definition for SPIx_TXFRn register *************/
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#define SPIx_TXFRn_TXCMD_TXDATA (((n) & 0xffff) << 16) // Transmit Command (in master mode)
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#define SPIx_TXFRn_TXDATA(n) (((n) & 0xffff) << 0) // Transmit Data
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/*********** Bits definition for SPIx_RXFRn register *************/
|
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#define SPIx_RXFRn_RXDATA(n) (((n) & 0xffff) << 0) // Receive Data
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/****************************************************************/
|
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/* */
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/* Inter-Integrated Circuit (I2C) */
|
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/* */
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/****************************************************************/
|
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/*********** Bits definition for I2Cx_A1 register *************/
|
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#define I2Cx_A1_AD ((uint8_t)0xFE) /*!< Address [7:1] */
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#define I2Cx_A1_AD_SHIT 1
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/*********** Bits definition for I2Cx_F register **************/
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#define I2Cx_F_MULT ((uint8_t)0xC0) /*!< Multiplier factor */
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#define I2Cx_F_ICR ((uint8_t)0x3F) /*!< Clock rate */
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#define I2Cx_F_MULT_SHIFT 5
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/*********** Bits definition for I2Cx_C1 register *************/
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#define I2Cx_C1_IICEN ((uint8_t)0x80) /*!< I2C Enable */
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#define I2Cx_C1_IICIE ((uint8_t)0x40) /*!< I2C Interrupt Enable */
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#define I2Cx_C1_MST ((uint8_t)0x20) /*!< Master Mode Select */
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#define I2Cx_C1_TX ((uint8_t)0x10) /*!< Transmit Mode Select */
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#define I2Cx_C1_TXAK ((uint8_t)0x08) /*!< Transmit Acknowledge Enable */
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#define I2Cx_C1_RSTA ((uint8_t)0x04) /*!< Repeat START */
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#define I2Cx_C1_WUEN ((uint8_t)0x02) /*!< Wakeup Enable */
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#define I2Cx_C1_DMAEN ((uint8_t)0x01) /*!< DMA Enable */
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/*********** Bits definition for I2Cx_S register **************/
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#define I2Cx_S_TCF ((uint8_t)0x80) /*!< Transfer Complete Flag */
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#define I2Cx_S_IAAS ((uint8_t)0x40) /*!< Addressed As A Slave */
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#define I2Cx_S_BUSY ((uint8_t)0x20) /*!< Bus Busy */
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#define I2Cx_S_ARBL ((uint8_t)0x10) /*!< Arbitration Lost */
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#define I2Cx_S_RAM ((uint8_t)0x08) /*!< Range Address Match */
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#define I2Cx_S_SRW ((uint8_t)0x04) /*!< Slave Read/Write */
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#define I2Cx_S_IICIF ((uint8_t)0x02) /*!< Interrupt Flag */
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#define I2Cx_S_RXAK ((uint8_t)0x01) /*!< Receive Acknowledge */
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/*********** Bits definition for I2Cx_D register **************/
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#define I2Cx_D_DATA ((uint8_t)0xFF) /*!< Data */
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/*********** Bits definition for I2Cx_C2 register *************/
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#define I2Cx_C2_GCAEN ((uint8_t)0x80) /*!< General Call Address Enable */
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#define I2Cx_C2_ADEXT ((uint8_t)0x40) /*!< Address Extension */
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#define I2Cx_C2_HDRS ((uint8_t)0x20) /*!< High Drive Select */
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#define I2Cx_C2_SBRC ((uint8_t)0x10) /*!< Slave Baud Rate Control */
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#define I2Cx_C2_RMEN ((uint8_t)0x08) /*!< Range Address Matching Enable */
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#define I2Cx_C2_AD_10_8 ((uint8_t)0x03) /*!< Slave Address [10:8] */
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/*********** Bits definition for I2Cx_FLT register ************/
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#define I2Cx_FLT_SHEN ((uint8_t)0x80) /*!< Stop Hold Enable */
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#define I2Cx_FLT_STOPF ((uint8_t)0x40) /*!< I2C Bus Stop Detect Flag */
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#define I2Cx_FLT_STOPIE ((uint8_t)0x20) /*!< I2C Bus Stop Interrupt Enable */
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#define I2Cx_FLT_FLT ((uint8_t)0x1F) /*!< I2C Programmable Filter Factor */
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/*********** Bits definition for I2Cx_RA register *************/
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#define I2Cx_RA_RAD ((uint8_t)0xFE) /*!< Range Slave Address */
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#define I2Cx_RA_RAD_SHIFT 1
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/*********** Bits definition for I2Cx_SMB register ************/
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#define I2Cx_SMB_FACK ((uint8_t)0x80) /*!< Fast NACK/ACK Enable */
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#define I2Cx_SMB_ALERTEN ((uint8_t)0x40) /*!< SMBus Alert Response Address Enable */
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#define I2Cx_SMB_SIICAEN ((uint8_t)0x20) /*!< Second I2C Address Enable */
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#define I2Cx_SMB_TCKSEL ((uint8_t)0x10) /*!< Timeout Counter Clock Select */
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#define I2Cx_SMB_SLTF ((uint8_t)0x08) /*!< SCL Low Timeout Flag */
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#define I2Cx_SMB_SHTF1 ((uint8_t)0x04) /*!< SCL High Timeout Flag 1 */
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#define I2Cx_SMB_SHTF2 ((uint8_t)0x02) /*!< SCL High Timeout Flag 2 */
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#define I2Cx_SMB_SHTF2IE ((uint8_t)0x01) /*!< SHTF2 Interrupt Enable */
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/*********** Bits definition for I2Cx_A2 register *************/
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#define I2Cx_A2_SAD ((uint8_t)0xFE) /*!< SMBus Address */
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#define I2Cx_A2_SAD_SHIFT 1
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/*********** Bits definition for I2Cx_SLTH register ***********/
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#define I2Cx_SLTH_SSLT ((uint8_t)0xFF) /*!< MSB of SCL low timeout value */
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/*********** Bits definition for I2Cx_SLTL register ***********/
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#define I2Cx_SLTL_SSLT ((uint8_t)0xFF) /*!< LSB of SCL low timeout value */
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/****************************************************************/
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/* */
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/* Universal Asynchronous Receiver/Transmitter (UART) */
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/* */
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/****************************************************************/
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/********* Bits definition for UARTx_BDH register *************/
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#define UARTx_BDH_LBKDIE ((uint8_t)0x80) /*!< LIN Break Detect Interrupt Enable */
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#define UARTx_BDH_RXEDGIE ((uint8_t)0x40) /*!< RxD Input Active Edge Interrupt Enable */
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#define UARTx_BDH_SBR_MASK ((uint8_t)0x1F)
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#define UARTx_BDH_SBR(x) ((uint8_t)((uint8_t)(x) & UARTx_BDH_SBR_MASK)) /*!< Baud Rate Modulo Divisor */
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/********* Bits definition for UARTx_BDL register *************/
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#define UARTx_BDL_SBR_MASK ((uint8_t)0xFF) /*!< Baud Rate Modulo Divisor */
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/********* Bits definition for UARTx_C1 register **************/
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#define UARTx_C1_LOOPS ((uint8_t)0x80) /*!< Loop Mode Select */
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#define UARTx_C1_DOZEEN ((uint8_t)0x40) /*!< Doze Enable */
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#define UARTx_C1_UARTSWAI ((uint8_t)0x40) /*!< UART Stops in Wait Mode */
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#define UARTx_C1_RSRC ((uint8_t)0x20) /*!< Receiver Source Select */
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#define UARTx_C1_M ((uint8_t)0x10) /*!< 9-Bit or 8-Bit Mode Select */
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#define UARTx_C1_WAKE ((uint8_t)0x08) /*!< Receiver Wakeup Method Select */
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#define UARTx_C1_ILT ((uint8_t)0x04) /*!< Idle Line Type Select */
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#define UARTx_C1_PE ((uint8_t)0x02) /*!< Parity Enable */
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#define UARTx_C1_PT ((uint8_t)0x01) /*!< Parity Type */
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/********* Bits definition for UARTx_C2 register **************/
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#define UARTx_C2_TIE ((uint8_t)0x80) /*!< Transmit Interrupt Enable for TDRE */
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#define UARTx_C2_TCIE ((uint8_t)0x40) /*!< Transmission Complete Interrupt Enable for TC */
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#define UARTx_C2_RIE ((uint8_t)0x20) /*!< Receiver Interrupt Enable for RDRF */
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#define UARTx_C2_ILIE ((uint8_t)0x10) /*!< Idle Line Interrupt Enable for IDLE */
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#define UARTx_C2_TE ((uint8_t)0x08) /*!< Transmitter Enable */
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#define UARTx_C2_RE ((uint8_t)0x04) /*!< Receiver Enable */
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#define UARTx_C2_RWU ((uint8_t)0x02) /*!< Receiver Wakeup Control */
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#define UARTx_C2_SBK ((uint8_t)0x01) /*!< Send Break */
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/********* Bits definition for UARTx_S1 register **************/
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#define UARTx_S1_TDRE ((uint8_t)0x80) /*!< Transmit Data Register Empty Flag */
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#define UARTx_S1_TC ((uint8_t)0x40) /*!< Transmission Complete Flag */
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#define UARTx_S1_RDRF ((uint8_t)0x20) /*!< Receiver Data Register Full Flag */
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#define UARTx_S1_IDLE ((uint8_t)0x10) /*!< Idle Line Flag */
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#define UARTx_S1_OR ((uint8_t)0x08) /*!< Receiver Overrun Flag */
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#define UARTx_S1_NF ((uint8_t)0x04) /*!< Noise Flag */
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#define UARTx_S1_FE ((uint8_t)0x02) /*!< Framing Error Flag */
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#define UARTx_S1_PF ((uint8_t)0x01) /*!< Parity Error Flag */
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/********* Bits definition for UARTx_S2 register **************/
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#define UARTx_S2_LBKDIF ((uint8_t)0x80) /*!< LIN Break Detect Interrupt Flag */
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#define UARTx_S2_RXEDGIF ((uint8_t)0x40) /*!< UART_RX Pin Active Edge Interrupt Flag */
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#define UARTx_S2_MSBF ((uint8_t)0x20) /*!< MSB First */
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#define UARTx_S2_RXINV ((uint8_t)0x10) /*!< Receive Data Inversion */
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#define UARTx_S2_RWUID ((uint8_t)0x08) /*!< Receive Wake Up Idle Detect */
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#define UARTx_S2_BRK13 ((uint8_t)0x04) /*!< Break Character Generation Length */
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#define UARTx_S2_LBKDE ((uint8_t)0x02) /*!< LIN Break Detect Enable */
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#define UARTx_S2_RAF ((uint8_t)0x01) /*!< Receiver Active Flag */
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/********* Bits definition for UARTx_C3 register **************/
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#define UARTx_C3_R8 ((uint8_t)0x80) /*!< Ninth Data Bit for Receiver */
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#define UARTx_C3_T8 ((uint8_t)0x40) /*!< Ninth Data Bit for Transmitter */
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#define UARTx_C3_TXDIR ((uint8_t)0x20) /*!< UART_TX Pin Direction in Single-Wire Mode */
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#define UARTx_C3_TXINV ((uint8_t)0x10) /*!< Transmit Data Inversion */
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#define UARTx_C3_ORIE ((uint8_t)0x08) /*!< Overrun Interrupt Enable */
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#define UARTx_C3_NEIE ((uint8_t)0x04) /*!< Noise Error Interrupt Enable */
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#define UARTx_C3_FEIE ((uint8_t)0x02) /*!< Framing Error Interrupt Enable */
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#define UARTx_C3_PEIE ((uint8_t)0x01) /*!< Parity Error Interrupt Enable */
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/********* Bits definition for UARTx_D register ***************/
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#define UARTx_D_R7T7 ((uint8_t)0x80) /*!< Read receive data buffer 7 or write transmit data buffer 7 */
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#define UARTx_D_R6T6 ((uint8_t)0x40) /*!< Read receive data buffer 6 or write transmit data buffer 6 */
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#define UARTx_D_R5T5 ((uint8_t)0x20) /*!< Read receive data buffer 5 or write transmit data buffer 5 */
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#define UARTx_D_R4T4 ((uint8_t)0x10) /*!< Read receive data buffer 4 or write transmit data buffer 4 */
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#define UARTx_D_R3T3 ((uint8_t)0x08) /*!< Read receive data buffer 3 or write transmit data buffer 3 */
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#define UARTx_D_R2T2 ((uint8_t)0x04) /*!< Read receive data buffer 2 or write transmit data buffer 2 */
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#define UARTx_D_R1T1 ((uint8_t)0x02) /*!< Read receive data buffer 1 or write transmit data buffer 1 */
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#define UARTx_D_R0T0 ((uint8_t)0x01) /*!< Read receive data buffer 0 or write transmit data buffer 0 */
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/********* Bits definition for UARTx_MA1 register *************/
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#define UARTx_MA1_MA ((uint8_t)0xFF) /*!< Match Address */
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/********* Bits definition for UARTx_MA2 register *************/
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#define UARTx_MA2_MA ((uint8_t)0xFF) /*!< Match Address */
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/********* Bits definition for UARTx_C4 register **************/
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#define UARTx_C4_MAEN1 ((uint8_t)0x80) /*!< Match Address Mode Enable 1 */
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#define UARTx_C4_MAEN2 ((uint8_t)0x40) /*!< Match Address Mode Enable 2 */
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#define UARTx_C4_M10 ((uint8_t)0x20) /*!< 10-bit Mode Select */
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#define UARTx_C4_BRFA_MASK ((uint8_t)0x1F)
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#define UARTx_C4_BRFA(x) ((uint8_t)((uint8_t)(x) & UARTx_C4_BRFA_MASK)) /*!< Baud Rate Fine Adjust */
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/********* Bits definition for UARTx_C5 register **************/
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#define UARTx_C5_TDMAE ((uint8_t)0x80) /*!< Transmitter DMA Enable */
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#define UARTx_C5_RDMAE ((uint8_t)0x20) /*!< Receiver Full DMA Enable */
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#define UARTx_C5_BOTHEDGE ((uint8_t)0x02) /*!< Both Edge Sampling */
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#define UARTx_C5_RESYNCDIS ((uint8_t)0x01) /*!< Resynchronization Disable */
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/******* Bits definition for UARTx_CFIFO register ************/
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#define UARTx_CFIFO_TXFLUSH ((uint8_t)0x80) /*!< Transmit FIFO/Buffer Flush */
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#define UARTx_CFIFO_RXFLUSH ((uint8_t)0x40) /*!< Receive FIFO/Buffer Flush */
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#define UARTx_CFIFO_RXOFE ((uint8_t)0x04) /*!< Receive FIFO Overflow Interrupt Enable */
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#define UARTx_CFIFO_TXOFE ((uint8_t)0x02) /*!< Transmit FIFO Overflow Interrupt Enable */
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#define UARTx_CFIFO_RXUFE ((uint8_t)0x01) /*!< Receive FIFO Underflow Interrupt Enable */
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/******* Bits definition for UARTx_PFIFO register ************/
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#define UARTx_PFIFO_TXFE ((uint8_t)0x80) /*!< Transmit FIFO Enable */
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#define UARTx_PFIFO_TXFIFOSIZE_SHIFT 4
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#define UARTx_PFIFO_TXFIFOSIZE_MASK ((uint8_t)((uint8_t)0x7 << UARTx_PFIFO_TXFIFOSIZE_SHIFT))
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#define UARTx_PFIFO_TXFIFOSIZE(x) ((uint8_t)(((uint8_t)(x) << UARTx_PFIFO_TXFIFOSIZE_SHIFT) & UARTx_PFIFO_TXFIFOSIZE_MASK)) /*!< Transmit FIFO Buffer depth */
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#define UARTx_PFIFO_RXFE ((uint8_t)0x08) /*!< Receive FIFOh */
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#define UARTx_PFIFO_RXFIFOSIZE_SHIFT 0
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#define UARTx_PFIFO_RXFIFOSIZE_MASK ((uint8_t)((uint8_t)0x7 << UARTx_PFIFO_RXFIFOSIZE_SHIFT))
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#define UARTx_PFIFO_RXFIFOSIZE(x) ((uint8_t)(((uint8_t)(x) << UARTx_PFIFO_RXFIFOSIZE_SHIFT) & UARTx_PFIFO_RXFIFOSIZE_MASK)) /*!< Receive FIFO Buffer depth */
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/****************************************************************/
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/* */
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/* Power Management Controller (PMC) */
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/* */
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/****************************************************************/
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/********* Bits definition for PMC_LVDSC1 register *************/
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#define PMC_LVDSC1_LVDF ((uint8_t)0x80) /*!< Low-Voltage Detect Flag */
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#define PMC_LVDSC1_LVDACK ((uint8_t)0x40) /*!< Low-Voltage Detect Acknowledge */
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#define PMC_LVDSC1_LVDIE ((uint8_t)0x20) /*!< Low-Voltage Detect Interrupt Enable */
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#define PMC_LVDSC1_LVDRE ((uint8_t)0x10) /*!< Low-Voltage Detect Reset Enable */
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#define PMC_LVDSC1_LVDV_MASK ((uint8_t)0x3) /*!< Low-Voltage Detect Voltage Select */
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#define PMC_LVDSC1_LVDV_SHIFT 0
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#define PMC_LVDSC1_LVDV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC1_LVDV_SHIFT))&PMC_LVDSC1_LVDV_MASK)
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/********* Bits definition for PMC_LVDSC1 register *************/
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#define PMC_LVDSC2_LVWF ((uint8_t)0x80) /*!< Low-Voltage Warning Flag */
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#define PMC_LVDSC2_LVWACK ((uint8_t)0x40) /*!< Low-Voltage Warning Acknowledge */
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#define PMC_LVDSC2_LVWIE ((uint8_t)0x20) /*!< Low-Voltage Warning Interrupt Enable */
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#define PMC_LVDSC2_LVWV_MASK 0x3 /*!< Low-Voltage Warning Voltage Select */
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#define PMC_LVDSC2_LVWV_SHIFT 0
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#define PMC_LVDSC2_LVWV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC2_LVWV_SHIFT))&PMC_LVDSC2_LVWV_MASK)
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/********* Bits definition for PMC_REGSC register *************/
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#define PMC_REGSC_BGEN ((uint8_t)0x10) /*!< Bandgap Enable In VLPx Operation */
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#define PMC_REGSC_ACKISO ((uint8_t)0x8) /*!< Acknowledge Isolation */
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#define PMC_REGSC_REGONS ((uint8_t)0x4) /*!< Regulator In Run Regulation Status */
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#define PMC_REGSC_BGBE ((uint8_t)0x1) /*!< Bandgap Buffer Enable */
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/****************************************************************/
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/* */
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/* Watchdog */
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/* */
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/****************************************************************/
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/******** Bits definition for WDOG_STCTRLH register ***********/
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#define WDOG_STCTRLH_DISTESTWDOG ((uint16_t)0x4000)
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#define WDOG_STCTRLH_BYTESEL_1_0 ((uint16_t)0x3000)
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#define WDOG_STCTRLH_TESTSEL ((uint16_t)0x0800)
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#define WDOG_STCTRLH_TESTWDOG ((uint16_t)0x0400)
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#define WDOG_STCTRLH_WAITEN ((uint16_t)0x0080)
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#define WDOG_STCTRLH_STOPEN ((uint16_t)0x0040)
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#define WDOG_STCTRLH_DBGEN ((uint16_t)0x0020)
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#define WDOG_STCTRLH_ALLOWUPDATE ((uint16_t)0x0010)
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#define WDOG_STCTRLH_WINEN ((uint16_t)0x0008)
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#define WDOG_STCTRLH_IRQRSTEN ((uint16_t)0x0004)
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#define WDOG_STCTRLH_CLKSRC ((uint16_t)0x0002)
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#define WDOG_STCTRLH_WDOGEN ((uint16_t)0x0001)
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/******** Bits definition for WDOG_STCTRLL register ***********/
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#define WDOG_STCTRLL_INTFLG ((uint16_t)0x8000)
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/********* Bits definition for WDOG_PRESC register ************/
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#define WDOG_PRESC_PRESCVAL ((uint16_t)0x0700)
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#endif
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