148 lines
4.9 KiB
C
148 lines
4.9 KiB
C
/*
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ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio.
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This file is part of ChibiOS/RT.
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ChibiOS/RT is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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ChibiOS/RT is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/**
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* @file STM8L/hal_lld.c
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* @brief STM8L HAL subsystem low level driver source.
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*
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* @addtogroup HAL
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* @{
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*/
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#include "ch.h"
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#include "hal.h"
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/*===========================================================================*/
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/* Driver exported variables. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver local variables. */
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/*===========================================================================*/
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/**
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* @brief PAL setup.
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* @details Digital I/O ports static configuration as defined in @p board.h.
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*/
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ROMCONST PALConfig pal_default_config =
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{
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{
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{VAL_GPIOAODR, 0, VAL_GPIOADDR, VAL_GPIOACR1, VAL_GPIOACR2},
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{VAL_GPIOBODR, 0, VAL_GPIOBDDR, VAL_GPIOBCR1, VAL_GPIOBCR2},
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{VAL_GPIOCODR, 0, VAL_GPIOCDDR, VAL_GPIOCCR1, VAL_GPIOCCR2},
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{VAL_GPIODODR, 0, VAL_GPIODDDR, VAL_GPIODCR1, VAL_GPIODCR2},
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{VAL_GPIOEODR, 0, VAL_GPIOEDDR, VAL_GPIOECR1, VAL_GPIOECR2},
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{VAL_GPIOFODR, 0, VAL_GPIOFDDR, VAL_GPIOFCR1, VAL_GPIOFCR2},
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{VAL_GPIOGODR, 0, VAL_GPIOGDDR, VAL_GPIOGCR1, VAL_GPIOGCR2},
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#if defined(STM8L15X_MDP) || defined(STM8L15X_HD)
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{VAL_GPIOHODR, 0, VAL_GPIOHDDR, VAL_GPIOHCR1, VAL_GPIOHCR2},
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{VAL_GPIOIODR, 0, VAL_GPIOIDDR, VAL_GPIOICR1, VAL_GPIOICR2},
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#endif
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}
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};
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/*===========================================================================*/
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/* Driver local functions. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver interrupt handlers. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver exported functions. */
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/*===========================================================================*/
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/**
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* @brief Low level HAL driver initialization.
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* @details Clock sources initialization, HSI is assumed to be already
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* started after reset.
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* @note If the @p STM8L_CLOCK_INIT option is set to @p FALSE then the
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* initialization is not performed and is left to the application.
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*
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* @notapi
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*/
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void hal_lld_init(void) {
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#if STM8L_CLOCK_INIT
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/* Makes sure that HSI is stable before proceeding.*/
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CLK->ICKCR |= CLK_ICKCR_HSION;
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while ((CLK->ICKCR & CLK_ICKCR_HSIRDY) == 0)
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;
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/* LSI startup and stabilization if required.*/
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#if STM8L_LSI_ENABLED
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CLK->ICKCR |= CLK_ICKCR_LSION;
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while ((CLK->ICKCR & CLK_ICKCR_LSIRDY) == 0)
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;
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#endif
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/* HSE startup and stabilization if required.*/
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#if STM8L_HSE_ENABLED
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#if HSEBYPASS
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CLK->ECKCR |= CLK_ECKCR_HSEON | CLK_ECKCR_HSEBYP;
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#else
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CLK->ECKCR |= CLK_ECKCR_HSEON;
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#endif
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while ((CLK->ECKCR & CLK_ECKCR_HSERDY) == 0)
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;
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#endif
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/* LSE startup and stabilization if required.*/
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#if STM8L_LSE_ENABLED
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#if LSEBYPASS
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CLK->ECKCR |= CLK_ECKCR_LSEON | CLK_ECKCR_LSEBYP;
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#else
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CLK->ECKCR |= CLK_ECKCR_LSEON;
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#endif
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while ((CLK->ECKCR & CLK_ECKCR_LSERDY) == 0)
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;
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#endif
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/* Setting up clock dividers.*/
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CLK->CKDIVR = STM8L_SYSCLK_DIVIDER << 0;
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/* SYSCLK switch to the selected source, not necessary if it is HSI.*/
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#if STM8L_SYSCLK_SOURCE != CLK_SYSSEL_HSI
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/* Switching clock (manual switch mode).*/
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CLK->SWR = STM8_CLOCK_SOURCE;
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while ((CLK->SWCR & CLK_SWCR_SWIF) == 0)
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;
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CLK->SWCR = CLK_SWCR_SWEN;
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#endif
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/* Clocks initially all disabled, note the boot ROM clock is disabled
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because the boot loader is no more required and it draws pretious uAs.*/
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CLK->PCKENR1 = 0;
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CLK->PCKENR2 = 0;
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CLK->PCKENR3 = 0;
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/* Other clock related initializations.*/
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CLK->CSSR = 0;
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CLK->CCOR = 0;
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/* HSI disabled if it is no more required.*/
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#if !STM8L_HSI_ENABLED
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CLK->ICKCR &= ~CLK_ICKCR_HSION;
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#endif
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#endif /* STM8L_CLOCK_INIT */
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}
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/** @} */
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