993 lines
32 KiB
C
993 lines
32 KiB
C
/*
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ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
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2011,2012,2013 Giovanni Di Sirio.
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This file is part of ChibiOS/RT.
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ChibiOS/RT is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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ChibiOS/RT is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/**
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* @file STM32F0xx/hal_lld.h
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* @brief STM32F0xx HAL subsystem low level driver header.
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* @pre This module requires the following macros to be defined in the
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* @p board.h file:
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* - STM32_LSECLK.
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* - STM32_LSEDRV.
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* - STM32_LSE_BYPASS (optionally).
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* - STM32_HSECLK.
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* - STM32_HSE_BYPASS (optionally).
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* .
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* One of the following macros must also be defined:
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* - STM32F0XX for Entry Level devices.
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* .
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*
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* @addtogroup HAL
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* @{
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*/
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#ifndef _HAL_LLD_H_
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#define _HAL_LLD_H_
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#include "stm32.h"
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/*===========================================================================*/
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/* Driver constants. */
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/*===========================================================================*/
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/**
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* @brief Defines the support for realtime counters in the HAL.
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*/
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#define HAL_IMPLEMENTS_COUNTERS FALSE
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/**
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* @name Platform identification
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* @{
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*/
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#define PLATFORM_NAME "STM32F05x Entry Level"
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/** @} */
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/**
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* @name Absolute Maximum Ratings
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* @{
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*/
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/**
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* @brief Maximum system clock frequency.
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*/
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#define STM32_SYSCLK_MAX 48000000
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/**
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* @brief Maximum HSE clock frequency.
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*/
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#define STM32_HSECLK_MAX 32000000
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/**
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* @brief Minimum HSE clock frequency.
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*/
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#define STM32_HSECLK_MIN 1000000
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/**
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* @brief Maximum LSE clock frequency.
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*/
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#define STM32_LSECLK_MAX 1000000
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/**
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* @brief Minimum LSE clock frequency.
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*/
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#define STM32_LSECLK_MIN 32768
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/**
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* @brief Maximum PLLs input clock frequency.
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*/
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#define STM32_PLLIN_MAX 25000000
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/**
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* @brief Minimum PLLs input clock frequency.
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*/
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#define STM32_PLLIN_MIN 1000000
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/**
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* @brief Maximum PLL output clock frequency.
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*/
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#define STM32_PLLOUT_MAX 48000000
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/**
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* @brief Minimum PLL output clock frequency.
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*/
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#define STM32_PLLOUT_MIN 16000000
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/**
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* @brief Maximum APB clock frequency.
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*/
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#define STM32_PCLK_MAX 48000000
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/**
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* @brief Maximum ADC clock frequency.
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*/
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#define STM32_ADCCLK_MAX 14000000
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/** @} */
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/**
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* @name Internal clock sources
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* @{
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*/
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#define STM32_HSICLK 8000000 /**< High speed internal clock. */
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#define STM32_HSI14CLK 14000000 /**< 14MHz speed internal clock.*/
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#define STM32_LSICLK 40000 /**< Low speed internal clock. */
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/** @} */
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/**
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* @name PWR_CR register bits definitions
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* @{
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*/
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#define STM32_PLS_MASK (7 << 5) /**< PLS bits mask. */
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#define STM32_PLS_LEV0 (0 << 5) /**< PVD level 0. */
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#define STM32_PLS_LEV1 (1 << 5) /**< PVD level 1. */
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#define STM32_PLS_LEV2 (2 << 5) /**< PVD level 2. */
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#define STM32_PLS_LEV3 (3 << 5) /**< PVD level 3. */
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#define STM32_PLS_LEV4 (4 << 5) /**< PVD level 4. */
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#define STM32_PLS_LEV5 (5 << 5) /**< PVD level 5. */
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#define STM32_PLS_LEV6 (6 << 5) /**< PVD level 6. */
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#define STM32_PLS_LEV7 (7 << 5) /**< PVD level 7. */
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/** @} */
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/**
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* @name RCC_CFGR register bits definitions
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* @{
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*/
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#define STM32_SW_HSI (0 << 0) /**< SYSCLK source is HSI. */
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#define STM32_SW_HSE (1 << 0) /**< SYSCLK source is HSE. */
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#define STM32_SW_PLL (2 << 0) /**< SYSCLK source is PLL. */
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#define STM32_HPRE_DIV1 (0 << 4) /**< SYSCLK divided by 1. */
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#define STM32_HPRE_DIV2 (8 << 4) /**< SYSCLK divided by 2. */
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#define STM32_HPRE_DIV4 (9 << 4) /**< SYSCLK divided by 4. */
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#define STM32_HPRE_DIV8 (10 << 4) /**< SYSCLK divided by 8. */
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#define STM32_HPRE_DIV16 (11 << 4) /**< SYSCLK divided by 16. */
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#define STM32_HPRE_DIV64 (12 << 4) /**< SYSCLK divided by 64. */
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#define STM32_HPRE_DIV128 (13 << 4) /**< SYSCLK divided by 128. */
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#define STM32_HPRE_DIV256 (14 << 4) /**< SYSCLK divided by 256. */
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#define STM32_HPRE_DIV512 (15 << 4) /**< SYSCLK divided by 512. */
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#define STM32_PPRE_DIV1 (0 << 8) /**< HCLK divided by 1. */
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#define STM32_PPRE_DIV2 (4 << 8) /**< HCLK divided by 2. */
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#define STM32_PPRE_DIV4 (5 << 8) /**< HCLK divided by 4. */
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#define STM32_PPRE_DIV8 (6 << 8) /**< HCLK divided by 8. */
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#define STM32_PPRE_DIV16 (7 << 8) /**< HCLK divided by 16. */
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#define STM32_ADCPRE_DIV2 (0 << 14) /**< PCLK divided by 2. */
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#define STM32_ADCPRE_DIV4 (1 << 14) /**< PCLK divided by 4. */
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#define STM32_PLLSRC_HSI (0 << 16) /**< PLL clock source is HSI. */
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#define STM32_PLLSRC_HSE (1 << 16) /**< PLL clock source is HSE. */
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#define STM32_MCOSEL_NOCLOCK (0 << 24) /**< No clock on MCO pin. */
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#define STM32_MCOSEL_HSI14 (3 << 24) /**< HSI14 clock on MCO pin. */
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#define STM32_MCOSEL_SYSCLK (4 << 24) /**< SYSCLK on MCO pin. */
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#define STM32_MCOSEL_HSI (5 << 24) /**< HSI clock on MCO pin. */
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#define STM32_MCOSEL_HSE (6 << 24) /**< HSE clock on MCO pin. */
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#define STM32_MCOSEL_PLLDIV2 (7 << 24) /**< PLL/2 clock on MCO pin. */
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/** @} */
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/**
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* @name RCC_BDCR register bits definitions
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* @{
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*/
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#define STM32_RTCSEL_MASK (3 << 8) /**< RTC clock source mask. */
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#define STM32_RTCSEL_NOCLOCK (0 << 8) /**< No clock. */
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#define STM32_RTCSEL_LSE (1 << 8) /**< LSE used as RTC clock. */
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#define STM32_RTCSEL_LSI (2 << 8) /**< LSI used as RTC clock. */
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#define STM32_RTCSEL_HSEDIV (3 << 8) /**< HSE divided by 32 used as
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RTC clock. */
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/** @} */
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/**
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* @name RCC_CFGR3 register bits definitions
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* @{
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*/
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#define STM32_USART1SW_MASK (3 << 0) /**< USART1 clock source mask. */
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#define STM32_USART1SW_PCLK (0 << 0) /**< USART1 clock is PCLK. */
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#define STM32_USART1SW_SYSCLK (1 << 0) /**< USART1 clock is SYSCLK. */
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#define STM32_USART1SW_LSE (2 << 0) /**< USART1 clock is LSE. */
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#define STM32_USART1SW_HSI (3 << 0) /**< USART1 clock is HSI. */
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#define STM32_I2C1SW_MASK (1 << 4) /**< I2C clock source mask. */
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#define STM32_I2C1SW_HSI (0 << 4) /**< I2C clock is HSI. */
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#define STM32_I2C1SW_SYSCLK (1 << 4) /**< I2C clock is SYSCLK. */
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#define STM32_CECSW_MASK (1 << 6) /**< CEC clock source mask. */
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#define STM32_CECSW_HSI (0 << 6) /**< CEC clock is HSI/244. */
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#define STM32_CECSW_LSE (1 << 6) /**< CEC clock is LSE. */
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#define STM32_ADCSW_MASK (1 << 8) /**< ADC clock source mask. */
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#define STM32_ADCSW_HSI14 (0 << 8) /**< ADC clock is HSI14. */
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#define STM32_ADCSW_PCLK (1 << 8) /**< ADC clock is PCLK/2|4. */
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/** @} */
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/*===========================================================================*/
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/* Platform capabilities. */
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/*===========================================================================*/
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/**
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* @name STM32F0xx capabilities
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* @{
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*/
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/* ADC attributes.*/
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#define STM32_HAS_ADC1 TRUE
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#define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1) | \
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STM32_DMA_STREAM_ID_MSK(1, 2))
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#define STM32_ADC1_DMA_CHN 0x00000000
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#define STM32_HAS_ADC2 FALSE
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#define STM32_ADC2_DMA_MSK 0x00000000
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#define STM32_ADC2_DMA_CHN 0x00000000
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#define STM32_HAS_ADC3 FALSE
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#define STM32_ADC3_DMA_MSK 0x00000000
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#define STM32_ADC3_DMA_CHN 0x00000000
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#define STM32_HAS_ADC4 FALSE
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#define STM32_ADC4_DMA_MSK 0x00000000
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#define STM32_ADC4_DMA_CHN 0x00000000
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/* CAN attributes.*/
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#define STM32_HAS_CAN1 FALSE
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#define STM32_HAS_CAN2 FALSE
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#define STM32_CAN_MAX_FILTERS 0
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/* DAC attributes.*/
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#define STM32_HAS_DAC TRUE
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/* DMA attributes.*/
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#define STM32_ADVANCED_DMA FALSE
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#define STM32_HAS_DMA1 TRUE
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#define STM32_HAS_DMA2 FALSE
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/* ETH attributes.*/
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#define STM32_HAS_ETH FALSE
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/* EXTI attributes.*/
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#define STM32_EXTI_NUM_CHANNELS 28
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/* GPIO attributes.*/
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#define STM32_HAS_GPIOA TRUE
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#define STM32_HAS_GPIOB TRUE
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#define STM32_HAS_GPIOC TRUE
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#define STM32_HAS_GPIOD TRUE
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#define STM32_HAS_GPIOE FALSE
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#define STM32_HAS_GPIOF TRUE
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#define STM32_HAS_GPIOG FALSE
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#define STM32_HAS_GPIOH FALSE
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#define STM32_HAS_GPIOI FALSE
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/* I2C attributes.*/
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#define STM32_HAS_I2C1 TRUE
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#define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3))
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#define STM32_I2C1_RX_DMA_CHN 0x00000000
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#define STM32_I2C1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2))
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#define STM32_I2C1_TX_DMA_CHN 0x00000000
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#define STM32_HAS_I2C2 TRUE
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#define STM32_I2C2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5))
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#define STM32_I2C2_RX_DMA_CHN 0x00000000
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#define STM32_I2C2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4))
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#define STM32_I2C2_TX_DMA_CHN 0x00000000
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#define STM32_HAS_I2C3 FALSE
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#define STM32_I2C3_RX_DMA_MSK 0
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#define STM32_I2C3_RX_DMA_CHN 0x00000000
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#define STM32_I2C3_TX_DMA_MSK 0
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#define STM32_I2C3_TX_DMA_CHN 0x00000000
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/* RTC attributes.*/
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#define STM32_HAS_RTC TRUE
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#define STM32_RTC_HAS_SUBSECONDS FALSE
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#define STM32_RTC_IS_CALENDAR TRUE
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/* SDIO attributes.*/
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#define STM32_HAS_SDIO FALSE
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/* SPI attributes.*/
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#define STM32_HAS_SPI1 TRUE
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#define STM32_SPI1_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2)
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#define STM32_SPI1_RX_DMA_CHN 0x00000000
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#define STM32_SPI1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3)
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#define STM32_SPI1_TX_DMA_CHN 0x00000000
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#define STM32_HAS_SPI2 TRUE
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#define STM32_SPI2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
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#define STM32_SPI2_RX_DMA_CHN 0x00000000
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#define STM32_SPI2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5)
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#define STM32_SPI2_TX_DMA_CHN 0x00000000
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#define STM32_HAS_SPI3 FALSE
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#define STM32_SPI3_RX_DMA_MSK 0
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#define STM32_SPI3_RX_DMA_CHN 0x00000000
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#define STM32_SPI3_TX_DMA_MSK 0
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#define STM32_SPI3_TX_DMA_CHN 0x00000000
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/* TIM attributes.*/
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#define STM32_HAS_TIM1 TRUE
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#define STM32_HAS_TIM2 TRUE
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#define STM32_HAS_TIM3 TRUE
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#define STM32_HAS_TIM4 FALSE
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#define STM32_HAS_TIM5 FALSE
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#define STM32_HAS_TIM6 TRUE
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#define STM32_HAS_TIM7 FALSE
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#define STM32_HAS_TIM8 FALSE
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#define STM32_HAS_TIM9 FALSE
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#define STM32_HAS_TIM10 FALSE
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#define STM32_HAS_TIM11 FALSE
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#define STM32_HAS_TIM12 FALSE
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#define STM32_HAS_TIM13 FALSE
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#define STM32_HAS_TIM14 TRUE
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#define STM32_HAS_TIM15 TRUE
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#define STM32_HAS_TIM16 TRUE
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#define STM32_HAS_TIM17 TRUE
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#define STM32_HAS_TIM18 FALSE
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#define STM32_HAS_TIM19 FALSE
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/* USART attributes.*/
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#define STM32_HAS_USART1 TRUE
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#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) | \
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STM32_DMA_STREAM_ID_MSK(1, 5))
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#define STM32_USART1_RX_DMA_CHN 0x00000000
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#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) | \
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STM32_DMA_STREAM_ID_MSK(1, 4))
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#define STM32_USART1_TX_DMA_CHN 0x00000000
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#define STM32_HAS_USART2 TRUE
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#define STM32_USART2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5))
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#define STM32_USART2_RX_DMA_CHN 0x00000000
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#define STM32_USART2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4))
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#define STM32_USART2_TX_DMA_CHN 0x00000000
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#define STM32_HAS_USART3 FALSE
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#define STM32_USART3_RX_DMA_MSK 0
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#define STM32_USART3_RX_DMA_CHN 0x00000000
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#define STM32_USART3_TX_DMA_MSK 0
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#define STM32_USART3_TX_DMA_CHN 0x00000000
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#define STM32_HAS_UART4 FALSE
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#define STM32_UART4_RX_DMA_MSK 0
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#define STM32_UART4_RX_DMA_CHN 0x00000000
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#define STM32_UART4_TX_DMA_MSK 0
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#define STM32_UART4_TX_DMA_CHN 0x00000000
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#define STM32_HAS_UART5 FALSE
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#define STM32_UART5_RX_DMA_MSK 0
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#define STM32_UART5_RX_DMA_CHN 0x00000000
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#define STM32_UART5_TX_DMA_MSK 0
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#define STM32_UART5_TX_DMA_CHN 0x00000000
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#define STM32_HAS_USART6 FALSE
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#define STM32_USART6_RX_DMA_MSK 0
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#define STM32_USART6_RX_DMA_CHN 0x00000000
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#define STM32_USART6_TX_DMA_MSK 0
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#define STM32_USART6_TX_DMA_CHN 0x00000000
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/* USB attributes.*/
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#define STM32_HAS_USB TRUE
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#define STM32_HAS_OTG1 FALSE
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#define STM32_HAS_OTG2 FALSE
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/** @} */
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/*===========================================================================*/
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/* Platform specific friendly IRQ names. */
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/*===========================================================================*/
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/**
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* @name IRQ VECTOR names
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* @{
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*/
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#define WWDG_IRQHandler Vector40 /**< Window Watchdog. */
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#define PVD_IRQHandler Vector44 /**< PVD through EXTI Line
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detect. */
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#define RTC_IRQHandler Vector48 /**< RTC through EXTI Line
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Interrupt. */
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#define FLASH_IRQHandler Vector4C /**< Flash. */
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#define RCC_IRQHandler Vector50 /**< RCC. */
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#define EXTI0_1_IRQHandler Vector54 /**< EXTI Line 0..1. */
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#define EXTI2_3_IRQHandler Vector58 /**< EXTI Line 2..3. */
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#define EXTI4_15_IRQHandler Vector5C /**< EXTI Line 4..15. */
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#define TS_IRQHandler Vector60 /**< TS. */
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#define DMA1_Ch1_IRQHandler Vector64 /**< DMA1 Channel 1. */
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#define DMA1_Ch2_3_IRQHandler Vector68 /**< DMA1 Channels 2 and 3. */
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#define DMA1_Ch4_5_IRQHandler Vector6C /**< DMA1 Channels 4 and 5. */
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#define ADC1_COMP_IRQHandler Vector70 /**< ADC1 comparators 1 and 2. */
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#define TIM1_BRK_UP_TRG_COM_IRQHandler Vector74 /**< TIM1 common. */
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#define TIM1_CC_IRQHandler Vector78 /**< TIM1 Capture Compare. */
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#define TIM2_IRQHandler Vector7C /**< TIM2. */
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#define TIM3_IRQHandler Vector80 /**< TIM3. */
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#define TIM6_DAC_IRQHandler Vector84 /**< TIM6 and DAC. */
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#define TIM14_IRQHandler Vector8C /**< TIM14. */
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#define TIM15_IRQHandler Vector90 /**< TIM15. */
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#define TIM16_IRQHandler Vector94 /**< TIM16. */
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#define TIM17_IRQHandler Vector98 /**< TIM17. */
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#define I2C1_IRQHandler Vector9C /**< I2C1. */
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#define I2C2_IRQHandler VectorA0 /**< I2C2. */
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#define SPI1_IRQHandler VectorA4 /**< SPI1. */
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#define SPI2_IRQHandler VectorA8 /**< SPI2. */
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#define USART1_IRQHandler VectorAC /**< USART1. */
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#define USART2_IRQHandler VectorB0 /**< USART2. */
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#define CEC_IRQHandler VectorB8 /**< CEC. */
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/** @} */
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/*===========================================================================*/
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/* Driver pre-compile time settings. */
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/*===========================================================================*/
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/**
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* @name Configuration options
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* @{
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*/
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/**
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* @brief Disables the PWR/RCC initialization in the HAL.
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*/
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#if !defined(STM32_NO_INIT) || defined(__DOXYGEN__)
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#define STM32_NO_INIT FALSE
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#endif
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/**
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* @brief Enables or disables the programmable voltage detector.
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*/
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#if !defined(STM32_PVD_ENABLE) || defined(__DOXYGEN__)
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#define STM32_PVD_ENABLE FALSE
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#endif
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/**
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* @brief Sets voltage level for programmable voltage detector.
|
|
*/
|
|
#if !defined(STM32_PLS) || defined(__DOXYGEN__)
|
|
#define STM32_PLS STM32_PLS_LEV0
|
|
#endif
|
|
|
|
/**
|
|
* @brief Enables or disables the HSI clock source.
|
|
*/
|
|
#if !defined(STM32_HSI_ENABLED) || defined(__DOXYGEN__)
|
|
#define STM32_HSI_ENABLED TRUE
|
|
#endif
|
|
|
|
/**
|
|
* @brief Enables or disables the HSI14 clock source.
|
|
*/
|
|
#if !defined(STM32_HSI14_ENABLED) || defined(__DOXYGEN__)
|
|
#define STM32_HSI14_ENABLED TRUE
|
|
#endif
|
|
|
|
/**
|
|
* @brief Enables or disables the LSI clock source.
|
|
*/
|
|
#if !defined(STM32_LSI_ENABLED) || defined(__DOXYGEN__)
|
|
#define STM32_LSI_ENABLED FALSE
|
|
#endif
|
|
|
|
/**
|
|
* @brief Enables or disables the HSE clock source.
|
|
*/
|
|
#if !defined(STM32_HSE_ENABLED) || defined(__DOXYGEN__)
|
|
#define STM32_HSE_ENABLED TRUE
|
|
#endif
|
|
|
|
/**
|
|
* @brief Enables or disables the LSE clock source.
|
|
*/
|
|
#if !defined(STM32_LSE_ENABLED) || defined(__DOXYGEN__)
|
|
#define STM32_LSE_ENABLED FALSE
|
|
#endif
|
|
|
|
/**
|
|
* @brief Main clock source selection.
|
|
* @note If the selected clock source is not the PLL then the PLL is not
|
|
* initialized and started.
|
|
* @note The default value is calculated for a 48MHz system clock from
|
|
* a 8MHz crystal using the PLL.
|
|
*/
|
|
#if !defined(STM32_SW) || defined(__DOXYGEN__)
|
|
#define STM32_SW STM32_SW_PLL
|
|
#endif
|
|
|
|
/**
|
|
* @brief Clock source for the PLL.
|
|
* @note This setting has only effect if the PLL is selected as the
|
|
* system clock source.
|
|
* @note The default value is calculated for a 48MHz system clock from
|
|
* a 8MHz crystal using the PLL.
|
|
*/
|
|
#if !defined(STM32_PLLSRC) || defined(__DOXYGEN__)
|
|
#define STM32_PLLSRC STM32_PLLSRC_HSE
|
|
#endif
|
|
|
|
/**
|
|
* @brief Crystal PLL pre-divider.
|
|
* @note This setting has only effect if the PLL is selected as the
|
|
* system clock source.
|
|
* @note The default value is calculated for a 72MHz system clock from
|
|
* a 8MHz crystal using the PLL.
|
|
*/
|
|
#if !defined(STM32_PREDIV_VALUE) || defined(__DOXYGEN__)
|
|
#define STM32_PREDIV_VALUE 1
|
|
#endif
|
|
|
|
/**
|
|
* @brief PLL multiplier value.
|
|
* @note The allowed range is 2...16.
|
|
* @note The default value is calculated for a 48MHz system clock from
|
|
* a 8MHz crystal using the PLL.
|
|
*/
|
|
#if !defined(STM32_PLLMUL_VALUE) || defined(__DOXYGEN__)
|
|
#define STM32_PLLMUL_VALUE 6
|
|
#endif
|
|
|
|
/**
|
|
* @brief AHB prescaler value.
|
|
* @note The default value is calculated for a 48MHz system clock from
|
|
* a 8MHz crystal using the PLL.
|
|
*/
|
|
#if !defined(STM32_HPRE) || defined(__DOXYGEN__)
|
|
#define STM32_HPRE STM32_HPRE_DIV1
|
|
#endif
|
|
|
|
/**
|
|
* @brief APB1 prescaler value.
|
|
*/
|
|
#if !defined(STM32_PPRE) || defined(__DOXYGEN__)
|
|
#define STM32_PPRE STM32_PPRE_DIV1
|
|
#endif
|
|
|
|
/**
|
|
* @brief MCO pin setting.
|
|
*/
|
|
#if !defined(STM32_MCOSEL) || defined(__DOXYGEN__)
|
|
#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK
|
|
#endif
|
|
|
|
/**
|
|
* @brief ADC prescaler value.
|
|
*/
|
|
#if !defined(STM32_ADCPRE) || defined(__DOXYGEN__)
|
|
#define STM32_ADCPRE STM32_ADCPRE_DIV4
|
|
#endif
|
|
|
|
/**
|
|
* @brief ADC clock source.
|
|
*/
|
|
#if !defined(STM32_ADCSW) || defined(__DOXYGEN__)
|
|
#define STM32_ADCSW STM32_ADCSW_HSI14
|
|
#endif
|
|
|
|
/**
|
|
* @brief CEC clock source.
|
|
*/
|
|
#if !defined(STM32_CECSW) || defined(__DOXYGEN__)
|
|
#define STM32_CECSW STM32_CECSW_HSI
|
|
#endif
|
|
|
|
/**
|
|
* @brief I2C1 clock source.
|
|
*/
|
|
#if !defined(STM32_I2C1SW) || defined(__DOXYGEN__)
|
|
#define STM32_I2C1SW STM32_I2C1SW_HSI
|
|
#endif
|
|
|
|
/**
|
|
* @brief USART1 clock source.
|
|
*/
|
|
#if !defined(STM32_USART1SW) || defined(__DOXYGEN__)
|
|
#define STM32_USART1SW STM32_USART1SW_PCLK
|
|
#endif
|
|
|
|
/**
|
|
* @brief RTC clock source.
|
|
*/
|
|
#if !defined(STM32_RTCSEL) || defined(__DOXYGEN__)
|
|
#define STM32_RTCSEL STM32_RTCSEL_LSI
|
|
#endif
|
|
/** @} */
|
|
|
|
/*===========================================================================*/
|
|
/* Derived constants and error checks. */
|
|
/*===========================================================================*/
|
|
|
|
/*
|
|
* Configuration-related checks.
|
|
*/
|
|
#if !defined(STM32F0xx_MCUCONF)
|
|
#error "Using a wrong mcuconf.h file, STM32F0xx_MCUCONF not defined"
|
|
#endif
|
|
|
|
/*
|
|
* HSI related checks.
|
|
*/
|
|
#if STM32_HSI_ENABLED
|
|
#else /* !STM32_HSI_ENABLED */
|
|
|
|
#if STM32_SW == STM32_SW_HSI
|
|
#error "HSI not enabled, required by STM32_SW"
|
|
#endif
|
|
|
|
#if STM32_CECSW == STM32_CECSW_HSI
|
|
#error "HSI not enabled, required by STM32_CECSW"
|
|
#endif
|
|
|
|
#if STM32_I2C1SW == STM32_I2C1SW_HSI
|
|
#error "HSI not enabled, required by STM32_I2C1SW"
|
|
#endif
|
|
|
|
#if STM32_USART1SW == STM32_USART1SW_HSI
|
|
#error "HSI not enabled, required by STM32_USART1SW"
|
|
#endif
|
|
|
|
#if (STM32_SW == STM32_SW_PLL) && (STM32_PLLSRC == STM32_PLLSRC_HSI)
|
|
#error "HSI not enabled, required by STM32_SW and STM32_PLLSRC"
|
|
#endif
|
|
|
|
#if (STM32_MCOSEL == STM32_MCOSEL_HSI) || \
|
|
((STM32_MCOSEL == STM32_MCOSEL_PLLDIV2) && \
|
|
(STM32_PLLSRC == STM32_PLLSRC_HSI))
|
|
#error "HSI not enabled, required by STM32_MCOSEL"
|
|
#endif
|
|
|
|
#endif /* !STM32_HSI_ENABLED */
|
|
|
|
/*
|
|
* HSI14 related checks.
|
|
*/
|
|
#if STM32_HSI14_ENABLED
|
|
#else /* !STM32_HSI14_ENABLED */
|
|
|
|
#if STM32_MCOSEL == STM32_MCOSEL_HSI14
|
|
#error "HSI14 not enabled, required by STM32_MCOSEL"
|
|
#endif
|
|
|
|
#if STM32_ADCSW == STM32_ADCSW_HSI14
|
|
#error "HSI14 not enabled, required by STM32_ADCSW"
|
|
#endif
|
|
|
|
#endif /* !STM32_HSI14_ENABLED */
|
|
|
|
/*
|
|
* HSE related checks.
|
|
*/
|
|
#if STM32_HSE_ENABLED
|
|
|
|
#if STM32_HSECLK == 0
|
|
#error "HSE frequency not defined"
|
|
#elif (STM32_HSECLK < STM32_HSECLK_MIN) || (STM32_HSECLK > STM32_HSECLK_MAX)
|
|
#error "STM32_HSECLK outside acceptable range (STM32_HSECLK_MIN...STM32_HSECLK_MAX)"
|
|
#endif
|
|
|
|
#else /* !STM32_HSE_ENABLED */
|
|
|
|
#if STM32_SW == STM32_SW_HSE
|
|
#error "HSE not enabled, required by STM32_SW"
|
|
#endif
|
|
|
|
#if (STM32_SW == STM32_SW_PLL) && (STM32_PLLSRC == STM32_PLLSRC_HSE)
|
|
#error "HSE not enabled, required by STM32_SW and STM32_PLLSRC"
|
|
#endif
|
|
|
|
#if (STM32_MCOSEL == STM32_MCOSEL_HSE) || \
|
|
((STM32_MCOSEL == STM32_MCOSEL_PLLDIV2) && \
|
|
(STM32_PLLSRC == STM32_PLLSRC_HSE))
|
|
#error "HSE not enabled, required by STM32_MCOSEL"
|
|
#endif
|
|
|
|
#if STM32_RTCSEL == STM32_RTCSEL_HSEDIV
|
|
#error "HSE not enabled, required by STM32_RTCSEL"
|
|
#endif
|
|
|
|
#endif /* !STM32_HSE_ENABLED */
|
|
|
|
/*
|
|
* LSI related checks.
|
|
*/
|
|
#if STM32_LSI_ENABLED
|
|
#else /* !STM32_LSI_ENABLED */
|
|
|
|
#if STM32_RTCSEL == STM32_RTCSEL_LSI
|
|
#error "LSI not enabled, required by STM32_RTCSEL"
|
|
#endif
|
|
|
|
#endif /* !STM32_LSI_ENABLED */
|
|
|
|
/*
|
|
* LSE related checks.
|
|
*/
|
|
#if STM32_LSE_ENABLED
|
|
|
|
#if (STM32_LSECLK == 0)
|
|
#error "LSE frequency not defined"
|
|
#endif
|
|
|
|
#if (STM32_LSECLK < STM32_LSECLK_MIN) || (STM32_LSECLK > STM32_LSECLK_MAX)
|
|
#error "STM32_LSECLK outside acceptable range (STM32_LSECLK_MIN...STM32_LSECLK_MAX)"
|
|
#endif
|
|
|
|
#if !defined(STM32_LSEDRV)
|
|
#error "STM32_LSEDRV not defined"
|
|
#endif
|
|
|
|
#if (STM32_LSEDRV >> 3) > 3
|
|
#error "STM32_LSEDRV outside acceptable range ((0<<3)...(3<<3))"
|
|
#endif
|
|
|
|
#if STM32_CECSW == STM32_CECSW_LSE
|
|
#error "LSE not enabled, required by STM32_CECSW"
|
|
#endif
|
|
|
|
#if STM32_USART1SW == STM32_USART1SW_LSE
|
|
#error "LSE not enabled, required by STM32_USART1SW"
|
|
#endif
|
|
|
|
#else /* !STM32_LSE_ENABLED */
|
|
|
|
#if STM32_RTCSEL == STM32_RTCSEL_LSE
|
|
#error "LSE not enabled, required by STM32_RTCSEL"
|
|
#endif
|
|
|
|
#endif /* !STM32_LSE_ENABLED */
|
|
|
|
/* PLL activation conditions.*/
|
|
#if (STM32_SW == STM32_SW_PLL) || \
|
|
(STM32_MCOSEL == STM32_MCOSEL_PLLDIV2) || \
|
|
defined(__DOXYGEN__)
|
|
/**
|
|
* @brief PLL activation flag.
|
|
*/
|
|
#define STM32_ACTIVATE_PLL TRUE
|
|
#else
|
|
#define STM32_ACTIVATE_PLL FALSE
|
|
#endif
|
|
|
|
/* HSE prescaler setting check.*/
|
|
#if ((STM32_PREDIV_VALUE >= 1) || (STM32_PREDIV_VALUE <= 16))
|
|
#define STM32_PREDIV ((STM32_PREDIV_VALUE - 1) << 0)
|
|
#else
|
|
#error "invalid STM32_PREDIV value specified"
|
|
#endif
|
|
|
|
/**
|
|
* @brief PLLMUL field.
|
|
*/
|
|
#if ((STM32_PLLMUL_VALUE >= 2) && (STM32_PLLMUL_VALUE <= 16)) || \
|
|
defined(__DOXYGEN__)
|
|
#define STM32_PLLMUL ((STM32_PLLMUL_VALUE - 2) << 18)
|
|
#else
|
|
#error "invalid STM32_PLLMUL_VALUE value specified"
|
|
#endif
|
|
|
|
/**
|
|
* @brief PLL input clock frequency.
|
|
*/
|
|
#if (STM32_PLLSRC == STM32_PLLSRC_HSE) || defined(__DOXYGEN__)
|
|
#define STM32_PLLCLKIN (STM32_HSECLK / STM32_PREDIV_VALUE)
|
|
#elif STM32_PLLSRC == STM32_PLLSRC_HSI
|
|
#define STM32_PLLCLKIN (STM32_HSICLK / 2)
|
|
#else
|
|
#error "invalid STM32_PLLSRC value specified"
|
|
#endif
|
|
|
|
/* PLL input frequency range check.*/
|
|
#if (STM32_PLLCLKIN < STM32_PLLIN_MIN) || (STM32_PLLCLKIN > STM32_PLLIN_MAX)
|
|
#error "STM32_PLLCLKIN outside acceptable range (STM32_PLLIN_MIN...STM32_PLLIN_MAX)"
|
|
#endif
|
|
|
|
/**
|
|
* @brief PLL output clock frequency.
|
|
*/
|
|
#define STM32_PLLCLKOUT (STM32_PLLCLKIN * STM32_PLLMUL_VALUE)
|
|
|
|
/* PLL output frequency range check.*/
|
|
#if (STM32_PLLCLKOUT < STM32_PLLOUT_MIN) || (STM32_PLLCLKOUT > STM32_PLLOUT_MAX)
|
|
#error "STM32_PLLCLKOUT outside acceptable range (STM32_PLLOUT_MIN...STM32_PLLOUT_MAX)"
|
|
#endif
|
|
|
|
/**
|
|
* @brief System clock source.
|
|
*/
|
|
#if (STM32_SW == STM32_SW_PLL) || defined(__DOXYGEN__)
|
|
#define STM32_SYSCLK STM32_PLLCLKOUT
|
|
#elif (STM32_SW == STM32_SW_HSI)
|
|
#define STM32_SYSCLK STM32_HSICLK
|
|
#elif (STM32_SW == STM32_SW_HSE)
|
|
#define STM32_SYSCLK STM32_HSECLK
|
|
#else
|
|
#error "invalid STM32_SW value specified"
|
|
#endif
|
|
|
|
/* Check on the system clock.*/
|
|
#if STM32_SYSCLK > STM32_SYSCLK_MAX
|
|
#error "STM32_SYSCLK above maximum rated frequency (STM32_SYSCLK_MAX)"
|
|
#endif
|
|
|
|
/**
|
|
* @brief AHB frequency.
|
|
*/
|
|
#if (STM32_HPRE == STM32_HPRE_DIV1) || defined(__DOXYGEN__)
|
|
#define STM32_HCLK (STM32_SYSCLK / 1)
|
|
#elif STM32_HPRE == STM32_HPRE_DIV2
|
|
#define STM32_HCLK (STM32_SYSCLK / 2)
|
|
#elif STM32_HPRE == STM32_HPRE_DIV4
|
|
#define STM32_HCLK (STM32_SYSCLK / 4)
|
|
#elif STM32_HPRE == STM32_HPRE_DIV8
|
|
#define STM32_HCLK (STM32_SYSCLK / 8)
|
|
#elif STM32_HPRE == STM32_HPRE_DIV16
|
|
#define STM32_HCLK (STM32_SYSCLK / 16)
|
|
#elif STM32_HPRE == STM32_HPRE_DIV64
|
|
#define STM32_HCLK (STM32_SYSCLK / 64)
|
|
#elif STM32_HPRE == STM32_HPRE_DIV128
|
|
#define STM32_HCLK (STM32_SYSCLK / 128)
|
|
#elif STM32_HPRE == STM32_HPRE_DIV256
|
|
#define STM32_HCLK (STM32_SYSCLK / 256)
|
|
#elif STM32_HPRE == STM32_HPRE_DIV512
|
|
#define STM32_HCLK (STM32_SYSCLK / 512)
|
|
#else
|
|
#error "invalid STM32_HPRE value specified"
|
|
#endif
|
|
|
|
/* AHB frequency check.*/
|
|
#if STM32_HCLK > STM32_SYSCLK_MAX
|
|
#error "STM32_HCLK exceeding maximum frequency (STM32_SYSCLK_MAX)"
|
|
#endif
|
|
|
|
/**
|
|
* @brief APB frequency.
|
|
*/
|
|
#if (STM32_PPRE == STM32_PPRE_DIV1) || defined(__DOXYGEN__)
|
|
#define STM32_PCLK (STM32_HCLK / 1)
|
|
#elif STM32_PPRE == STM32_PPRE_DIV2
|
|
#define STM32_PCLK (STM32_HCLK / 2)
|
|
#elif STM32_PPRE == STM32_PPRE_DIV4
|
|
#define STM32_PCLK (STM32_HCLK / 4)
|
|
#elif STM32_PPRE == STM32_PPRE_DIV8
|
|
#define STM32_PCLK (STM32_HCLK / 8)
|
|
#elif STM32_PPRE == STM32_PPRE_DIV16
|
|
#define STM32_PCLK (STM32_HCLK / 16)
|
|
#else
|
|
#error "invalid STM32_PPRE value specified"
|
|
#endif
|
|
|
|
/* APB frequency check.*/
|
|
#if STM32_PCLK > STM32_PCLK_MAX
|
|
#error "STM32_PCLK exceeding maximum frequency (STM32_PCLK_MAX)"
|
|
#endif
|
|
|
|
/**
|
|
* @brief RTC clock.
|
|
*/
|
|
#if (STM32_RTCSEL == STM32_RTCSEL_LSE) || defined(__DOXYGEN__)
|
|
#define STM32_RTCCLK STM32_LSECLK
|
|
#elif STM32_RTCSEL == STM32_RTCSEL_LSI
|
|
#define STM32_RTCCLK STM32_LSICLK
|
|
#elif STM32_RTCSEL == STM32_RTCSEL_HSEDIV
|
|
#define STM32_RTCCLK (STM32_HSECLK / 32)
|
|
#elif STM32_RTCSEL == STM32_RTCSEL_NOCLOCK
|
|
#define STM32_RTCCLK 0
|
|
#else
|
|
#error "invalid source selected for RTC clock"
|
|
#endif
|
|
|
|
/**
|
|
* @brief ADC frequency.
|
|
*/
|
|
#if STM32_ADCSW == STM32_ADCSW_HSI14
|
|
#define STM32_ADCCLK STM32_HSI14CLK
|
|
#elif STM32_ADCSW == STM32_ADCSW_PCLK
|
|
#if (STM32_ADCPRE == STM32_ADCPRE_DIV2) || defined(__DOXYGEN__)
|
|
#define STM32_ADCCLK (STM32_PCLK / 2)
|
|
#elif STM32_ADCPRE == STM32_ADCPRE_DIV4
|
|
#define STM32_ADCCLK (STM32_PCLK / 4)
|
|
#else
|
|
#error "invalid STM32_ADCPRE value specified"
|
|
#endif
|
|
#else
|
|
#error "invalid source selected for ADC clock"
|
|
#endif
|
|
|
|
/* ADC frequency check.*/
|
|
#if STM32_ADCCLK > STM32_ADCCLK_MAX
|
|
#error "STM32_ADCCLK exceeding maximum frequency (STM32_ADCCLK_MAX)"
|
|
#endif
|
|
|
|
/**
|
|
* @brief CEC frequency.
|
|
*/
|
|
#if STM32_CECSW == STM32_CECSW_HSI
|
|
#define STM32_CECCLK STM32_HSICLK
|
|
#elif STM32_CECSW == STM32_CECSW_LSE
|
|
#define STM32_CECCLK STM32_LSECLK
|
|
#else
|
|
#error "invalid source selected for CEC clock"
|
|
#endif
|
|
|
|
/**
|
|
* @brief I2C1 frequency.
|
|
*/
|
|
#if STM32_I2CSW == STM32_I2C1SW_HSI
|
|
#define STM32_I2C1CLK STM32_HSICLK
|
|
#elif STM32_I2CSW == STM32_I2C1SW_SYSCLK
|
|
#define STM32_I2C1CLK STM32_SYSCLK
|
|
#else
|
|
#error "invalid source selected for I2C1 clock"
|
|
#endif
|
|
|
|
/**
|
|
* @brief USART1 frequency.
|
|
*/
|
|
#if STM32_USART1SW == STM32_USART1SW_PCLK
|
|
#define STM32_USART1CLK STM32_PCLK
|
|
#elif STM32_USART1SW == STM32_USART1SW_SYSCLK
|
|
#define STM32_USART1CLK STM32_SYSCLK
|
|
#elif STM32_USART1SW == STM32_USART1SW_LSECLK
|
|
#define STM32_USART1CLK STM32_LSECLK
|
|
#elif STM32_USART1SW == STM32_USART1SW_HSICLK
|
|
#define STM32_USART1CLK STM32_HSICLK
|
|
#else
|
|
#error "invalid source selected for USART1 clock"
|
|
#endif
|
|
|
|
/**
|
|
* @brief USART2 frequency.
|
|
*/
|
|
#define STM32_USART2CLK STM32_PCLK
|
|
|
|
/**
|
|
* @brief Timers clock.
|
|
*/
|
|
#if (STM32_PPRE == STM32_PPRE_DIV1) || defined(__DOXYGEN__)
|
|
#define STM32_TIMCLK1 (STM32_PCLK * 1)
|
|
#define STM32_TIMCLK2 (STM32_PCLK * 1)
|
|
#else
|
|
#define STM32_TIMCLK1 (STM32_PCLK * 2)
|
|
#define STM32_TIMCLK2 (STM32_PCLK * 2)
|
|
#endif
|
|
|
|
/**
|
|
* @brief Flash settings.
|
|
*/
|
|
#if (STM32_HCLK <= 24000000) || defined(__DOXYGEN__)
|
|
#define STM32_FLASHBITS 0x00000010
|
|
#else
|
|
#define STM32_FLASHBITS 0x00000011
|
|
#endif
|
|
|
|
/*===========================================================================*/
|
|
/* Driver data structures and types. */
|
|
/*===========================================================================*/
|
|
|
|
/*===========================================================================*/
|
|
/* Driver macros. */
|
|
/*===========================================================================*/
|
|
|
|
/*===========================================================================*/
|
|
/* External declarations. */
|
|
/*===========================================================================*/
|
|
|
|
/* STM32 ISR, DMA and RCC helpers.*/
|
|
#include "stm32_isr.h"
|
|
#include "stm32_dma.h"
|
|
#include "stm32_rcc.h"
|
|
|
|
#ifdef __cplusplus
|
|
extern "C" {
|
|
#endif
|
|
void hal_lld_init(void);
|
|
void stm32_clock_init(void);
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|
|
|
|
#endif /* _HAL_LLD_H_ */
|
|
|
|
/** @} */
|