166 lines
5.7 KiB
C
166 lines
5.7 KiB
C
/*
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ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio.
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This file is part of ChibiOS/RT.
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ChibiOS/RT is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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ChibiOS/RT is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/**
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* @file ARMCMx/chcore.c
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* @brief ARM Cortex-Mx architecture port code.
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*
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* @addtogroup ARMCMx_CORE
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* @{
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*/
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#include "ch.h"
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#include "nvic.h"
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/**
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* @brief PC register temporary storage.
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*/
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regarm_t _port_saved_pc;
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/**
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* @brief IRQ nesting counter.
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*/
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unsigned _port_irq_nesting;
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/**
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* @brief Halts the system.
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* @note The function is declared as a weak symbol, it is possible
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* to redefine it in your application code.
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*/
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#if !defined(__DOXYGEN__)
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__attribute__((weak))
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#endif
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void port_halt(void) {
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port_disable();
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while (TRUE) {
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}
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}
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/**
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* @brief System Timer vector.
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* @details This interrupt is used as system tick.
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* @note The timer must be initialized in the startup code.
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*/
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CH_IRQ_HANDLER(SysTickVector) {
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CH_IRQ_PROLOGUE();
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chSysLockFromIsr();
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chSysTimerHandlerI();
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chSysUnlockFromIsr();
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CH_IRQ_EPILOGUE();
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}
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/**
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* @brief Post-IRQ switch code.
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* @details On entry the stack and the registers are restored by the exception
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* return, the PC value is stored in @p _port_saved_pc, the interrupts
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* are disabled.
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*/
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#if !defined(__DOXYGEN__)
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__attribute__((naked))
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#endif
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void _port_switch_from_irq(void) {
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/* Note, saves r4 to make space for the PC.*/
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asm volatile ("push {r0, r1, r2, r3, r4} \n\t" \
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"mov r0, r12 \n\t" \
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"mrs r1, XPSR \n\t" \
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"push {r0, r1, lr} \n\t" \
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"ldr r0, =_port_saved_pc \n\t" \
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"ldr r0, [r0] \n\t" \
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"add r0, r0, #1 \n\t" \
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"str r0, [sp, #28]");
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chSchDoRescheduleI();
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/* Note, the PC is restored alone after re-enabling the interrupts in
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order to minimize the (very remote and unlikely) possibility that
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the stack is filled by continous and saturating interrups that would
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not allow that last word to be pulled out of the stack.*/
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asm volatile ("pop {r0, r1, r2} \n\t" \
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"mov r12, r0 \n\t" \
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"msr XPSR, r1 \n\t" \
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"mov lr, r2 \n\t" \
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"pop {r0, r1, r2, r3} \n\t" \
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"cpsie i \n\t" \
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"pop {pc}");
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}
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#if CORTEX_MODEL == CORTEX_M0
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#define PUSH_CONTEXT(sp) { \
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asm volatile ("push {r4, r5, r6, r7, lr} \n\t" \
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"mov r4, r8 \n\t" \
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"mov r5, r9 \n\t" \
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"mov r6, r10 \n\t" \
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"mov r7, r11 \n\t" \
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"push {r4, r5, r6, r7}"); \
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}
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#define POP_CONTEXT(sp) { \
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asm volatile ("pop {r4, r5, r6, r7} \n\t" \
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"mov r8, r4 \n\t" \
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"mov r9, r5 \n\t" \
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"mov r10, r6 \n\t" \
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"mov r11, r7 \n\t" \
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"pop {r4, r5, r6, r7, pc}" : : "r" (sp)); \
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}
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#else /* CORTEX_MODEL != CORTEX_M0 */
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#endif /* CORTEX_MODEL != CORTEX_M0 */
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/**
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* @brief Performs a context switch between two threads.
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* @details This is the most critical code in any port, this function
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* is responsible for the context switch between 2 threads.
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* @note The implementation of this code affects <b>directly</b> the context
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* switch performance so optimize here as much as you can.
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*
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* @param[in] ntp the thread to be switched in
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* @param[in] otp the thread to be switched out
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*/
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#if !defined(__DOXYGEN__)
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__attribute__((naked))
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#endif
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void port_switch(Thread *ntp, Thread *otp) {
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register struct intctx *sp_thd asm ("sp");
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PUSH_CONTEXT(sp_thd);
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otp->p_ctx.r13 = sp_thd;
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sp_thd = ntp->p_ctx.r13;
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POP_CONTEXT(sp_thd);
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}
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/**
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* @brief Start a thread by invoking its work function.
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* @details If the work function returns @p chThdExit() is automatically
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* invoked.
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*/
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void _port_thread_start(void) {
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asm volatile ("cpsie i \n\t" \
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"mov r0, r5 \n\t" \
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"blx r4 \n\t" \
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"bl chThdExit");
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}
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/** @} */
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