359 lines
12 KiB
C
359 lines
12 KiB
C
/*
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ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio.
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This file is part of ChibiOS/RT.
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ChibiOS/RT is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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ChibiOS/RT is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/**
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* @file ARMCM3/chcore.h
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* @brief ARM Cortex-M3 architecture port macros and structures.
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*
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* @addtogroup ARMCM3_CORE
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* @{
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*/
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#ifndef _CHCORE_H_
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#define _CHCORE_H_
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/*
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* Port-related configuration parameters.
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*/
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/**
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* @brief Enables the use of the WFI ins.
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*/
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#ifndef ENABLE_WFI_IDLE
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#define ENABLE_WFI_IDLE 0
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#endif
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/**
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* @brief Name of the implemented architecture.
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*/
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#define CH_ARCHITECTURE_NAME "ARM"
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/* Inclusion of the Cortex-M3 implementation specific parameters.*/
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#include "cmparams.h"
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/* Generating model-dependent info.*/
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#if (CORTEX_MODEL == CORTEX_M3) || defined(__DOXYGEN__)
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/**
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* @brief Macro defining the ARM Cortex-M3 architecture.
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*/
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#define CH_ARCHITECTURE_ARMCM3
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/**
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* @brief Name of the architecture variant (optional).
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*/
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#define CH_CORE_VARIANT_NAME "Cortex-M3"
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#else
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#error "this ports only supports the Cortex-M3 architecture"
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#endif
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/**
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* @brief 32 bits stack and memory alignment enforcement.
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*/
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typedef uint32_t stkalign_t;
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/**
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* @brief Generic ARM register.
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*/
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typedef void *regarm_t;
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#if !defined(__DOXYGEN__)
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/**
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* @brief Interrupt saved context.
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* @details This structure represents the stack frame saved during a
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* preemption-capable interrupt handler.
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* @note This structure is empty in this port.
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*/
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struct extctx {
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};
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#endif
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#if !defined(__DOXYGEN__)
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/**
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* @brief System saved context.
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* @details This structure represents the inner stack frame during a context
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* switching.
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*/
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struct intctx {
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regarm_t basepri;
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regarm_t r4;
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regarm_t r5;
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regarm_t r6;
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#ifndef CH_CURRP_REGISTER_CACHE
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regarm_t r7;
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#endif
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regarm_t r8;
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regarm_t r9;
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regarm_t r10;
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regarm_t r11;
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regarm_t lr_exc;
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/* Start of the hardware saved frame.*/
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regarm_t r0;
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regarm_t r1;
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regarm_t r2;
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regarm_t r3;
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regarm_t r12;
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regarm_t lr_thd;
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regarm_t pc;
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regarm_t xpsr;
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};
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#endif
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#if !defined(__DOXYGEN__)
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/**
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* @brief Platform dependent part of the @p Thread structure.
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* @details In the Cortex-M3 port this structure just holds a pointer to the
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* @p intctx structure representing the stack pointer at the time
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* of the context switch.
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*/
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struct context {
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struct intctx *r13;
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};
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#endif
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/**
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* @brief Platform dependent part of the @p chThdInit() API.
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* @details This code usually setup the context switching frame represented
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* by an @p intctx structure.
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*/
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#define SETUP_CONTEXT(workspace, wsize, pf, arg) { \
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tp->p_ctx.r13 = (struct intctx *)((uint8_t *)workspace + \
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wsize - \
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sizeof(struct intctx)); \
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tp->p_ctx.r13->basepri = CORTEX_BASEPRI_USER; \
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tp->p_ctx.r13->lr_exc = (regarm_t)0xFFFFFFFD; \
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tp->p_ctx.r13->r0 = arg; \
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tp->p_ctx.r13->lr_thd = chThdExit; \
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tp->p_ctx.r13->pc = pf; \
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tp->p_ctx.r13->xpsr = (regarm_t)0x01000000; \
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}
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/**
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* @brief Stack size for the system idle thread.
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* @details This size depends on the idle thread implementation, usually
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* the idle thread should take no more space than those reserved
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* by @p INT_REQUIRED_STACK.
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* @note In this port it is set to 4 because the idle thread does have
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* a stack frame when compiling without optimizations.
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*/
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#ifndef IDLE_THREAD_STACK_SIZE
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#define IDLE_THREAD_STACK_SIZE 4
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#endif
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/**
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* @brief Per-thread stack overhead for interrupts servicing.
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* @details This constant is used in the calculation of the correct working
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* area size.
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* This value can be zero on those architecture where there is a
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* separate interrupt stack and the stack space between @p intctx and
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* @p extctx is known to be zero.
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* @note This port requires no extra stack space for interrupt handling.
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*/
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#ifndef INT_REQUIRED_STACK
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#define INT_REQUIRED_STACK 0
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#endif
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/**
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* @brief Enforces a correct alignment for a stack area size value.
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*/
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#define STACK_ALIGN(n) ((((n) - 1) | (sizeof(stkalign_t) - 1)) + 1)
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/**
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* @brief Computes the thread working area global size.
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*/
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#define THD_WA_SIZE(n) STACK_ALIGN(sizeof(Thread) + \
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sizeof(struct intctx) + \
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sizeof(struct extctx) + \
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(n) + (INT_REQUIRED_STACK))
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/**
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* @brief Static working area allocation.
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* @details This macro is used to allocate a static thread working area
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* aligned as both position and size.
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*/
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#define WORKING_AREA(s, n) stkalign_t s[THD_WA_SIZE(n) / sizeof(stkalign_t)];
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/**
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* @brief IRQ prologue code.
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* @details This macro must be inserted at the start of all IRQ handlers
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* enabled to invoke system APIs.
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*/
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#define PORT_IRQ_PROLOGUE()
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/**
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* @brief IRQ epilogue code.
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* @details This macro must be inserted at the end of all IRQ handlers
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* enabled to invoke system APIs.
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*/
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#define PORT_IRQ_EPILOGUE() { \
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chSysLockFromIsr(); \
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if (chSchIsRescRequiredI()) \
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SCB_ICSR = ICSR_PENDSVSET; \
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chSysUnlockFromIsr(); \
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}
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/**
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* @brief IRQ handler function declaration.
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* @note @p id can be a function name or a vector number depending on the
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* port implementation.
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*/
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#define PORT_IRQ_HANDLER(id) void id(void)
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/**
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* @brief Port-related initialization code.
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* @note This function is empty in this port.
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*/
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#define port_init()
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/**
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* @brief Kernel-lock action.
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* @details Usually this function just disables interrupts but may perform
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* more actions.
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* @note In this port this it raises the base priority to kernel level.
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*/
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#if CH_OPTIMIZE_SPEED
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#define port_lock() { \
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register uint32_t tmp asm ("r3") = CORTEX_BASEPRI_KERNEL; \
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asm volatile ("msr BASEPRI, %0" : : "r" (tmp)); \
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}
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#else
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#define port_lock() { \
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asm volatile ("bl _port_lock" : : : "r3", "lr"); \
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}
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#endif
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/**
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* @brief Kernel-unlock action.
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* @details Usually this function just disables interrupts but may perform
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* more actions.
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* @note In this port this it lowers the base priority to kernel level.
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*/
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#if CH_OPTIMIZE_SPEED
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#define port_unlock() { \
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register uint32_t tmp asm ("r3") = CORTEX_BASEPRI_USER; \
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asm volatile ("msr BASEPRI, %0" : : "r" (tmp)); \
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}
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#else
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#define port_unlock() { \
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asm volatile ("bl _port_unlock" : : : "r3", "lr"); \
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}
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#endif
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/**
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* @brief Kernel-lock action from an interrupt handler.
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* @details This function is invoked before invoking I-class APIs from
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* interrupt handlers. The implementation is architecture dependent,
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* in its simplest form it is void.
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* @note Same as @p port_lock() in this port.
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*/
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#define port_lock_from_isr() port_lock()
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/**
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* @brief Kernel-unlock action from an interrupt handler.
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* @details This function is invoked after invoking I-class APIs from interrupt
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* handlers. The implementation is architecture dependent, in its
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* simplest form it is void.
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* @note Same as @p port_unlock() in this port.
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*/
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#define port_unlock_from_isr() port_unlock()
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/**
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* @brief Disables all the interrupt sources.
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* @note Of course non maskable interrupt sources are not included.
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* @note In this port it disables all the interrupt sources by raising
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* the priority mask to level 0.
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*/
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#define port_disable() asm volatile ("cpsid i")
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/**
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* @brief Disables the interrupt sources below kernel-level priority.
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* @note Interrupt sources above kernel level remains enabled.
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* @note In this port it raises/lowers the base priority to kernel level.
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*/
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#define port_suspend() { \
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register uint32_t tmp asm ("r3") = CORTEX_BASEPRI_KERNEL; \
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asm volatile ("msr BASEPRI, %0 \n\t" \
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"cpsie i" : : "r" (tmp)); \
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}
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/**
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* @brief Enables all the interrupt sources.
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* @note In this port it lowers the base priority to user level.
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*/
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#define port_enable() { \
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register uint32_t tmp asm ("r3") = CORTEX_BASEPRI_USER; \
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asm volatile ("msr BASEPRI, %0 \n\t" \
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"cpsie i" : : "r" (tmp)); \
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}
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/**
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* @brief Enters an architecture-dependent IRQ-waiting mode.
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* @details The function is meant to return when an interrupt becomes pending.
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* The simplest implementation is an empty function or macro but this
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* would not take advantage of architecture-specific power saving
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* modes.
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* @note Implemented as an inlined @p WFI instruction.
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*/
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#if ENABLE_WFI_IDLE || defined(__DOXYGEN__)
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#define port_wait_for_interrupt() { \
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asm volatile ("wfi"); \
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}
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#else
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#define port_wait_for_interrupt()
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#endif
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/**
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* @brief Performs a context switch between two threads.
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* @details This is the most critical code in any port, this function
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* is responsible for the context switch between 2 threads.
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* @note The implementation of this code affects <b>directly</b> the context
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* switch performance so optimize here as much as you can.
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* @note Implemented as inlined code for performance reasons.
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*
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* @param[in] ntp the thread to be switched in
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* @param[in] otp the thread to be switched out
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*/
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static INLINE Thread *port_switch(Thread *ntp, Thread *otp) {
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register Thread *_ntp asm ("r0") = (ntp);
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register Thread *_otp asm ("r1") = (otp);
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#if CH_DBG_ENABLE_STACK_CHECK
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register char *sp asm ("sp");
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if (sp - sizeof(struct intctx) - sizeof(Thread) < (char *)_otp)
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asm volatile ("movs r0, #0 \n\t"
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"b chDbgPanic");
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#endif /* CH_DBG_ENABLE_STACK_CHECK */
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asm volatile ("svc #0" : : "r" (_otp), "r" (_ntp) : "memory");
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return _otp;
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}
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#ifdef __cplusplus
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extern "C" {
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#endif
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void port_halt(void);
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#if !CH_OPTIMIZE_SPEED
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void _port_lock(void);
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void _port_unlock(void);
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#endif
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#ifdef __cplusplus
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}
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#endif
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#endif /* _CHCORE_H_ */
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/** @} */
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