215 lines
6.9 KiB
C
215 lines
6.9 KiB
C
/*
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ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
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2011,2012 Giovanni Di Sirio.
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This file is part of ChibiOS/RT.
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ChibiOS/RT is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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ChibiOS/RT is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/**
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* @file templates/hal_lld.h
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* @brief HAL subsystem low level driver header template.
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*
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* @addtogroup HAL
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* @{
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*/
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#ifndef _HAL_LLD_H_
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#define _HAL_LLD_H_
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#include "sam4l.h"
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/*===========================================================================*/
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/* Driver constants. */
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/*===========================================================================*/
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/**
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* @brief Defines the support for realtime counters in the HAL.
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*/
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#define HAL_IMPLEMENTS_COUNTERS TRUE
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/**
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* @brief Platform name.
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*/
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#define PLATFORM_NAME "SAM4L Series"
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/**
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* @name MCCTRL register bits definitions
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* @{
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*/
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#define SAM_MCSEL_MASK (7 << 0) /**< MCSEL bits mask. */
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#define SAM_MCSEL_RCSYS (0 << 0) /**< System RC oscillator. */
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#define SAM_MCSEL_OSC0 (1 << 0) /**< Oscillator 0. */
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#define SAM_MCSEL_PLL (2 << 0) /**< PLL. */
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#define SAM_MCSEL_DFLL (3 << 0) /**< DFLL. */
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#define SAM_MCSEL_RC80M (4 << 0) /**< 80 MHz RC oscillator. */
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#define SAM_MCSEL_RCFAST (5 << 0) /**< 4/8/12 MHz RC oscillator. */
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#define SAM_MCSEL_RC1M (6 << 0) /**< 1 MHz RC oscillator. */
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/** @} */
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/**
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* @name CPUSEL register bits definitions
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* @{
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*/
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#define SAM_CPUSEL_MASK (7 << 0) /**< CPUSEL bits mask. */
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#define SAM_CPUSEL_DIV1 0
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#define SAM_CPUSEL_DIV2 (SAM_CPUDIV | 0)
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#define SAM_CPUSEL_DIV4 (SAM_CPUDIV | 1)
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#define SAM_CPUSEL_DIV8 (SAM_CPUDIV | 2)
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#define SAM_CPUSEL_DIV16 (SAM_CPUDIV | 3)
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#define SAM_CPUSEL_DIV32 (SAM_CPUDIV | 4)
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#define SAM_CPUSEL_DIV64 (SAM_CPUDIV | 5)
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#define SAM_CPUSEL_DIV128 (SAM_CPUDIV | 6)
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#define SAM_CPUSEL_DIV256 (SAM_CPUDIV | 7)
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#define SAM_CPUDIV (1 << 7) /**< CPUDIV bit. */
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/**
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* @name PBx registers bits definitions
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* @{
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*/
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#define SAM_PBSEL_MASK (7 << 0) /**< PBSEL bits mask. */
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#define SAM_PBSEL_DIV1 0
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#define SAM_PBSEL_DIV2 (SAM_CPUDIV | 0)
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#define SAM_PBSEL_DIV4 (SAM_CPUDIV | 1)
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#define SAM_PBSEL_DIV8 (SAM_CPUDIV | 2)
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#define SAM_PBSEL_DIV16 (SAM_CPUDIV | 3)
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#define SAM_PBSEL_DIV32 (SAM_CPUDIV | 4)
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#define SAM_PBSEL_DIV64 (SAM_CPUDIV | 5)
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#define SAM_PBSEL_DIV128 (SAM_CPUDIV | 6)
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#define SAM_PBSEL_DIV256 (SAM_CPUDIV | 7)
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#define SAM_PBDIV (1 << 7) /**< PBDIV bit. */
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/** @} */
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/*===========================================================================*/
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/* Driver pre-compile time settings. */
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/*===========================================================================*/
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/**
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* @name Configuration options
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* @{
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*/
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/**
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* @brief Disables the clock initialization in the HAL.
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*/
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#if !defined(SAM_NO_INIT) || defined(__DOXYGEN__)
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#define SAM_NO_INIT FALSE
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#endif
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/**
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* @brief MCCTRL register settings.
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*/
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#if !defined(SAM_MCCTRL_MCSEL) || defined(__DOXYGEN__)
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#define SAM_MCCTRL_MCSEL SAM_MCSEL_PLL
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#endif
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/**
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* @brief CPUSEL register settings.
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*/
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#if !defined(SAM_CPUSEL) || defined(__DOXYGEN__)
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#define SAM_CPUSEL SAM_CPUSEL_DIV1
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#endif
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/**
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* @brief PBASEL register settings.
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*/
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#if !defined(SAM_PBASEL) || defined(__DOXYGEN__)
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#define SAM_PBASEL SAM_PBSEL_DIV1
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#endif
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/**
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* @brief PBBSEL register settings.
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*/
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#if !defined(SAM_PBBSEL) || defined(__DOXYGEN__)
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#define SAM_PBBSEL SAM_PBSEL_DIV1
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#endif
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/**
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* @brief PBCSEL register settings.
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*/
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#if !defined(SAM_PBCSEL) || defined(__DOXYGEN__)
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#define SAM_PBCSEL SAM_PBSEL_DIV1
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#endif
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/**
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* @brief PBDSEL register settings.
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*/
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#if !defined(SAM_PBDSEL) || defined(__DOXYGEN__)
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#define SAM_PBDSEL SAM_PBSEL_DIV1
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#endif
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/** @} */
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/*===========================================================================*/
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/* Derived constants and error checks. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver data structures and types. */
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/*===========================================================================*/
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/**
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* @brief Type representing a system clock frequency.
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*/
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typedef uint32_t halclock_t;
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/**
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* @brief Type of the realtime free counter value.
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*/
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typedef uint32_t halrtcnt_t;
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/*===========================================================================*/
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/* Driver macros. */
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/*===========================================================================*/
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/**
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* @brief Returns the current value of the system free running counter.
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* @note This service is implemented by returning the content of the
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* DWT_CYCCNT register.
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*
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* @return The value of the system free running counter of
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* type halrtcnt_t.
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*
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* @notapi
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*/
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#define hal_lld_get_counter_value() DWT_CYCCNT
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/**
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* @brief Realtime counter frequency.
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* @note The DWT_CYCCNT register is incremented directly by the system
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* clock so this function returns STM32_HCLK.
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*
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* @return The realtime counter frequency of type halclock_t.
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*
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* @notapi
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*/
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#define hal_lld_get_counter_frequency() STM32_HCLK
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/*===========================================================================*/
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/* External declarations. */
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/*===========================================================================*/
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#ifdef __cplusplus
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extern "C" {
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#endif
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void sam4l_clock_init(void);
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void hal_lld_init(void);
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#ifdef __cplusplus
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}
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#endif
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#endif /* _HAL_LLD_H_ */
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/** @} */
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