146 lines
5.0 KiB
C
146 lines
5.0 KiB
C
/*
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ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio.
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This file is part of ChibiOS/RT.
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ChibiOS/RT is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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ChibiOS/RT is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/**
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* @file AT91SAM7/hal_lld.c
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* @brief AT91SAM7 HAL subsystem low level driver source.
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*
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* @addtogroup AT91SAM7_HAL
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* @{
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*/
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#include "ch.h"
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#include "hal.h"
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/*===========================================================================*/
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/* Driver exported variables. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver local variables. */
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/*===========================================================================*/
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/**
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* @brief PAL setup.
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* @details Digital I/O ports static configuration as defined in @p board.h.
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*/
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const PALConfig pal_default_config =
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{
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{VAL_PIOA_ODSR, VAL_PIOA_OSR, VAL_PIOA_PUSR},
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#if (SAM7_PLATFORM == SAM7X128) || (SAM7_PLATFORM == SAM7X256) || \
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(SAM7_PLATFORM == SAM7X512)
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{VAL_PIOB_ODSR, VAL_PIOB_OSR, VAL_PIOB_PUSR}
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#endif
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};
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/*===========================================================================*/
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/* Driver local functions. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver interrupt handlers. */
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/*===========================================================================*/
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static CH_IRQ_HANDLER(spurious_handler) {
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CH_IRQ_PROLOGUE();
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AT91SAM7_SPURIOUS_HANDLER_HOOK();
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AT91C_BASE_AIC->AIC_EOICR = 0;
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CH_IRQ_EPILOGUE();
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}
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/*===========================================================================*/
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/* Driver exported functions. */
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/*===========================================================================*/
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/**
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* @brief Low level HAL driver initialization.
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*
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* @notapi
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*/
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void hal_lld_init(void) {
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unsigned i;
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/* FIQ Handler weak symbol defined in vectors.s.*/
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void FiqHandler(void);
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/* Default AIC setup, the device drivers will modify it as needed.*/
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AT91C_BASE_AIC->AIC_ICCR = 0xFFFFFFFF;
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AT91C_BASE_AIC->AIC_IDCR = 0xFFFFFFFF;
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AT91C_BASE_AIC->AIC_SVR[0] = (AT91_REG)FiqHandler;
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for (i = 1; i < 31; i++) {
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AT91C_BASE_AIC->AIC_SVR[i] = (AT91_REG)NULL;
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AT91C_BASE_AIC->AIC_EOICR = (AT91_REG)i;
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}
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AT91C_BASE_AIC->AIC_SPU = (AT91_REG)spurious_handler;
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}
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/**
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* @brief AT91SAM7 clocks and PLL initialization.
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* @note All the involved constants come from the file @p board.h.
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* @note This function must be invoked only after the system reset.
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*
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* @special
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*/
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void at91sam7_clock_init(void) {
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/* wait for reset */
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while((AT91C_BASE_RSTC->RSTC_RSR & (AT91C_RSTC_SRCMP | AT91C_RSTC_NRSTL)) != AT91C_RSTC_NRSTL)
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;
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/* enable reset */
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AT91C_BASE_RSTC->RSTC_RMR = ((0xA5 << 24) | AT91C_RSTC_URSTEN);
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/* Flash Memory: 1 wait state, about 50 cycles in a microsecond.*/
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#if SAM7_PLATFORM == SAM7X512
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AT91C_BASE_MC->MC0_FMR = (AT91C_MC_FMCN & (50 << 16)) | AT91C_MC_FWS_1FWS;
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AT91C_BASE_MC->MC1_FMR = (AT91C_MC_FMCN & (50 << 16)) | AT91C_MC_FWS_1FWS;
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#else
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AT91C_BASE_MC->MC_FMR = (AT91C_MC_FMCN & (50 << 16)) | AT91C_MC_FWS_1FWS;
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#endif
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/* Enables the main oscillator and waits 56 slow cycles as startup time.*/
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AT91C_BASE_PMC->PMC_MOR = (AT91C_CKGR_OSCOUNT & (7 << 8)) | AT91C_CKGR_MOSCEN;
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while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MOSCS))
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;
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/* PLL setup: DIV = 14, MUL = 72, PLLCOUNT = 10
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PLLfreq = 96109714 Hz (rounded).*/
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AT91C_BASE_PMC->PMC_PLLR = (AT91C_CKGR_DIV & 14) |
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(AT91C_CKGR_PLLCOUNT & (10 << 8)) |
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(AT91SAM7_USBDIV) |
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(AT91C_CKGR_MUL & (72 << 16));
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while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_LOCK))
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;
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/* Master clock = PLLfreq / 2 = 48054858 Hz (rounded).*/
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AT91C_BASE_PMC->PMC_MCKR = AT91C_PMC_PRES_CLK_2;
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while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY))
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;
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AT91C_BASE_PMC->PMC_MCKR |= AT91C_PMC_CSS_PLL_CLK;
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while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY))
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;
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}
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/** @} */
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