303 lines
8.3 KiB
C
303 lines
8.3 KiB
C
/*
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ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio.
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This file is part of ChibiOS/RT.
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ChibiOS/RT is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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ChibiOS/RT is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/**
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* @file ports/ARMCM3/chcore.h
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* @brief ARM Cortex-M3 architecture port macros and structures.
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* @addtogroup ARMCM3_CORE
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* @{
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*/
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#ifndef _CHCORE_H_
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#define _CHCORE_H_
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/*
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* Port-related configuration parameters.
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*/
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/**
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* Enables the use of the WFI ins.
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*/
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#ifndef ENABLE_WFI_IDLE
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#define ENABLE_WFI_IDLE 0
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#endif
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/**
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* BASEPRI user level, 0 = disabled.
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*/
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#ifndef BASEPRI_USER
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#define BASEPRI_USER 0
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#endif
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/**
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* BASEPRI level within kernel lock.
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* Priority levels higher than this one (lower values) are unaffected by
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* the OS activity and can be classified as fast interrupt sources, see
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* @ref interrupt_classes.
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*/
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#ifndef BASEPRI_KERNEL
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#define BASEPRI_KERNEL 0x40
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#endif
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/**
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* SVCALL handler priority.
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* @note This priority must always be one level above the @p BASEPRI_KERNEL
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* value.
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* @note It is recommended to leave this priority level for this handler alone.
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*/
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#ifndef PRIORITY_SVCALL
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#define PRIORITY_SVCALL (BASEPRI_KERNEL - 0x10)
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#endif
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/**
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* SYSTICK handler priority.
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*/
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#ifndef PRIORITY_SYSTICK
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#define PRIORITY_SYSTICK 0x80
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#endif
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/**
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* PENDSV handler priority.
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* @note It is recommended to leave this priority level for this handler alone.
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* @note This is a reserved handler and its priority must always be the
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* lowest priority in the system in order to be always executed last
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* in the interrupt servicing chain.
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*/
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#ifndef PRIORITY_PENDSV
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#define PRIORITY_PENDSV 0xF0
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#endif
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/**
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* Macro defining the ARM Cortex-M3 architecture.
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*/
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#define CH_ARCHITECTURE_ARMCM3
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/**
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* 32 bit stack alignment.
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*/
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typedef uint32_t stkalign_t;
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/**
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* Generic ARM register.
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*/
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typedef void *regarm_t;
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/** @cond never */
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/**
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* Interrupt saved context, empty in this architecture.
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*/
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struct extctx {
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};
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/** @endcond */
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/** @cond never */
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/**
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* This structure represents the inner stack frame during a context switching.
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*/
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struct intctx {
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regarm_t basepri;
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regarm_t r4;
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regarm_t r5;
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regarm_t r6;
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#ifndef CH_CURRP_REGISTER_CACHE
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regarm_t r7;
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#endif
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regarm_t r8;
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regarm_t r9;
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regarm_t r10;
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regarm_t r11;
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regarm_t lr_exc;
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regarm_t r0;
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regarm_t r1;
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regarm_t r2;
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regarm_t r3;
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regarm_t r12;
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regarm_t lr_thd;
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regarm_t pc;
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regarm_t xpsr;
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};
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/** @endcond */
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/** @cond never */
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/**
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* Cortex-M3 context structure.
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*/
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struct context {
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struct intctx *r13;
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};
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/** @endcond */
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/**
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* Platform dependent part of the @p chThdInit() API.
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* This code usually setup the context switching frame represented by a
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* @p intctx structure.
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*/
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#define SETUP_CONTEXT(workspace, wsize, pf, arg) { \
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tp->p_ctx.r13 = (struct intctx *)((uint8_t *)workspace + \
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wsize - \
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sizeof(struct intctx)); \
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tp->p_ctx.r13->basepri = BASEPRI_USER; \
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tp->p_ctx.r13->lr_exc = (regarm_t)0xFFFFFFFD; \
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tp->p_ctx.r13->r0 = arg; \
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tp->p_ctx.r13->r1 = pf; \
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tp->p_ctx.r13->pc = threadstart; \
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tp->p_ctx.r13->xpsr = (regarm_t)0x01000000; \
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}
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/**
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* The default idle thread implementation requires no extra stack space in
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* this port.
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*/
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#ifndef IDLE_THREAD_STACK_SIZE
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#define IDLE_THREAD_STACK_SIZE 0
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#endif
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/**
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* This port requires no extra stack space for interrupt handling.
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*/
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#ifndef INT_REQUIRED_STACK
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#define INT_REQUIRED_STACK 0
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#endif
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/**
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* Enforces a correct alignment for a stack area size value.
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*/
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#define STACK_ALIGN(n) ((((n) - 1) | sizeof(stkalign_t)) + 1)
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/**
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* Computes the thread working area global size.
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*/
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#define THD_WA_SIZE(n) STACK_ALIGN(sizeof(Thread) + \
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sizeof(struct intctx) + \
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sizeof(struct extctx) + \
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(n) + (INT_REQUIRED_STACK))
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/**
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* Macro used to allocate a thread working area aligned as both position and
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* size.
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*/
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#define WORKING_AREA(s, n) stkalign_t s[THD_WA_SIZE(n) / sizeof(stkalign_t)];
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/**
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* IRQ prologue code, inserted at the start of all IRQ handlers enabled to
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* invoke system APIs.
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*/
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#define PORT_IRQ_PROLOGUE()
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/**
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* IRQ epilogue code, inserted at the end of all IRQ handlers enabled to
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* invoke system APIs.
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*/
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#define PORT_IRQ_EPILOGUE() { \
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SCB_ICSR = ICSR_PENDSVSET; \
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}
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/**
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* IRQ handler function declaration.
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*/
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#define PORT_IRQ_HANDLER(id) void id(void)
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/**
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* This function is empty in this port.
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*/
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#define port_init()
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/**
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* Raises the base priority to kernel level.
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*/
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#define port_lock() { \
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register uint32_t tmp asm ("r3") = BASEPRI_KERNEL; \
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asm volatile ("msr BASEPRI, %0" : : "r" (tmp)); \
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}
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/**
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* Lowers the base priority to user level.
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*/
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#define port_unlock() { \
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register uint32_t tmp asm ("r3") = BASEPRI_USER; \
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asm volatile ("msr BASEPRI, %0" : : "r" (tmp)); \
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}
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/**
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* Same as @p port_lock() in this port.
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*/
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#define port_lock_from_isr() port_lock()
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/**
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* Same as @p port_unlock() in this port.
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*/
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#define port_unlock_from_isr() port_unlock()
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/**
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* Disables all the interrupt sources by raising the priority mask to level 0.
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*/
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#define port_disable() asm volatile ("cpsid i")
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/**
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* Raises/lowers the base priority to kernel level.
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*/
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#define port_suspend() { \
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register uint32_t tmp asm ("r3") = BASEPRI_KERNEL; \
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asm volatile ("msr BASEPRI, %0 \n\t" \
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"cpsie i" : : "r" (tmp)); \
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}
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/**
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* Lowers the base priority to user level.
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*/
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#define port_enable() { \
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register uint32_t tmp asm ("r3") = BASEPRI_USER; \
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asm volatile ("msr BASEPRI, %0 \n\t" \
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"cpsie i" : : "r" (tmp)); \
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}
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/**
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* This port function is implemented as inlined code for performance reasons.
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*/
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#if ENABLE_WFI_IDLE || defined(__DOXYGEN__)
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#define port_wait_for_interrupt() { \
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asm volatile ("wfi"); \
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}
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#else
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#define port_wait_for_interrupt()
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#endif
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/**
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* This port function is implemented as inlined code for performance reasons.
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*/
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#define port_switch(otp, ntp) { \
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register Thread *_otp asm ("r0") = (otp); \
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register Thread *_ntp asm ("r1") = (ntp); \
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asm volatile ("svc #0" : : "r" (_otp), "r" (_ntp)); \
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}
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#ifdef __cplusplus
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extern "C" {
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#endif
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void port_puts(char *msg);
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void port_halt(void);
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void threadstart(void);
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#ifdef __cplusplus
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}
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#endif
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#endif /* _CHCORE_H_ */
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/** @} */
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