465 lines
21 KiB
C
465 lines
21 KiB
C
/*
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ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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/**
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* @file STM32F7xx/stm32_registry.h
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* @brief STM32F7xx capabilities registry.
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*
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* @addtogroup HAL
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* @{
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*/
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#ifndef _STM32_REGISTRY_H_
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#define _STM32_REGISTRY_H_
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/*===========================================================================*/
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/* Platform capabilities. */
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/*===========================================================================*/
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/**
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* @name STM32F7xx capabilities
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* @{
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*/
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/*===========================================================================*/
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/* STM32F745xx, STM32F746xx, STM32F756xx. */
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/*===========================================================================*/
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#if defined(STM32F745xx) || defined(STM32F746xx) || defined(STM32F756xx) || \
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defined(__DOXYGEN__)
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/* ADC attributes.*/
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#define STM32_HAS_ADC1 TRUE
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#define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\
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STM32_DMA_STREAM_ID_MSK(2, 4))
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#define STM32_ADC1_DMA_CHN 0x00000000
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#define STM32_HAS_ADC2 TRUE
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#define STM32_ADC2_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 2) |\
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STM32_DMA_STREAM_ID_MSK(2, 3))
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#define STM32_ADC2_DMA_CHN 0x00001100
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#define STM32_HAS_ADC3 TRUE
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#define STM32_ADC3_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\
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STM32_DMA_STREAM_ID_MSK(2, 1))
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#define STM32_ADC3_DMA_CHN 0x00000022
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#define STM32_HAS_ADC4 FALSE
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#define STM32_HAS_SDADC1 FALSE
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#define STM32_HAS_SDADC2 FALSE
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#define STM32_HAS_SDADC3 FALSE
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/* CAN attributes.*/
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#define STM32_CAN_MAX_FILTERS 28
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#define STM32_HAS_CAN1 TRUE
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#define STM32_CAN1_TX_HANDLER Vector8C
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#define STM32_CAN1_RX0_HANDLER Vector90
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#define STM32_CAN1_RX1_HANDLER Vector94
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#define STM32_CAN1_SCE_HANDLER Vector98
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#define STM32_CAN1_TX_NUMBER 19
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#define STM32_CAN1_RX0_NUMBER 20
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#define STM32_CAN1_RX1_NUMBER 21
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#define STM32_CAN1_SCE_NUMBER 22
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#define STM32_HAS_CAN2 TRUE
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#define STM32_CAN2_TX_HANDLER Vector13C
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#define STM32_CAN2_RX0_HANDLER Vector140
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#define STM32_CAN2_RX1_HANDLER Vector144
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#define STM32_CAN2_SCE_HANDLER Vector148
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#define STM32_CAN2_TX_NUMBER 63
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#define STM32_CAN2_RX0_NUMBER 64
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#define STM32_CAN2_RX1_NUMBER 65
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#define STM32_CAN2_SCE_NUMBER 66
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/* DAC attributes.*/
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#define STM32_HAS_DAC1_CH1 TRUE
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#define STM32_DAC1_CH1_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5)
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#define STM32_DAC1_CH1_DMA_CHN 0x00070000
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#define STM32_HAS_DAC1_CH2 TRUE
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#define STM32_DAC1_CH2_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 6)
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#define STM32_DAC1_CH2_DMA_CHN 0x00700000
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#define STM32_HAS_DAC2_CH1 FALSE
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#define STM32_HAS_DAC2_CH2 FALSE
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/* DMA attributes.*/
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#define STM32_ADVANCED_DMA TRUE
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#define STM32_HAS_DMA1 TRUE
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#define STM32_HAS_DMA2 TRUE
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/* ETH attributes.*/
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#define STM32_HAS_ETH TRUE
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#define STM32_ETH_HANDLER Vector134
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#define STM32_ETH_NUMBER 61
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/* EXTI attributes.*/
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#define STM32_EXTI_NUM_CHANNELS 23
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/* GPIO attributes.*/
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#define STM32_HAS_GPIOA TRUE
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#define STM32_HAS_GPIOB TRUE
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#define STM32_HAS_GPIOC TRUE
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#define STM32_HAS_GPIOD TRUE
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#define STM32_HAS_GPIOE TRUE
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#define STM32_HAS_GPIOH TRUE
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#define STM32_HAS_GPIOF TRUE
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#define STM32_HAS_GPIOG TRUE
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#define STM32_HAS_GPIOI TRUE
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#define STM32_HAS_GPIOJ TRUE
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#define STM32_HAS_GPIOK TRUE
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#define STM32_GPIO_EN_MASK (RCC_AHB1ENR_GPIOAEN | \
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RCC_AHB1ENR_GPIOBEN | \
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RCC_AHB1ENR_GPIOCEN | \
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RCC_AHB1ENR_GPIODEN | \
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RCC_AHB1ENR_GPIOEEN | \
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RCC_AHB1ENR_GPIOFEN | \
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RCC_AHB1ENR_GPIOGEN | \
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RCC_AHB1ENR_GPIOHEN | \
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RCC_AHB1ENR_GPIOIEN | \
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RCC_AHB1ENR_GPIOJEN | \
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RCC_AHB1ENR_GPIOKEN)
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/* I2C attributes.*/
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#define STM32_HAS_I2C1 TRUE
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#define STM32_I2C1_EVENT_HANDLER VectorBC
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#define STM32_I2C1_ERROR_HANDLER VectorC0
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#define STM32_I2C1_EVENT_NUMBER 31
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#define STM32_I2C1_ERROR_NUMBER 32
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#define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 0) |\
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STM32_DMA_STREAM_ID_MSK(1, 5))
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#define STM32_I2C1_RX_DMA_CHN 0x00100001
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#define STM32_I2C1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7) |\
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STM32_DMA_STREAM_ID_MSK(1, 6))
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#define STM32_I2C1_TX_DMA_CHN 0x11000000
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#define STM32_HAS_I2C2 TRUE
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#define STM32_I2C2_EVENT_HANDLER VectorC4
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#define STM32_I2C2_ERROR_HANDLER VectorC8
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#define STM32_I2C2_EVENT_NUMBER 33
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#define STM32_I2C2_ERROR_NUMBER 34
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#define STM32_I2C2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
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STM32_DMA_STREAM_ID_MSK(1, 3))
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#define STM32_I2C2_RX_DMA_CHN 0x00007700
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#define STM32_I2C2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 7)
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#define STM32_I2C2_TX_DMA_CHN 0x70000000
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#define STM32_HAS_I2C3 TRUE
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#define STM32_I2C3_EVENT_HANDLER Vector160
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#define STM32_I2C3_ERROR_HANDLER Vector164
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#define STM32_I2C3_EVENT_NUMBER 72
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#define STM32_I2C3_ERROR_NUMBER 73
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#define STM32_I2C3_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2)
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#define STM32_I2C3_RX_DMA_CHN 0x00000300
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#define STM32_I2C3_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
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#define STM32_I2C3_TX_DMA_CHN 0x00030000
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#define STM32_HAS_I2C4 TRUE
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#define STM32_I2C4_EVENT_HANDLER Vector1BC
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#define STM32_I2C4_ERROR_HANDLER Vector1C0
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#define STM32_I2C4_EVENT_NUMBER 95
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#define STM32_I2C4_ERROR_NUMBER 96
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#define STM32_I2C4_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2)
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#define STM32_I2C4_RX_DMA_CHN 0x00000200
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#define STM32_I2C4_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5)
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#define STM32_I2C4_TX_DMA_CHN 0x00200000
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/* RTC attributes.*/
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#define STM32_HAS_RTC TRUE
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#define STM32_RTC_HAS_SUBSECONDS TRUE
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#define STM32_RTC_HAS_PERIODIC_WAKEUPS TRUE
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#define STM32_RTC_NUM_ALARMS 2
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#define STM32_RTC_HAS_INTERRUPTS FALSE
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/* SDIO attributes.*/
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#define STM32_HAS_SDIO TRUE
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#define STM32_SDIO_HANDLER Vector104
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#define STM32_SDIO_NUMBER 49
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#define STM32_SDC_SDIO_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3) |\
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STM32_DMA_STREAM_ID_MSK(2, 6))
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#define STM32_SDC_SDIO_DMA_CHN 0x04004000
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/* SPI attributes.*/
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#define STM32_HAS_SPI1 TRUE
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#define STM32_SPI1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\
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STM32_DMA_STREAM_ID_MSK(2, 2))
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#define STM32_SPI1_RX_DMA_CHN 0x00000303
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#define STM32_SPI1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3) |\
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STM32_DMA_STREAM_ID_MSK(2, 5))
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#define STM32_SPI1_TX_DMA_CHN 0x00303000
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#define STM32_HAS_SPI2 TRUE
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#define STM32_SPI2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3)
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#define STM32_SPI2_RX_DMA_CHN 0x00000000
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#define STM32_SPI2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
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#define STM32_SPI2_TX_DMA_CHN 0x00000000
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#define STM32_HAS_SPI3 TRUE
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#define STM32_SPI3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 0) |\
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STM32_DMA_STREAM_ID_MSK(1, 2))
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#define STM32_SPI3_RX_DMA_CHN 0x00000000
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#define STM32_SPI3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5) |\
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STM32_DMA_STREAM_ID_MSK(1, 7))
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#define STM32_SPI3_TX_DMA_CHN 0x00000000
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#define STM32_HAS_SPI4 TRUE
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#define STM32_SPI4_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\
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STM32_DMA_STREAM_ID_MSK(2, 3))
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#define STM32_SPI4_RX_DMA_CHN 0x00005004
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#define STM32_SPI4_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 1) |\
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STM32_DMA_STREAM_ID_MSK(2, 4))
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#define STM32_SPI4_TX_DMA_CHN 0x00050040
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#define STM32_HAS_SPI5 TRUE
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#define STM32_SPI5_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3) | \
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STM32_DMA_STREAM_ID_MSK(2, 5))
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#define STM32_SPI5_RX_DMA_CHN 0x00702000
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#define STM32_SPI5_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 4) | \
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STM32_DMA_STREAM_ID_MSK(2, 6))
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#define STM32_SPI5_TX_DMA_CHN 0x07020000
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#define STM32_HAS_SPI6 TRUE
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#define STM32_SPI6_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 6))
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#define STM32_SPI6_RX_DMA_CHN 0x01000000
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#define STM32_SPI6_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 5))
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#define STM32_SPI6_TX_DMA_CHN 0x00100000
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/* TIM attributes.*/
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#define STM32_TIM_MAX_CHANNELS 4
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#define STM32_HAS_TIM1 TRUE
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#define STM32_TIM1_IS_32BITS FALSE
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#define STM32_TIM1_CHANNELS 4
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#define STM32_TIM1_UP_HANDLER VectorA4
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#define STM32_TIM1_CC_HANDLER VectorAC
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#define STM32_TIM1_UP_NUMBER 25
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#define STM32_TIM1_CC_NUMBER 27
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#define STM32_HAS_TIM2 TRUE
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#define STM32_TIM2_IS_32BITS TRUE
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#define STM32_TIM2_CHANNELS 4
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#define STM32_TIM2_HANDLER VectorB0
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#define STM32_TIM2_NUMBER 28
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#define STM32_HAS_TIM3 TRUE
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#define STM32_TIM3_IS_32BITS FALSE
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#define STM32_TIM3_CHANNELS 4
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#define STM32_TIM3_HANDLER VectorB4
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#define STM32_TIM3_NUMBER 29
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#define STM32_HAS_TIM4 TRUE
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#define STM32_TIM4_IS_32BITS FALSE
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#define STM32_TIM4_CHANNELS 4
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#define STM32_TIM4_HANDLER VectorB8
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#define STM32_TIM4_NUMBER 30
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#define STM32_HAS_TIM5 TRUE
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#define STM32_TIM5_IS_32BITS TRUE
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#define STM32_TIM5_CHANNELS 4
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#define STM32_TIM5_HANDLER Vector108
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#define STM32_TIM5_NUMBER 50
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#define STM32_HAS_TIM6 TRUE
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#define STM32_TIM6_IS_32BITS FALSE
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#define STM32_TIM6_CHANNELS 0
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#define STM32_TIM6_HANDLER Vector118
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#define STM32_TIM6_NUMBER 54
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#define STM32_HAS_TIM7 TRUE
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#define STM32_TIM7_IS_32BITS FALSE
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#define STM32_TIM7_CHANNELS 0
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#define STM32_TIM7_HANDLER Vector11C
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#define STM32_TIM7_NUMBER 55
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#define STM32_HAS_TIM8 TRUE
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#define STM32_TIM8_IS_32BITS FALSE
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#define STM32_TIM8_CHANNELS 6
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#define STM32_TIM8_UP_HANDLER VectorF0
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#define STM32_TIM8_CC_HANDLER VectorF8
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#define STM32_TIM8_UP_NUMBER 44
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#define STM32_TIM8_CC_NUMBER 46
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#define STM32_HAS_TIM9 TRUE
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#define STM32_TIM9_IS_32BITS FALSE
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#define STM32_TIM9_CHANNELS 2
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#define STM32_TIM9_HANDLER VectorA0
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#define STM32_TIM9_NUMBER 24
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#define STM32_HAS_TIM10 TRUE
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#define STM32_TIM10_IS_32BITS FALSE
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#define STM32_TIM10_CHANNELS 2
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#define STM32_TIM10_HANDLER VectorA4 /* Note: same as STM32_TIM1_UP */
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#define STM32_TIM10_NUMBER 25 /* Note: same as STM32_TIM1_UP */
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#define STM32_HAS_TIM11 TRUE
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#define STM32_TIM11_IS_32BITS FALSE
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#define STM32_TIM11_CHANNELS 2
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#define STM32_TIM11_HANDLER VectorA8
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#define STM32_TIM11_NUMBER 26
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#define STM32_HAS_TIM12 TRUE
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#define STM32_TIM12_IS_32BITS FALSE
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#define STM32_TIM12_CHANNELS 2
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#define STM32_TIM12_HANDLER VectorEC
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#define STM32_TIM12_NUMBER 43
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#define STM32_HAS_TIM13 TRUE
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#define STM32_TIM13_IS_32BITS FALSE
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#define STM32_TIM13_CHANNELS 2
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#define STM32_TIM13_HANDLER VectorF0 /* Note: same as STM32_TIM8_UP */
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#define STM32_TIM13_NUMBER 44 /* Note: same as STM32_TIM8_UP */
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#define STM32_HAS_TIM14 TRUE
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#define STM32_TIM14_IS_32BITS FALSE
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#define STM32_TIM14_CHANNELS 2
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#define STM32_TIM14_HANDLER VectorF4
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#define STM32_TIM14_NUMBER 45
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#define STM32_HAS_TIM15 FALSE
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#define STM32_HAS_TIM16 FALSE
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#define STM32_HAS_TIM17 FALSE
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#define STM32_HAS_TIM18 FALSE
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#define STM32_HAS_TIM19 FALSE
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#define STM32_HAS_TIM20 FALSE
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#define STM32_HAS_TIM21 FALSE
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#define STM32_HAS_TIM22 FALSE
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/* USART attributes.*/
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#define STM32_HAS_USART1 TRUE
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#define STM32_USART1_HANDLER VectorD4
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#define STM32_USART1_NUMBER 37
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#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 2) |\
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STM32_DMA_STREAM_ID_MSK(2, 5))
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#define STM32_USART1_RX_DMA_CHN 0x00400400
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#define STM32_USART1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 7)
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#define STM32_USART1_TX_DMA_CHN 0x40000000
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#define STM32_HAS_USART2 TRUE
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#define STM32_USART2_HANDLER VectorD8
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#define STM32_USART2_NUMBER 38
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#define STM32_USART2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5)
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#define STM32_USART2_RX_DMA_CHN 0x00400000
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#define STM32_USART2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 6)
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#define STM32_USART2_TX_DMA_CHN 0x04000000
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#define STM32_HAS_USART3 TRUE
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#define STM32_USART3_HANDLER VectorDC
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#define STM32_USART3_NUMBER 39
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#define STM32_USART3_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 1)
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#define STM32_USART3_RX_DMA_CHN 0x00000040
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#define STM32_USART3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) |\
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STM32_DMA_STREAM_ID_MSK(1, 4))
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#define STM32_USART3_TX_DMA_CHN 0x00074000
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#define STM32_HAS_UART4 TRUE
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#define STM32_UART4_HANDLER Vector110
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#define STM32_UART4_NUMBER 52
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#define STM32_UART4_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2)
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#define STM32_UART4_RX_DMA_CHN 0x00000400
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#define STM32_UART4_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
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#define STM32_UART4_TX_DMA_CHN 0x00040000
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#define STM32_HAS_UART5 TRUE
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#define STM32_UART5_HANDLER Vector114
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#define STM32_UART5_NUMBER 53
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#define STM32_UART5_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 0)
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#define STM32_UART5_RX_DMA_CHN 0x00000004
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#define STM32_UART5_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 7)
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#define STM32_UART5_TX_DMA_CHN 0x40000000
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#define STM32_HAS_USART6 TRUE
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#define STM32_USART6_HANDLER Vector15C
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#define STM32_USART6_NUMBER 71
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#define STM32_USART6_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 1) |\
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STM32_DMA_STREAM_ID_MSK(2, 2))
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#define STM32_USART6_RX_DMA_CHN 0x00000550
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#define STM32_USART6_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 6) |\
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STM32_DMA_STREAM_ID_MSK(2, 7))
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#define STM32_USART6_TX_DMA_CHN 0x55000000
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#define STM32_HAS_UART7 TRUE
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#define STM32_UART7_HANDLER Vector188
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#define STM32_UART7_NUMBER 83
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#define STM32_UART7_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3)
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#define STM32_UART7_RX_DMA_CHN 0x00005000
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#define STM32_UART7_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 1)
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#define STM32_UART7_TX_DMA_CHN 0x00000050
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#define STM32_HAS_UART8 TRUE
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#define STM32_UART8_HANDLER Vector18C
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#define STM32_UART8_NUMBER 83
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#define STM32_UART8_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 6)
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#define STM32_UART8_RX_DMA_CHN 0x05000000
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#define STM32_UART8_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 0)
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#define STM32_UART8_TX_DMA_CHN 0x00000005
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/* USB attributes.*/
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#define STM32_HAS_USB FALSE
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#define STM32_HAS_OTG1 TRUE
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#define STM32_OTG1_HANDLER Vector14C
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#define STM32_OTG1_NUMBER 67
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#define STM32_HAS_OTG2 TRUE
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#define STM32_OTG2_HANDLER Vector174
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#define STM32_OTG2_EP1OUT_HANDLER Vector168
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#define STM32_OTG2_EP1IN_HANDLER Vector16C
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#define STM32_OTG2_NUMBER 77
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#define STM32_OTG2_EP1OUT_NUMBER 74
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#define STM32_OTG2_EP1IN_NUMBER 75
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/* LTDC attributes.*/
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#define STM32_HAS_LTDC TRUE
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/* DMA2D attributes.*/
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#define STM32_HAS_DMA2D TRUE
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/* FSMC attributes.*/
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#define STM32_HAS_FSMC TRUE
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#define STM32_FSMC_IS_FMC TRUE
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#define STM32_FSMC_HANDLER Vector100
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#define STM32_FSMC_NUMBER 48
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#define STM32_FSMC_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\
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STM32_DMA_STREAM_ID_MSK(2, 1) |\
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STM32_DMA_STREAM_ID_MSK(2, 2) |\
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STM32_DMA_STREAM_ID_MSK(2, 3) |\
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STM32_DMA_STREAM_ID_MSK(2, 4) |\
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STM32_DMA_STREAM_ID_MSK(2, 5) |\
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STM32_DMA_STREAM_ID_MSK(2, 6) |\
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STM32_DMA_STREAM_ID_MSK(2, 7))
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#define STM32_FSMC_DMA_CHN 0x00000000
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/* LTDC attributes.*/
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#define STM32_LTDC_EV_HANDLER Vector1A0
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#define STM32_LTDC_ER_HANDLER Vector1A4
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#define STM32_LTDC_EV_NUMBER 88
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#define STM32_LTDC_ER_NUMBER 89
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/* DMA2D attributes.*/
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#define STM32_DMA2D_HANDLER Vector1A8
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#define STM32_DMA2D_NUMBER 90
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/* CRC attributes.*/
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#define STM32_HAS_CRC TRUE
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#define STM32_CRC_PROGRAMMABLE FALSE
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#endif /* defined(STM32F745xx) || defined(STM32F746xx) || defined(STM32F756xx) */
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/** @} */
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#endif /* _STM32_REGISTRY_H_ */
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/** @} */
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