145 lines
5.4 KiB
C
145 lines
5.4 KiB
C
/*
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ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
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2011,2012 Giovanni Di Sirio.
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This file is part of ChibiOS/RT.
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ChibiOS/RT is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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ChibiOS/RT is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/*
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* STM32F0xx drivers configuration.
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* The following settings override the default settings present in
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* the various device driver implementation headers.
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* Note that the settings for each driver only have effect if the whole
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* driver is enabled in halconf.h.
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*
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* IRQ priorities:
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* 3...0 Lowest...Highest.
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*
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* DMA priorities:
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* 0...3 Lowest...Highest.
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*/
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#define STM32F0xx_MCUCONF
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/*
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* HAL driver system settings.
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*/
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#define STM32_NO_INIT FALSE
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#define STM32_PVD_ENABLE FALSE
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#define STM32_PLS STM32_PLS_LEV0
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#define STM32_HSI_ENABLED TRUE
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#define STM32_HSI14_ENABLED TRUE
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#define STM32_LSI_ENABLED TRUE
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#define STM32_HSE_ENABLED FALSE
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#define STM32_LSE_ENABLED FALSE
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#define STM32_SW STM32_SW_PLL
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#define STM32_PLLSRC STM32_PLLSRC_HSI
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#define STM32_PREDIV_VALUE 1
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#define STM32_PLLMUL_VALUE 12
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#define STM32_HPRE STM32_HPRE_DIV1
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#define STM32_PPRE STM32_PPRE_DIV1
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#define STM32_ADCSW STM32_ADCSW_HSI14
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#define STM32_ADCPRE STM32_ADCPRE_DIV4
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#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK
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#define STM32_ADCPRE STM32_ADCPRE_DIV4
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#define STM32_ADCSW STM32_ADCSW_HSI14
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#define STM32_CECSW STM32_CECSW_HSI
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#define STM32_I2C1SW STM32_I2C1SW_HSI
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#define STM32_USART1SW STM32_USART1SW_PCLK
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#define STM32_RTCSEL STM32_RTCSEL_LSI
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/*
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* ADC driver system settings.
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*/
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#define STM32_ADC_USE_ADC1 FALSE
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#define STM32_ADC_ADC1_DMA_PRIORITY 2
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#define STM32_ADC_IRQ_PRIORITY 2
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#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 2
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/*
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* EXT driver system settings.
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*/
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#define STM32_EXT_EXTI0_1_IRQ_PRIORITY 3
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#define STM32_EXT_EXTI2_3_IRQ_PRIORITY 3
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#define STM32_EXT_EXTI4_15_IRQ_PRIORITY 3
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#define STM32_EXT_EXTI16_IRQ_PRIORITY 3
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#define STM32_EXT_EXTI17_IRQ_PRIORITY 3
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/*
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* GPT driver system settings.
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*/
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#define STM32_GPT_USE_TIM1 FALSE
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#define STM32_GPT_USE_TIM2 FALSE
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#define STM32_GPT_USE_TIM3 FALSE
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#define STM32_GPT_TIM1_IRQ_PRIORITY 2
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#define STM32_GPT_TIM2_IRQ_PRIORITY 2
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#define STM32_GPT_TIM3_IRQ_PRIORITY 2
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/*
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* ICU driver system settings.
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*/
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#define STM32_ICU_USE_TIM1 FALSE
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#define STM32_ICU_USE_TIM2 FALSE
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#define STM32_ICU_USE_TIM3 FALSE
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#define STM32_ICU_TIM1_IRQ_PRIORITY 3
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#define STM32_ICU_TIM2_IRQ_PRIORITY 3
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#define STM32_ICU_TIM3_IRQ_PRIORITY 3
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/*
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* PWM driver system settings.
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*/
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#define STM32_PWM_USE_ADVANCED FALSE
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#define STM32_PWM_USE_TIM1 FALSE
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#define STM32_PWM_USE_TIM2 FALSE
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#define STM32_PWM_USE_TIM3 FALSE
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#define STM32_PWM_TIM1_IRQ_PRIORITY 3
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#define STM32_PWM_TIM2_IRQ_PRIORITY 3
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#define STM32_PWM_TIM3_IRQ_PRIORITY 3
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/*
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* SERIAL driver system settings.
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*/
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#define STM32_SERIAL_USE_USART1 TRUE
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#define STM32_SERIAL_USE_USART2 FALSE
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#define STM32_SERIAL_USART1_PRIORITY 3
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#define STM32_SERIAL_USART2_PRIORITY 3
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/*
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* SPI driver system settings.
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*/
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#define STM32_SPI_USE_SPI1 FALSE
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#define STM32_SPI_USE_SPI2 FALSE
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#define STM32_SPI_SPI1_DMA_PRIORITY 1
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#define STM32_SPI_SPI2_DMA_PRIORITY 1
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#define STM32_SPI_SPI1_IRQ_PRIORITY 2
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#define STM32_SPI_SPI2_IRQ_PRIORITY 2
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#define STM32_SPI_DMA_ERROR_HOOK(spip) chSysHalt()
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/*
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* UART driver system settings.
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*/
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#define STM32_UART_USE_USART1 FALSE
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#define STM32_UART_USE_USART2 FALSE
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#define STM32_UART_USART1_IRQ_PRIORITY 3
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#define STM32_UART_USART2_IRQ_PRIORITY 3
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#define STM32_UART_USART1_DMA_PRIORITY 0
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#define STM32_UART_USART2_DMA_PRIORITY 0
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#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
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#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
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#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
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#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
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#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt()
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