226 lines
7.4 KiB
C
226 lines
7.4 KiB
C
/*
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ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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/**
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* @file STM32F4xx/hal_lld.c
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* @brief STM32F4xx/STM32F2xx HAL subsystem low level driver source.
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*
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* @addtogroup HAL
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* @{
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*/
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/* TODO: LSEBYP like in F3.*/
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#include "hal.h"
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/*===========================================================================*/
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/* Driver local definitions. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver exported variables. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver local variables and types. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver local functions. */
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/*===========================================================================*/
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/**
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* @brief Initializes the backup domain.
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* @note WARNING! Changing clock source impossible without resetting
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* of the whole BKP domain.
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*/
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static void hal_lld_backup_domain_init(void) {
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/* Backup domain access enabled and left open.*/
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PWR->CR |= PWR_CR_DBP;
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/* Reset BKP domain if different clock source selected.*/
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if ((RCC->BDCR & STM32_RTCSEL_MASK) != STM32_RTCSEL) {
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/* Backup domain reset.*/
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RCC->BDCR = RCC_BDCR_BDRST;
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RCC->BDCR = 0;
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}
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#if STM32_LSE_ENABLED
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RCC->BDCR |= RCC_BDCR_LSEON;
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while ((RCC->BDCR & RCC_BDCR_LSERDY) == 0)
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; /* Waits until LSE is stable. */
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#endif
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#if HAL_USE_RTC
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/* If the backup domain hasn't been initialized yet then proceed with
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initialization.*/
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if ((RCC->BDCR & RCC_BDCR_RTCEN) == 0) {
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/* Selects clock source.*/
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RCC->BDCR |= STM32_RTCSEL;
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/* RTC clock enabled.*/
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RCC->BDCR |= RCC_BDCR_RTCEN;
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}
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#endif /* HAL_USE_RTC */
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#if STM32_BKPRAM_ENABLE
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rccEnableBKPSRAM(false);
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PWR->CSR |= PWR_CSR_BRE;
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while ((PWR->CSR & PWR_CSR_BRR) == 0)
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; /* Waits until the regulator is stable */
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#else
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PWR->CSR &= ~PWR_CSR_BRE;
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#endif /* STM32_BKPRAM_ENABLE */
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}
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/*===========================================================================*/
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/* Driver interrupt handlers. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver exported functions. */
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/*===========================================================================*/
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/**
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* @brief Low level HAL driver initialization.
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*
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* @notapi
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*/
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void hal_lld_init(void) {
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/* Reset of all peripherals. AHB3 is not reseted because it could have
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been initialized in the board initialization file (board.c).*/
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rccResetAHB1(~0);
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rccResetAHB2(~0);
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rccResetAPB1(~RCC_APB1RSTR_PWRRST);
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rccResetAPB2(~0);
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/* PWR clock enabled.*/
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rccEnablePWRInterface(FALSE);
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/* Initializes the backup domain.*/
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hal_lld_backup_domain_init();
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#if defined(STM32_DMA_REQUIRED)
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dmaInit();
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#endif
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/* Programmable voltage detector enable.*/
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#if STM32_PVD_ENABLE
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PWR->CR |= PWR_CR_PVDE | (STM32_PLS & STM32_PLS_MASK);
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#endif /* STM32_PVD_ENABLE */
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}
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/**
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* @brief STM32F2xx clocks and PLL initialization.
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* @note All the involved constants come from the file @p board.h.
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* @note This function should be invoked just after the system reset.
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*
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* @special
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*/
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void stm32_clock_init(void) {
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#if !STM32_NO_INIT
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/* PWR clock enable.*/
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RCC->APB1ENR = RCC_APB1ENR_PWREN;
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/* PWR initialization.*/
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#if defined(STM32F4XX) || defined(__DOXYGEN__)
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PWR->CR = STM32_VOS;
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while ((PWR->CSR & PWR_CSR_VOSRDY) == 0)
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; /* Waits until power regulator is stable. */
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#else
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PWR->CR = 0;
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#endif
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/* Initial clocks setup and wait for HSI stabilization, the MSI clock is
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always enabled because it is the fallback clock when PLL the fails.*/
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RCC->CR |= RCC_CR_HSION;
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while ((RCC->CR & RCC_CR_HSIRDY) == 0)
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; /* Waits until HSI is stable. */
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#if STM32_HSE_ENABLED
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/* HSE activation.*/
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#if defined(STM32_HSE_BYPASS)
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/* HSE Bypass.*/
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RCC->CR |= RCC_CR_HSEON | RCC_CR_HSEBYP;
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#else
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/* No HSE Bypass.*/
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RCC->CR |= RCC_CR_HSEON;
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#endif
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while ((RCC->CR & RCC_CR_HSERDY) == 0)
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; /* Waits until HSE is stable. */
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#endif
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#if STM32_LSI_ENABLED
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/* LSI activation.*/
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RCC->CSR |= RCC_CSR_LSION;
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while ((RCC->CSR & RCC_CSR_LSIRDY) == 0)
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; /* Waits until LSI is stable. */
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#endif
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#if STM32_ACTIVATE_PLL
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/* PLL activation.*/
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RCC->PLLCFGR = STM32_PLLQ | STM32_PLLSRC | STM32_PLLP | STM32_PLLN |
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STM32_PLLM;
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RCC->CR |= RCC_CR_PLLON;
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while (!(RCC->CR & RCC_CR_PLLRDY))
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; /* Waits until PLL is stable. */
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#endif
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#if STM32_ACTIVATE_PLLI2S
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/* PLLI2S activation.*/
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RCC->PLLI2SCFGR = STM32_PLLI2SR | STM32_PLLI2SN;
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RCC->CR |= RCC_CR_PLLI2SON;
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while (!(RCC->CR & RCC_CR_PLLI2SRDY))
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; /* Waits until PLLI2S is stable. */
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#endif
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/* Other clock-related settings (dividers, MCO etc).*/
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RCC->CFGR |= STM32_MCO2PRE | STM32_MCO2SEL | STM32_MCO1PRE | STM32_MCO1SEL |
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STM32_RTCPRE | STM32_PPRE2 | STM32_PPRE1 | STM32_HPRE;
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/* Flash setup.*/
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#if defined(STM32_USE_REVISION_A_FIX)
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/* Some old revisions of F4x MCUs randomly crashes with compiler
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optimizations enabled AND flash caches enabled. */
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if ((DBGMCU->IDCODE == 0x20006411) && (SCB->CPUID == 0x410FC241))
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FLASH->ACR = FLASH_ACR_PRFTEN | STM32_FLASHBITS;
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else
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FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN |
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FLASH_ACR_DCEN | STM32_FLASHBITS;
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#else
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FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN |
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FLASH_ACR_DCEN | STM32_FLASHBITS;
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#endif
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/* Switching to the configured clock source if it is different from MSI.*/
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#if (STM32_SW != STM32_SW_HSI)
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RCC->CFGR |= STM32_SW; /* Switches on the selected clock source. */
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while ((RCC->CFGR & RCC_CFGR_SWS) != (STM32_SW << 2))
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;
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#endif
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#endif /* STM32_NO_INIT */
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/* SYSCFG clock enabled here because it is a multi-functional unit shared
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among multiple drivers.*/
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rccEnableAPB2(RCC_APB2ENR_SYSCFGEN, TRUE);
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}
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/** @} */
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