336 lines
9.6 KiB
C
336 lines
9.6 KiB
C
/*
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ChibiOS/HAL - Copyright (C) 2006-2014 Giovanni Di Sirio
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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/*
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Concepts and parts of this file have been contributed by Uladzimir Pylinsky
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aka barthess.
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*/
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/**
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* @file nand_lld.h
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* @brief NAND Driver subsystem low level driver header.
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*
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* @addtogroup NAND
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* @{
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*/
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#ifndef _NAND_LLD_H_
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#define _NAND_LLD_H_
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#include "fsmc.h"
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#if HAL_USE_NAND || defined(__DOXYGEN__)
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/*===========================================================================*/
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/* Driver constants. */
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/*===========================================================================*/
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#define NAND_MIN_PAGE_SIZE 256
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#define NAND_MAX_PAGE_SIZE 8192
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/*===========================================================================*/
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/* Driver pre-compile time settings. */
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/*===========================================================================*/
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/**
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* @name Configuration options
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* @{
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*/
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/**
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* @brief FSMC1 interrupt priority level setting.
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*/
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#if !defined(STM32_EMC_FSMC1_IRQ_PRIORITY) || defined(__DOXYGEN__)
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#define STM32_EMC_FSMC1_IRQ_PRIORITY 10
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#endif
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/**
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* @brief NAND driver enable switch.
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* @details If set to @p TRUE the support for NAND1 is included.
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*/
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#if !defined(STM32_NAND_USE_NAND1) || defined(__DOXYGEN__)
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#define STM32_NAND_USE_NAND1 FALSE
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#endif
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/**
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* @brief NAND driver enable switch.
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* @details If set to @p TRUE the support for NAND2 is included.
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*/
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#if !defined(STM32_NAND_USE_NAND2) || defined(__DOXYGEN__)
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#define STM32_NAND_USE_NAND2 FALSE
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#endif
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/**
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* @brief NAND DMA error hook.
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* @note The default action for DMA errors is a system halt because DMA
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* error can only happen because programming errors.
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*/
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#if !defined(STM32_NAND_DMA_ERROR_HOOK) || defined(__DOXYGEN__)
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#define STM32_NAND_DMA_ERROR_HOOK(nandp) osalSysHalt("DMA failure")
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#endif
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/**
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* @brief NAND interrupt enable switch.
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* @details If set to @p TRUE the support for internal FSMC interrupt included.
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*/
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#if !defined(STM32_NAND_USE_INT) || defined(__DOXYGEN__)
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#define STM32_NAND_USE_INT FALSE
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#endif
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/**
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* @brief NAND1 DMA priority (0..3|lowest..highest).
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*/
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#if !defined(STM32_NAND_NAND1_DMA_PRIORITY) || defined(__DOXYGEN__)
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#define STM32_NAND_NAND1_DMA_PRIORITY 0
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#endif
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/**
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* @brief NAND2 DMA priority (0..3|lowest..highest).
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*/
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#if !defined(STM32_NAND_NAND2_DMA_PRIORITY) || defined(__DOXYGEN__)
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#define STM32_NAND_NAND2_DMA_PRIORITY 0
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#endif
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/**
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* @brief DMA stream used for NAND operations.
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* @note This option is only available on platforms with enhanced DMA.
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*/
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#if !defined(STM32_NAND_DMA_STREAM) || defined(__DOXYGEN__)
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#define STM32_NAND_DMA_STREAM STM32_DMA_STREAM_ID(2, 6)
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#endif
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/** @} */
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/*===========================================================================*/
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/* Derived constants and error checks. */
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/*===========================================================================*/
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#if !STM32_NAND_USE_FSMC_NAND1 && !STM32_NAND_USE_FSMC_NAND2
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#error "NAND driver activated but no NAND peripheral assigned"
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#endif
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#if (STM32_NAND_USE_FSMC_NAND2 || STM32_NAND_USE_FSMC_NAND1) && !STM32_HAS_FSMC
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#error "FSMC not present in the selected device"
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#endif
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#if STM32_NAND_USE_EXT_INT && !HAL_USE_EXT
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#error "External interrupt controller must be enabled to use this feature"
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#endif
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#if (STM32_NAND_USE_FSMC_NAND2 || STM32_NAND_USE_FSMC_NAND1) && \
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!STM32_DMA_IS_VALID_ID(STM32_NAND_DMA_STREAM, \
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STM32_FSMC_DMA_MSK)
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#error "invalid DMA stream associated to NAND"
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#endif
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#if !defined(STM32_DMA_REQUIRED)
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#define STM32_DMA_REQUIRED
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#endif
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/*===========================================================================*/
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/* Driver data structures and types. */
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/*===========================================================================*/
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/**
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* @brief NAND driver condition flags type.
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*/
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typedef uint32_t nandflags_t;
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/**
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* @brief Type of a structure representing an NAND driver.
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*/
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typedef struct NANDDriver NANDDriver;
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/**
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* @brief Type of interrupt handler function
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*/
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typedef void (*nandisrhandler_t)(NANDDriver *nandp);
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#if STM32_NAND_USE_EXT_INT
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/**
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* @brief Type of function switching external interrupts on and off.
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*/
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typedef void (*nandisrswitch_t)(void);
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#endif /* STM32_NAND_USE_EXT_INT */
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/**
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* @brief Driver configuration structure.
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* @note It could be empty on some architectures.
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*/
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typedef struct {
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/**
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* @brief Pointer to lower level driver.
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*/
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FSMCDriver *fsmcp;
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/**
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* @brief Number of erase blocks in NAND device.
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*/
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uint32_t blocks;
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/**
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* @brief Number of data bytes in page.
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*/
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uint32_t page_data_size;
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/**
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* @brief Number of spare bytes in page.
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*/
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uint32_t page_spare_size;
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/**
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* @brief Number of pages in block.
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*/
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uint32_t pages_per_block;
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#if NAND_USE_BAD_MAP
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/**
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* @brief Pointer to bad block map.
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* @details One bit per block. Memory for map must be allocated by user.
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*/
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uint32_t *bb_map;
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#endif /* NAND_USE_BAD_MAP */
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/**
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* @brief Number of write cycles for row addressing.
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*/
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uint8_t rowcycles;
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/**
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* @brief Number of write cycles for column addressing.
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*/
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uint8_t colcycles;
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/* End of the mandatory fields.*/
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/**
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* @brief Number of wait cycles. This value will be used both for
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* PMEM and PATTR registers
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*
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* @note For proper calculation procedure please look at AN2784 document
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* from STMicroelectronics.
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*/
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uint32_t pmem;
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#if STM32_NAND_USE_EXT_INT
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/**
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* @brief Function enabling interrupts from EXTI
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*/
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nandisrswitch_t ext_nand_isr_enable;
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/**
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* @brief Function disabling interrupts from EXTI
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*/
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nandisrswitch_t ext_nand_isr_disable;
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#endif /* STM32_NAND_USE_EXT_INT */
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} NANDConfig;
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/**
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* @brief Structure representing an NAND driver.
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*/
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struct NANDDriver {
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/**
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* @brief Driver state.
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*/
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nandstate_t state;
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/**
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* @brief Current configuration data.
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*/
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const NANDConfig *config;
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/**
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* @brief Array to store bad block map.
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*/
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#if NAND_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__)
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#if CH_CFG_USE_MUTEXES || defined(__DOXYGEN__)
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/**
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* @brief Mutex protecting the bus.
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*/
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mutex_t mutex;
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#elif CH_CFG_USE_SEMAPHORES
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semaphore_t semaphore;
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#endif
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#endif /* NAND_USE_MUTUAL_EXCLUSION */
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/* End of the mandatory fields.*/
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/**
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* @brief Function enabling interrupts from FSMC
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*/
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nandisrhandler_t isr_handler;
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/**
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* @brief Pointer to current transaction buffer
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*/
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uint8_t *rxdata;
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/**
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* @brief Current transaction length
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*/
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size_t datalen;
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/**
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* @brief DMA mode bit mask.
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*/
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uint32_t dmamode;
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/**
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* @brief DMA channel.
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*/
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const stm32_dma_stream_t *dma;
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/**
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* @brief Thread waiting for I/O completion.
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*/
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thread_t *thread;
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/**
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* @brief Pointer to the FSMC NAND registers block.
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*/
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FSMC_NAND_TypeDef *nand;
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/**
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* @brief Memory mapping for data.
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*/
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uint8_t *map_data;
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/**
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* @brief Memory mapping for commands.
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*/
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uint8_t *map_cmd;
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/**
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* @brief Memory mapping for addresses.
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*/
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uint8_t *map_addr;
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};
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/*===========================================================================*/
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/* Driver macros. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* External declarations. */
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/*===========================================================================*/
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#if STM32_NAND_USE_FSMC_NAND1 && !defined(__DOXYGEN__)
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extern NANDDriver NANDD1;
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#endif
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#if STM32_NAND_USE_FSMC_NAND2 && !defined(__DOXYGEN__)
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extern NANDDriver NANDD2;
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#endif
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#ifdef __cplusplus
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extern "C" {
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#endif
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void nand_lld_init(void);
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void nand_lld_start(NANDDriver *nandp);
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void nand_lld_stop(NANDDriver *nandp);
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uint8_t nand_lld_write_data(NANDDriver *nandp, const uint8_t *data,
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size_t datalen, uint8_t *addr, size_t addrlen, uint32_t *ecc);
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void nand_lld_read_data(NANDDriver *nandp, uint8_t *data,
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size_t datalen, uint8_t *addr, size_t addrlen, uint32_t *ecc);
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void nand_lld_polled_read_data(NANDDriver *nandp, uint8_t *data, size_t len);
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uint8_t nand_lld_erase(NANDDriver *nandp, uint8_t *addr, size_t addrlen);
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void nand_lld_write_addr(NANDDriver *nandp, const uint8_t *addr, size_t len);
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void nand_lld_write_cmd(NANDDriver *nandp, uint8_t cmd);
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uint8_t nand_lld_read_status(NANDDriver *nandp);
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#ifdef __cplusplus
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}
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#endif
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#endif /* HAL_USE_NAND */
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#endif /* _NAND_LLD_H_ */
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/** @} */
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