469 lines
12 KiB
C
469 lines
12 KiB
C
/*
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ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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/**
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* @file STM32/gpt_lld.c
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* @brief STM32 GPT subsystem low level driver source.
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*
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* @addtogroup GPT
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* @{
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*/
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#include "ch.h"
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#include "hal.h"
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#if HAL_USE_GPT || defined(__DOXYGEN__)
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/*===========================================================================*/
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/* Driver local definitions. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver exported variables. */
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/*===========================================================================*/
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/**
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* @brief GPTD1 driver identifier.
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* @note The driver GPTD1 allocates the complex timer TIM1 when enabled.
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*/
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#if STM32_GPT_USE_TIM1 || defined(__DOXYGEN__)
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GPTDriver GPTD1;
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#endif
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/**
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* @brief GPTD2 driver identifier.
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* @note The driver GPTD2 allocates the timer TIM2 when enabled.
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*/
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#if STM32_GPT_USE_TIM2 || defined(__DOXYGEN__)
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GPTDriver GPTD2;
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#endif
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/**
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* @brief GPTD3 driver identifier.
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* @note The driver GPTD3 allocates the timer TIM3 when enabled.
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*/
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#if STM32_GPT_USE_TIM3 || defined(__DOXYGEN__)
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GPTDriver GPTD3;
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#endif
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/**
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* @brief GPTD4 driver identifier.
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* @note The driver GPTD4 allocates the timer TIM4 when enabled.
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*/
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#if STM32_GPT_USE_TIM4 || defined(__DOXYGEN__)
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GPTDriver GPTD4;
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#endif
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/**
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* @brief GPTD5 driver identifier.
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* @note The driver GPTD5 allocates the timer TIM5 when enabled.
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*/
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#if STM32_GPT_USE_TIM5 || defined(__DOXYGEN__)
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GPTDriver GPTD5;
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#endif
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/**
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* @brief GPTD8 driver identifier.
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* @note The driver GPTD8 allocates the timer TIM8 when enabled.
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*/
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#if STM32_GPT_USE_TIM8 || defined(__DOXYGEN__)
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GPTDriver GPTD8;
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#endif
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/*===========================================================================*/
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/* Driver local variables and types. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver local functions. */
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/*===========================================================================*/
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/**
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* @brief Shared IRQ handler.
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*
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* @param[in] gptp pointer to a @p GPTDriver object
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*/
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static void gpt_lld_serve_interrupt(GPTDriver *gptp) {
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gptp->tim->SR = 0;
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if (gptp->state == GPT_ONESHOT) {
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gptp->state = GPT_READY; /* Back in GPT_READY state. */
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gpt_lld_stop_timer(gptp); /* Timer automatically stopped. */
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}
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gptp->config->callback(gptp);
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}
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/*===========================================================================*/
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/* Driver interrupt handlers. */
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/*===========================================================================*/
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#if STM32_GPT_USE_TIM1
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#if !defined(STM32_TIM1_UP_HANDLER)
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#error "STM32_TIM1_UP_HANDLER not defined"
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#endif
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/**
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* @brief TIM2 interrupt handler.
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*
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* @isr
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*/
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CH_IRQ_HANDLER(STM32_TIM1_UP_HANDLER) {
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CH_IRQ_PROLOGUE();
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gpt_lld_serve_interrupt(&GPTD1);
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CH_IRQ_EPILOGUE();
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}
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#endif /* STM32_GPT_USE_TIM1 */
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#if STM32_GPT_USE_TIM2
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#if !defined(STM32_TIM2_HANDLER)
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#error "STM32_TIM2_HANDLER not defined"
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#endif
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/**
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* @brief TIM2 interrupt handler.
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*
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* @isr
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*/
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CH_IRQ_HANDLER(STM32_TIM2_HANDLER) {
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CH_IRQ_PROLOGUE();
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gpt_lld_serve_interrupt(&GPTD2);
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CH_IRQ_EPILOGUE();
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}
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#endif /* STM32_GPT_USE_TIM2 */
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#if STM32_GPT_USE_TIM3
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#if !defined(STM32_TIM3_HANDLER)
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#error "STM32_TIM3_HANDLER not defined"
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#endif
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/**
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* @brief TIM3 interrupt handler.
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*
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* @isr
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*/
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CH_IRQ_HANDLER(STM32_TIM3_HANDLER) {
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CH_IRQ_PROLOGUE();
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gpt_lld_serve_interrupt(&GPTD3);
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CH_IRQ_EPILOGUE();
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}
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#endif /* STM32_GPT_USE_TIM3 */
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#if STM32_GPT_USE_TIM4
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#if !defined(STM32_TIM4_HANDLER)
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#error "STM32_TIM4_HANDLER not defined"
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#endif
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/**
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* @brief TIM4 interrupt handler.
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*
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* @isr
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*/
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CH_IRQ_HANDLER(STM32_TIM4_HANDLER) {
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CH_IRQ_PROLOGUE();
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gpt_lld_serve_interrupt(&GPTD4);
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CH_IRQ_EPILOGUE();
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}
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#endif /* STM32_GPT_USE_TIM4 */
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#if STM32_GPT_USE_TIM5
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#if !defined(STM32_TIM5_HANDLER)
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#error "STM32_TIM5_HANDLER not defined"
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#endif
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/**
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* @brief TIM5 interrupt handler.
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*
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* @isr
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*/
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CH_IRQ_HANDLER(STM32_TIM5_HANDLER) {
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CH_IRQ_PROLOGUE();
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gpt_lld_serve_interrupt(&GPTD5);
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CH_IRQ_EPILOGUE();
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}
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#endif /* STM32_GPT_USE_TIM5 */
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#if STM32_GPT_USE_TIM8
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#if !defined(STM32_TIM8_UP_HANDLER)
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#error "STM32_TIM8_UP_HANDLER not defined"
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#endif
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/**
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* @brief TIM8 interrupt handler.
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*
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* @isr
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*/
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CH_IRQ_HANDLER(STM32_TIM8_UP_HANDLER) {
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CH_IRQ_PROLOGUE();
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gpt_lld_serve_interrupt(&GPTD8);
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CH_IRQ_EPILOGUE();
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}
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#endif /* STM32_GPT_USE_TIM8 */
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/*===========================================================================*/
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/* Driver exported functions. */
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/*===========================================================================*/
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/**
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* @brief Low level GPT driver initialization.
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*
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* @notapi
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*/
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void gpt_lld_init(void) {
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#if STM32_GPT_USE_TIM1
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/* Driver initialization.*/
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GPTD1.tim = STM32_TIM1;
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gptObjectInit(&GPTD1);
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#endif
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#if STM32_GPT_USE_TIM2
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/* Driver initialization.*/
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GPTD2.tim = STM32_TIM2;
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gptObjectInit(&GPTD2);
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#endif
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#if STM32_GPT_USE_TIM3
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/* Driver initialization.*/
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GPTD3.tim = STM32_TIM3;
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gptObjectInit(&GPTD3);
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#endif
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#if STM32_GPT_USE_TIM4
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/* Driver initialization.*/
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GPTD4.tim = STM32_TIM4;
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gptObjectInit(&GPTD4);
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#endif
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#if STM32_GPT_USE_TIM5
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/* Driver initialization.*/
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GPTD5.tim = STM32_TIM5;
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gptObjectInit(&GPTD5);
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#endif
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#if STM32_GPT_USE_TIM8
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/* Driver initialization.*/
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GPTD8.tim = STM32_TIM8;
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gptObjectInit(&GPTD8);
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#endif
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}
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/**
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* @brief Configures and activates the GPT peripheral.
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*
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* @param[in] gptp pointer to the @p GPTDriver object
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*
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* @notapi
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*/
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void gpt_lld_start(GPTDriver *gptp) {
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uint16_t psc;
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if (gptp->state == GPT_STOP) {
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/* Clock activation.*/
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#if STM32_GPT_USE_TIM1
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if (&GPTD1 == gptp) {
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rccEnableTIM1(FALSE);
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rccResetTIM1();
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nvicEnableVector(STM32_TIM1_UP_NUMBER,
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CORTEX_PRIORITY_MASK(STM32_GPT_TIM1_IRQ_PRIORITY));
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gptp->clock = STM32_TIMCLK2;
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}
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#endif
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#if STM32_GPT_USE_TIM2
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if (&GPTD2 == gptp) {
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rccEnableTIM2(FALSE);
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rccResetTIM2();
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nvicEnableVector(STM32_TIM2_NUMBER,
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CORTEX_PRIORITY_MASK(STM32_GPT_TIM2_IRQ_PRIORITY));
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gptp->clock = STM32_TIMCLK1;
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}
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#endif
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#if STM32_GPT_USE_TIM3
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if (&GPTD3 == gptp) {
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rccEnableTIM3(FALSE);
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rccResetTIM3();
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nvicEnableVector(STM32_TIM3_NUMBER,
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CORTEX_PRIORITY_MASK(STM32_GPT_TIM3_IRQ_PRIORITY));
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gptp->clock = STM32_TIMCLK1;
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}
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#endif
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#if STM32_GPT_USE_TIM4
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if (&GPTD4 == gptp) {
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rccEnableTIM4(FALSE);
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rccResetTIM4();
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nvicEnableVector(STM32_TIM4_NUMBER,
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CORTEX_PRIORITY_MASK(STM32_GPT_TIM4_IRQ_PRIORITY));
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gptp->clock = STM32_TIMCLK1;
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}
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#endif
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#if STM32_GPT_USE_TIM5
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if (&GPTD5 == gptp) {
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rccEnableTIM5(FALSE);
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rccResetTIM5();
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nvicEnableVector(STM32_TIM5_NUMBER,
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CORTEX_PRIORITY_MASK(STM32_GPT_TIM5_IRQ_PRIORITY));
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gptp->clock = STM32_TIMCLK1;
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}
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#endif
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#if STM32_GPT_USE_TIM8
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if (&GPTD8 == gptp) {
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rccEnableTIM8(FALSE);
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rccResetTIM8();
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nvicEnableVector(STM32_TIM8_UP_NUMBER,
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CORTEX_PRIORITY_MASK(STM32_GPT_TIM8_IRQ_PRIORITY));
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gptp->clock = STM32_TIMCLK2;
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}
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#endif
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}
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/* Prescaler value calculation.*/
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psc = (uint16_t)((gptp->clock / gptp->config->frequency) - 1);
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chDbgAssert(((uint32_t)(psc + 1) * gptp->config->frequency) == gptp->clock,
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"gpt_lld_start(), #1", "invalid frequency");
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/* Timer configuration.*/
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gptp->tim->CR1 = 0; /* Initially stopped. */
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gptp->tim->CR2 = TIM_CR2_CCDS; /* DMA on UE (if any). */
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gptp->tim->PSC = psc; /* Prescaler value. */
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gptp->tim->DIER = 0;
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}
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/**
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* @brief Deactivates the GPT peripheral.
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*
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* @param[in] gptp pointer to the @p GPTDriver object
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*
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* @notapi
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*/
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void gpt_lld_stop(GPTDriver *gptp) {
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if (gptp->state == GPT_READY) {
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gptp->tim->CR1 = 0; /* Timer disabled. */
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gptp->tim->DIER = 0; /* All IRQs disabled. */
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gptp->tim->SR = 0; /* Clear eventual pending IRQs. */
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#if STM32_GPT_USE_TIM1
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if (&GPTD1 == gptp) {
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nvicDisableVector(STM32_TIM1_UP_NUMBER);
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rccDisableTIM1(FALSE);
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}
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#endif
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#if STM32_GPT_USE_TIM2
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if (&GPTD2 == gptp) {
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nvicDisableVector(STM32_TIM2_NUMBER);
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rccDisableTIM2(FALSE);
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}
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#endif
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#if STM32_GPT_USE_TIM3
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if (&GPTD3 == gptp) {
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nvicDisableVector(STM32_TIM3_NUMBER);
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rccDisableTIM3(FALSE);
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}
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#endif
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#if STM32_GPT_USE_TIM4
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if (&GPTD4 == gptp) {
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nvicDisableVector(STM32_TIM4_NUMBER);
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rccDisableTIM4(FALSE);
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}
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#endif
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#if STM32_GPT_USE_TIM5
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if (&GPTD5 == gptp) {
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nvicDisableVector(STM32_TIM5_NUMBER);
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rccDisableTIM5(FALSE);
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}
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#endif
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#if STM32_GPT_USE_TIM8
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if (&GPTD8 == gptp) {
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nvicDisableVector(STM32_TIM8_UP_NUMBER);
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rccDisableTIM8(FALSE);
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}
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#endif
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}
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}
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/**
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* @brief Starts the timer in continuous mode.
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*
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* @param[in] gptp pointer to the @p GPTDriver object
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* @param[in] interval period in ticks
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*
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* @notapi
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*/
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void gpt_lld_start_timer(GPTDriver *gptp, gptcnt_t interval) {
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gptp->tim->ARR = interval - 1; /* Time constant. */
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gptp->tim->EGR = TIM_EGR_UG; /* Update event. */
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gptp->tim->CNT = 0; /* Reset counter. */
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/* NOTE: After generating the UG event it takes several clock cycles before
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SR bit 0 goes to 1. This is because the clearing of CNT has been inserted
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before the clearing of SR, to give it some time.*/
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gptp->tim->SR = 0; /* Clear pending IRQs (if any). */
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gptp->tim->DIER = TIM_DIER_UIE; /* Update Event IRQ enabled. */
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gptp->tim->CR1 = TIM_CR1_URS | TIM_CR1_CEN;
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}
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/**
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* @brief Stops the timer.
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*
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* @param[in] gptp pointer to the @p GPTDriver object
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*
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* @notapi
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*/
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void gpt_lld_stop_timer(GPTDriver *gptp) {
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gptp->tim->CR1 = 0; /* Initially stopped. */
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gptp->tim->SR = 0; /* Clear pending IRQs (if any). */
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gptp->tim->DIER = 0; /* Interrupts disabled. */
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}
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/**
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* @brief Starts the timer in one shot mode and waits for completion.
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* @details This function specifically polls the timer waiting for completion
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* in order to not have extra delays caused by interrupt servicing,
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* this function is only recommended for short delays.
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*
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* @param[in] gptp pointer to the @p GPTDriver object
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* @param[in] interval time interval in ticks
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*
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* @notapi
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*/
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void gpt_lld_polled_delay(GPTDriver *gptp, gptcnt_t interval) {
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gptp->tim->ARR = interval - 1; /* Time constant. */
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gptp->tim->EGR = TIM_EGR_UG; /* Update event. */
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gptp->tim->SR = 0; /* Clear pending IRQs (if any). */
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gptp->tim->CR1 = TIM_CR1_OPM | TIM_CR1_URS | TIM_CR1_CEN;
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while (!(gptp->tim->SR & TIM_SR_UIF))
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;
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}
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#endif /* HAL_USE_GPT */
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/** @} */
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