153 lines
4.9 KiB
ArmAsm
153 lines
4.9 KiB
ArmAsm
/*
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ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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/**
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* @file crt0.s
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* @brief Generic ARM startup file.
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*
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* @addtogroup ARM_GCC_STARTUP
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* @{
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*/
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#if !defined(__DOXYGEN__)
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.set MODE_USR, 0x10
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.set MODE_FIQ, 0x11
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.set MODE_IRQ, 0x12
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.set MODE_SVC, 0x13
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.set MODE_ABT, 0x17
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.set MODE_UND, 0x1B
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.set MODE_SYS, 0x1F
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.set I_BIT, 0x80
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.set F_BIT, 0x40
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.text
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.code 32
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.balign 4
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/*
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* Reset handler.
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*/
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.global Reset_Handler
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Reset_Handler:
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/*
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* Stack pointers initialization.
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*/
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ldr r0, =__stacks_end__
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/* Undefined */
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msr CPSR_c, #MODE_UND | I_BIT | F_BIT
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mov sp, r0
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ldr r1, =__und_stack_size__
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sub r0, r0, r1
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/* Abort */
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msr CPSR_c, #MODE_ABT | I_BIT | F_BIT
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mov sp, r0
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ldr r1, =__abt_stack_size__
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sub r0, r0, r1
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/* FIQ */
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msr CPSR_c, #MODE_FIQ | I_BIT | F_BIT
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mov sp, r0
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ldr r1, =__fiq_stack_size__
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sub r0, r0, r1
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/* IRQ */
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msr CPSR_c, #MODE_IRQ | I_BIT | F_BIT
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mov sp, r0
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ldr r1, =__irq_stack_size__
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sub r0, r0, r1
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/* Supervisor */
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msr CPSR_c, #MODE_SVC | I_BIT | F_BIT
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mov sp, r0
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ldr r1, =__svc_stack_size__
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sub r0, r0, r1
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/* System */
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msr CPSR_c, #MODE_SYS | I_BIT | F_BIT
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mov sp, r0
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// ldr r1, =__sys_stack_size__
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// sub r0, r0, r1
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/*
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* Early initialization.
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*/
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#if !defined(THUMB_NO_INTERWORKING)
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bl __early_init
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#else /* defined(THUMB_NO_INTERWORKING) */
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add r0, pc, #1
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bx r0
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.code 16
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bl __early_init
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mov r0, pc
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bx r0
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.code 32
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#endif /* defined(THUMB_NO_INTERWORKING) */
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/*
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* Data initialization.
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* NOTE: It assumes that the DATA size is a multiple of 4.
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*/
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ldr r1, =_textdata
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ldr r2, =_data
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ldr r3, =_edata
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dataloop:
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cmp r2, r3
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ldrlo r0, [r1], #4
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strlo r0, [r2], #4
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blo dataloop
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/*
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* BSS initialization.
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* NOTE: It assumes that the BSS size is a multiple of 4.
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*/
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mov r0, #0
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ldr r1, =_bss_start
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ldr r2, =_bss_end
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bssloop:
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cmp r1, r2
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strlo r0, [r1], #4
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blo bssloop
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/*
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* Late initialization.
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*/
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#if !defined(THUMB_NO_INTERWORKING)
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bl __late_init
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#else /* defined(THUMB_NO_INTERWORKING) */
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add r0, pc, #1
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bx r0
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.code 16
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bl __late_init
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mov r0, pc
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bx r0
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.code 32
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#endif /* defined(THUMB_NO_INTERWORKING) */
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/*
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* Main program invocation.
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*/
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#if defined(THUMB_NO_INTERWORKING)
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add r0, pc, #1
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bx r0
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.code 16
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bl main
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ldr r1, =__default_exit
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bx r1
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.code 32
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#else /* !defined(THUMB_NO_INTERWORKING) */
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bl main
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b __default_exit
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#endif /* !defined(THUMB_NO_INTERWORKING) */
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#endif /* !defined(__DOXYGEN__) */
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/** @} */
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