175 lines
6.5 KiB
ArmAsm
175 lines
6.5 KiB
ArmAsm
/*
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ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio.
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This file is part of ChibiOS/RT.
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ChibiOS/RT is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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ChibiOS/RT is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/**
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* @file PPC/ivor.s
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* @brief PowerPC IVORx handlers.
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*
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* @addtogroup PPC_CORE
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* @{
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*/
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/** @cond never */
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/*
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* INTC registers address.
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*/
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.equ INTC_IACKR, 0xfff48010
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.equ INTC_EOIR, 0xfff48018
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.section .handlers
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/*
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* IVOR10 handler (Book-E decrementer).
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*/
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.align 4
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.globl IVOR10
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IVOR10:
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/* Creation of the external stack frame (extctx structure).*/
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stwu %sp, -80(%sp) /* Size of the extctx structure.*/
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stw %r0, 32(%sp) /* Saves GPR0. */
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mfSRR0 %r0
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stw %r0, 8(%sp) /* Saves PC. */
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mfSRR1 %r0
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stw %r0, 12(%sp) /* Saves MSR. */
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mfCR %r0
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stw %r0, 16(%sp) /* Saves CR. */
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mfLR %r0
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stw %r0, 20(%sp) /* Saves LR. */
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mfCTR %r0
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stw %r0, 24(%sp) /* Saves CTR. */
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mfXER %r0
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stw %r0, 28(%sp) /* Saves XER. */
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stw %r3, 36(%sp) /* Saves GPR3...GPR12. */
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stw %r4, 40(%sp)
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stw %r5, 44(%sp)
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stw %r6, 48(%sp)
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stw %r7, 52(%sp)
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stw %r8, 56(%sp)
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stw %r9, 60(%sp)
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stw %r10, 64(%sp)
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stw %r11, 68(%sp)
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stw %r12, 72(%sp)
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/* Reset DIE bit in TSR register.*/
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lis %r3, 0x0800 /* DIS bit mask. */
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mtspr 336, %r3 /* TSR register. */
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/* System tick handler invokation.*/
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bl chSysTimerHandlerI
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bl chSchIsRescRequiredExI
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cmpli cr0, %r3, 0
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beq cr0, .ctxrestore
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bl chSchDoRescheduleI
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b .ctxrestore
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/*
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* IVOR4 handler (Book-E external interrupt).
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*/
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.align 4
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.globl IVOR4
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IVOR4:
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/* Creation of the external stack frame (extctx structure).*/
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stwu %sp, -80(%sp) /* Size of the extctx structure.*/
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stw %r0, 32(%sp) /* Saves GPR0. */
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mfSRR0 %r0
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stw %r0, 8(%sp) /* Saves PC. */
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mfSRR1 %r0
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stw %r0, 12(%sp) /* Saves MSR. */
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mfCR %r0
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stw %r0, 16(%sp) /* Saves CR. */
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mfLR %r0
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stw %r0, 20(%sp) /* Saves LR. */
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mfCTR %r0
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stw %r0, 24(%sp) /* Saves CTR. */
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mfXER %r0
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stw %r0, 28(%sp) /* Saves XER. */
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stw %r3, 36(%sp) /* Saves GPR3...GPR12. */
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stw %r4, 40(%sp)
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stw %r5, 44(%sp)
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stw %r6, 48(%sp)
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stw %r7, 52(%sp)
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stw %r8, 56(%sp)
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stw %r9, 60(%sp)
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stw %r10, 64(%sp)
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stw %r11, 68(%sp)
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stw %r12, 72(%sp)
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/* Software vector address from the INTC register.*/
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lis %r3, INTC_IACKR@h
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ori %r3, %r3, INTC_IACKR@l /* IACKR register address. */
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lwz %r3, 0(%r3) /* IACKR register value. */
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lwz %r3, 0(%r3)
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mtCTR %r3 /* Software handler address. */
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#if PPC_USE_IRQ_PREEMPTION
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/* Allows preemption while executing the software handler.*/
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wrteei 1
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#endif
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/* Exectes the software handler.*/
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bctrl
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#if PPC_USE_IRQ_PREEMPTION
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/* Prevents preemption again.*/
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wrteei 0
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#endif
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/* Informs the INTC that the interrupt has been served.*/
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mbar 0
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lis %r3, INTC_EOIR@h
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ori %r3, %r3, INTC_EOIR@l
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stw %r3, 0(%r3) /* Writing any value should do. */
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/* Verifies if a reschedulation is required.*/
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bl chSchIsRescRequiredExI
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cmpli cr0, %r3, 0
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beq cr0, .ctxrestore
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bl chSchDoRescheduleI
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/* Context restore.*/
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.ctxrestore:
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lwz %r3, 36(%sp) /* Restores GPR3...GPR12. */
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lwz %r4, 40(%sp)
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lwz %r5, 44(%sp)
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lwz %r6, 48(%sp)
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lwz %r7, 52(%sp)
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lwz %r8, 56(%sp)
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lwz %r9, 60(%sp)
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lwz %r10, 64(%sp)
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lwz %r11, 68(%sp)
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lwz %r12, 72(%sp)
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lwz %r0, 8(%sp)
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mtSRR0 %r0 /* Restores PC. */
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lwz %r0, 12(%sp)
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mtSRR1 %r0 /* Restores MSR. */
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lwz %r0, 16(%sp)
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mtCR %r0 /* Restores CR. */
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lwz %r0, 20(%sp)
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mtLR %r0 /* Restores LR. */
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lwz %r0, 24(%sp)
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mtCTR %r0 /* Restores CTR. */
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lwz %r0, 28(%sp)
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mtXER %r0 /* Restores XER. */
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lwz %r0, 32(%sp) /* Restores GPR0. */
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addi %sp, %sp, 80 /* Back to the previous frame. */
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rfi
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/** @endcond */
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/** @} */
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