410 lines
18 KiB
C
410 lines
18 KiB
C
/*
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ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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/**
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* @file STM32L0xx/stm32_registry.h
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* @brief STM32L0xx capabilities registry.
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*
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* @addtogroup HAL
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* @{
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*/
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#ifndef _STM32_REGISTRY_H_
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#define _STM32_REGISTRY_H_
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/*===========================================================================*/
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/* Platform capabilities. */
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/*===========================================================================*/
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/**
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* @name STM32L4xx capabilities
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* @{
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*/
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/* ADC attributes.*/
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#define STM32_HAS_ADC1 TRUE
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#define STM32_ADC1_HANDLER Vector88
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#define STM32_ADC1_NUMBER 18
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#define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1) |\
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STM32_DMA_STREAM_ID_MSK(2, 3))
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#define STM32_ADC1_DMA_CHN 0x00000000
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#define STM32_HAS_ADC2 TRUE
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#define STM32_ADC2_HANDLER Vector88
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#define STM32_ADC2_NUMBER 18
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#define STM32_ADC2_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
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STM32_DMA_STREAM_ID_MSK(2, 4))
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#define STM32_ADC2_DMA_CHN 0x00000000
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#define STM32_HAS_ADC3 TRUE
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#define STM32_ADC3_HANDLER VectorFC
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#define STM32_ADC3_NUMBER 47
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#define STM32_ADC3_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) |\
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STM32_DMA_STREAM_ID_MSK(2, 5))
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#define STM32_ADC3_DMA_CHN 0x00000000
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#define STM32_HAS_ADC4 FALSE
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/* CAN attributes.*/
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#define STM32_HAS_CAN1 TRUE
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#define STM32_HAS_CAN2 FALSE
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#define STM32_CAN_MAX_FILTERS 14
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/* DAC attributes.*/
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#define STM32_HAS_DAC1_CH1 TRUE
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#define STM32_DAC1_CH1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3)|\
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STM32_DMA_STREAM_ID_MSK(2, 4))
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#define STM32_DAC1_CH1_DMA_CHN 0x00005600
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#define STM32_HAS_DAC1_CH2 TRUE
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#define STM32_DAC1_CH2_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4)|\
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STM32_DMA_STREAM_ID_MSK(2, 5))
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#define STM32_DAC1_CH2_DMA_CHN 0x00033000
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#define STM32_HAS_DAC2_CH1 FALSE
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#define STM32_HAS_DAC2_CH2 FALSE
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/* DMA attributes.*/
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#define STM32_ADVANCED_DMA TRUE
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#define STM32_DMA_SUPPORTS_CSELR TRUE
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#define STM32_DMA1_NUM_CHANNELS 7
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#define STM32_DMA1_CH1_HANDLER Vector6C
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#define STM32_DMA1_CH2_HANDLER Vector70
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#define STM32_DMA1_CH3_HANDLER Vector74
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#define STM32_DMA1_CH4_HANDLER Vector78
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#define STM32_DMA1_CH5_HANDLER Vector7C
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#define STM32_DMA1_CH6_HANDLER Vector80
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#define STM32_DMA1_CH7_HANDLER Vector84
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#define STM32_DMA1_CH1_NUMBER 11
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#define STM32_DMA1_CH2_NUMBER 12
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#define STM32_DMA1_CH3_NUMBER 13
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#define STM32_DMA1_CH4_NUMBER 14
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#define STM32_DMA1_CH5_NUMBER 15
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#define STM32_DMA1_CH6_NUMBER 16
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#define STM32_DMA1_CH7_NUMBER 17
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#define STM32_DMA2_NUM_CHANNELS 7
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#define STM32_DMA2_CH1_HANDLER Vector120
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#define STM32_DMA2_CH2_HANDLER Vector124
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#define STM32_DMA2_CH3_HANDLER Vector128
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#define STM32_DMA2_CH4_HANDLER Vector12C
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#define STM32_DMA2_CH5_HANDLER Vector130
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#define STM32_DMA2_CH6_HANDLER Vector150
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#define STM32_DMA2_CH7_HANDLER Vector154
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#define STM32_DMA2_CH1_NUMBER 56
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#define STM32_DMA2_CH2_NUMBER 57
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#define STM32_DMA2_CH3_NUMBER 58
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#define STM32_DMA2_CH4_NUMBER 59
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#define STM32_DMA2_CH5_NUMBER 60
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#define STM32_DMA2_CH6_NUMBER 68
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#define STM32_DMA2_CH7_NUMBER 69
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/* ETH attributes.*/
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#define STM32_HAS_ETH FALSE
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/* EXTI attributes.*/
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#define STM32_EXTI_NUM_LINES 39
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#define STM32_EXTI_IMR_MASK 0xFF820000U
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#define STM32_EXTI_IMR2_MASK 0xFFFFFF87U
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#define STM32_EXTI_LINE0_HANDLER Vector58
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#define STM32_EXTI_LINE1_HANDLER Vector5C
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#define STM32_EXTI_LINE2_HANDLER Vector60
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#define STM32_EXTI_LINE3_HANDLER Vector64
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#define STM32_EXTI_LINE4_HANDLER Vector68
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#define STM32_EXTI_LINE5_9_HANDLER Vector9C
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#define STM32_EXTI_LINE10_15_HANDLER VectorE0
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#define STM32_EXTI_LINE1635_38_HANDLER Vector44
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#define STM32_EXTI_LINE18_HANDLER VectorE4
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#define STM32_EXTI_LINE19_HANDLER Vector48
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#define STM32_EXTI_LINE20_HANDLER Vector4C
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#define STM32_EXTI_LINE2122_HANDLER Vector140
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#define STM32_EXTI_LINE0_NUMBER 6
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#define STM32_EXTI_LINE1_NUMBER 7
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#define STM32_EXTI_LINE2_NUMBER 8
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#define STM32_EXTI_LINE3_NUMBER 9
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#define STM32_EXTI_LINE4_NUMBER 10
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#define STM32_EXTI_LINE5_9_NUMBER 23
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#define STM32_EXTI_LINE10_15_NUMBER 40
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#define STM32_EXTI_LINE1635_38_NUMBER 1
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#define STM32_EXTI_LINE18_NUMBER 41
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#define STM32_EXTI_LINE19_NUMBER 2
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#define STM32_EXTI_LINE20_NUMBER 3
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#define STM32_EXTI_LINE2122_NUMBER 64
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/* GPIO attributes.*/
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#define STM32_HAS_GPIOA TRUE
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#define STM32_HAS_GPIOB TRUE
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#define STM32_HAS_GPIOC TRUE
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#define STM32_HAS_GPIOD TRUE
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#define STM32_HAS_GPIOE TRUE
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#define STM32_HAS_GPIOF TRUE
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#define STM32_HAS_GPIOG TRUE
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#define STM32_HAS_GPIOH TRUE
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#define STM32_HAS_GPIOI FALSE
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#define STM32_HAS_GPIOJ FALSE
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#define STM32_HAS_GPIOK FALSE
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#define STM32_GPIO_EN_MASK (RCC_AHB2ENR_GPIOAEN | \
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RCC_AHB2ENR_GPIOBEN | \
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RCC_AHB2ENR_GPIOCEN | \
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RCC_AHB2ENR_GPIODEN | \
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RCC_AHB2ENR_GPIOEEN | \
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RCC_AHB2ENR_GPIOFEN | \
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RCC_AHB2ENR_GPIOGEN | \
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RCC_AHB2ENR_GPIOHEN)
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/* I2C attributes.*/
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#define STM32_HAS_I2C1 TRUE
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#define STM32_I2C1_EVENT_HANDLER VectorBC
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#define STM32_I2C1_EVENT_NUMBER 31
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#define STM32_I2C1_ERROR_HANDLER VectorC0
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#define STM32_I2C1_ERROR_NUMBER 32
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#define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7) |\
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STM32_DMA_STREAM_ID_MSK(2, 6))
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#define STM32_I2C1_RX_DMA_CHN 0x03500000
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#define STM32_I2C1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6) |\
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STM32_DMA_STREAM_ID_MSK(2, 7))
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#define STM32_I2C1_TX_DMA_CHN 0x05300000
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#define STM32_HAS_I2C2 TRUE
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#define STM32_I2C2_EVENT_HANDLER VectorC4
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#define STM32_I2C2_EVENT_NUMBER 33
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#define STM32_I2C2_ERROR_HANDLER VectorC8
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#define STM32_I2C2_ERROR_NUMBER 34
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#define STM32_I2C2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5))
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#define STM32_I2C2_RX_DMA_CHN 0x00030000
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#define STM32_I2C2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4))
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#define STM32_I2C2_TX_DMA_CHN 0x00003000
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#define STM32_HAS_I2C3 TRUE
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#define STM32_I2C3_EVENT_HANDLER Vector160
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#define STM32_I2C3_EVENT_NUMBER 72
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#define STM32_I2C3_ERROR_HANDLER Vector164
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#define STM32_I2C3_ERROR_NUMBER 73
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#define STM32_I2C3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3))
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#define STM32_I2C3_RX_DMA_CHN 0x00000300
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#define STM32_I2C3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2))
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#define STM32_I2C3_TX_DMA_CHN 0x00000030
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#define STM32_HAS_I2C4 FALSE
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/* RTC attributes.*/
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#define STM32_HAS_RTC TRUE
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#define STM32_RTC_HAS_SUBSECONDS TRUE
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#define STM32_RTC_HAS_PERIODIC_WAKEUPS FALSE
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#define STM32_RTC_NUM_ALARMS 2
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#define STM32_RTC_HAS_INTERRUPTS FALSE
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/* SDMMC attributes.*/
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#define STM32_HAS_SDMMC1 TRUE
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#define STM32_SDMMC1_HANDLER Vector104
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#define STM32_SDMMC1_NUMBER 49
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#define STM32_SDC_SDMMC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 4) |\
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STM32_DMA_STREAM_ID_MSK(2, 5))
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#define STM32_SDC_SDMMC1_DMA_CHN 0x00077000
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/* SPI attributes.*/
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#define STM32_HAS_SPI1 TRUE
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#define STM32_SPI1_SUPPORTS_I2S FALSE
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#define STM32_SPI1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
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STM32_DMA_STREAM_ID_MSK(2, 3))
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#define STM32_SPI1_RX_DMA_CHN 0x00000410
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#define STM32_SPI1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) |\
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STM32_DMA_STREAM_ID_MSK(2, 4))
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#define STM32_SPI1_TX_DMA_CHN 0x00004100
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#define STM32_HAS_SPI2 TRUE
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#define STM32_SPI2_SUPPORTS_I2S FALSE
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#define STM32_SPI2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4))
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#define STM32_SPI2_RX_DMA_CHN 0x00001000
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#define STM32_SPI2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5))
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#define STM32_SPI2_TX_DMA_CHN 0x00010000
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#define STM32_HAS_SPI3 FALSE
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#define STM32_SPI3_SUPPORTS_I2S FALSE
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#define STM32_SPI3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 1))
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#define STM32_SPI3_RX_DMA_CHN 0x00000003
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#define STM32_SPI3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 2))
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#define STM32_SPI3_TX_DMA_CHN 0x00000030
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#define STM32_HAS_SPI4 FALSE
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#define STM32_HAS_SPI5 FALSE
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#define STM32_HAS_SPI6 FALSE
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/* TIM attributes.*/
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#define STM32_HAS_TIM1 TRUE
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#define STM32_TIM1_IS_32BITS FALSE
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#define STM32_TIM1_CHANNELS 4
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#define STM32_TIM1_UP_HANDLER VectorA4
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#define STM32_TIM1_CC_HANDLER VectorAC
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#define STM32_TIM1_UP_NUMBER 25
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#define STM32_TIM1_CC_NUMBER 27
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#define STM32_HAS_TIM2 TRUE
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#define STM32_TIM2_IS_32BITS TRUE
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#define STM32_TIM2_CHANNELS 4
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#define STM32_TIM2_HANDLER VectorB0
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#define STM32_TIM2_NUMBER 28
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#define STM32_HAS_TIM3 TRUE
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#define STM32_TIM3_IS_32BITS FALSE
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#define STM32_TIM3_CHANNELS 4
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#define STM32_TIM3_HANDLER VectorB4
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#define STM32_TIM3_NUMBER 29
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#define STM32_HAS_TIM4 TRUE
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#define STM32_TIM4_IS_32BITS FALSE
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#define STM32_TIM4_CHANNELS 4
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#define STM32_TIM4_HANDLER VectorB8
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#define STM32_TIM4_NUMBER 30
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#define STM32_HAS_TIM5 TRUE
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#define STM32_TIM5_IS_32BITS TRUE
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#define STM32_TIM5_CHANNELS 4
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#define STM32_TIM5_HANDLER Vector108
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#define STM32_TIM5_NUMBER 50
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#define STM32_HAS_TIM6 TRUE
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#define STM32_TIM6_IS_32BITS FALSE
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#define STM32_TIM6_CHANNELS 0
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#define STM32_TIM6_HANDLER Vector118
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#define STM32_TIM6_NUMBER 54
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#define STM32_HAS_TIM7 TRUE
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#define STM32_TIM7_IS_32BITS FALSE
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#define STM32_TIM7_CHANNELS 0
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#define STM32_TIM7_HANDLER Vector11C
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#define STM32_TIM7_NUMBER 55
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#define STM32_HAS_TIM8 TRUE
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#define STM32_TIM8_IS_32BITS FALSE
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#define STM32_TIM8_CHANNELS 6
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#define STM32_TIM8_UP_HANDLER VectorF0
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#define STM32_TIM8_CC_HANDLER VectorF8
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#define STM32_TIM8_UP_NUMBER 44
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#define STM32_TIM8_CC_NUMBER 46
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#define STM32_HAS_TIM15 TRUE
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#define STM32_TIM15_IS_32BITS FALSE
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#define STM32_TIM15_CHANNELS 2
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#define STM32_TIM15_HANDLER VectorA0
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#define STM32_TIM15_NUMBER 24
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#define STM32_HAS_TIM16 TRUE
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#define STM32_TIM16_IS_32BITS FALSE
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#define STM32_TIM16_CHANNELS 2
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#define STM32_TIM16_HANDLER VectorA4
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#define STM32_TIM16_NUMBER 25
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#define STM32_HAS_TIM17 TRUE
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#define STM32_TIM17_IS_32BITS FALSE
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#define STM32_TIM17_CHANNELS 2
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#define STM32_TIM17_HANDLER VectorA8
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#define STM32_TIM17_NUMBER 26
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#define STM32_HAS_TIM9 FALSE
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#define STM32_HAS_TIM10 FALSE
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#define STM32_HAS_TIM11 FALSE
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#define STM32_HAS_TIM12 FALSE
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#define STM32_HAS_TIM13 FALSE
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#define STM32_HAS_TIM14 FALSE
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#define STM32_HAS_TIM18 FALSE
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#define STM32_HAS_TIM19 FALSE
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#define STM32_HAS_TIM20 FALSE
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#define STM32_HAS_TIM21 FALSE
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#define STM32_HAS_TIM22 FALSE
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/* USART attributes.*/
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#define STM32_HAS_USART1 TRUE
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#define STM32_USART1_HANDLER VectorD4
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#define STM32_USART1_NUMBER 37
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#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5) |\
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STM32_DMA_STREAM_ID_MSK(2, 7))
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#define STM32_USART1_RX_DMA_CHN 0x02020000
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#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4) |\
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STM32_DMA_STREAM_ID_MSK(2, 6))
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#define STM32_USART1_TX_DMA_CHN 0x00202000
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#define STM32_HAS_USART2 TRUE
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#define STM32_USART2_HANDLER VectorD8
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#define STM32_USART2_NUMBER 38
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#define STM32_USART2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6))
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#define STM32_USART2_RX_DMA_CHN 0x00200000
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#define STM32_USART2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7))
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#define STM32_USART2_TX_DMA_CHN 0x02000000
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#define STM32_HAS_USART3 TRUE
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#define STM32_USART3_HANDLER VectorDC
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#define STM32_USART3_NUMBER 39
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#define STM32_USART3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3))
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#define STM32_USART3_RX_DMA_CHN 0x00000200
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#define STM32_USART3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2))
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#define STM32_USART3_TX_DMA_CHN 0x00000020
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#define STM32_HAS_UART4 TRUE
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#define STM32_UART4_HANDLER Vector110
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#define STM32_UART4_NUMBER 52
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#define STM32_UART4_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 5)
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#define STM32_UART4_RX_DMA_CHN 0x00020000
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#define STM32_UART4_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 3)
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#define STM32_UART4_TX_DMA_CHN 0x00000200
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#define STM32_HAS_UART5 TRUE
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#define STM32_UART5_HANDLER Vector114
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#define STM32_UART5_NUMBER 53
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#define STM32_UART5_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 2)
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#define STM32_UART5_RX_DMA_CHN 0x00000020
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#define STM32_UART5_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 1)
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#define STM32_UART5_TX_DMA_CHN 0x00000002
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#define STM32_HAS_LPUART1 TRUE
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#define STM32_LPUART1_HANDLER Vector158
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#define STM32_LPUART1_NUMBER 70
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#define STM32_HAS_USART6 FALSE
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#define STM32_HAS_UART7 FALSE
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#define STM32_HAS_UART8 FALSE
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/* USB attributes.*/
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#define STM32_HAS_USB FALSE
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#define STM32_HAS_OTG1 TRUE
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#define STM32_OTG1_HANDLER Vector14C
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#define STM32_OTG1_NUMBER 67
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#define STM32_HAS_OTG2 FALSE
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/* IWDG attributes.*/
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#define STM32_HAS_IWDG TRUE
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#define STM32_IWDG_IS_WINDOWED TRUE
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/* LTDC attributes.*/
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#define STM32_HAS_LTDC FALSE
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/* DMA2D attributes.*/
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#define STM32_HAS_DMA2D FALSE
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/* FSMC attributes.*/
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#define STM32_HAS_FSMC FALSE
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/* CRC attributes.*/
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#define STM32_HAS_CRC TRUE
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#define STM32_CRC_PROGRAMMABLE TRUE
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/** @} */
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#endif /* _STM32_REGISTRY_H_ */
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/** @} */
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