429 lines
14 KiB
C
429 lines
14 KiB
C
/*
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ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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/**
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* @file STM32/LLD/ADCv2/adc_lld.c
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* @brief STM32 ADC subsystem low level driver source.
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*
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* @addtogroup ADC
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* @{
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*/
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#include "hal.h"
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#if HAL_USE_ADC || defined(__DOXYGEN__)
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/*===========================================================================*/
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/* Driver local definitions. */
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/*===========================================================================*/
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#define ADC1_DMA_CHANNEL \
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STM32_DMA_GETCHANNEL(STM32_ADC_ADC1_DMA_STREAM, STM32_ADC1_DMA_CHN)
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#define ADC2_DMA_CHANNEL \
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STM32_DMA_GETCHANNEL(STM32_ADC_ADC2_DMA_STREAM, STM32_ADC2_DMA_CHN)
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#define ADC3_DMA_CHANNEL \
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STM32_DMA_GETCHANNEL(STM32_ADC_ADC3_DMA_STREAM, STM32_ADC3_DMA_CHN)
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/*===========================================================================*/
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/* Driver exported variables. */
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/*===========================================================================*/
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/** @brief ADC1 driver identifier.*/
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#if STM32_ADC_USE_ADC1 || defined(__DOXYGEN__)
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ADCDriver ADCD1;
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#endif
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/** @brief ADC2 driver identifier.*/
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#if STM32_ADC_USE_ADC2 || defined(__DOXYGEN__)
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ADCDriver ADCD2;
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#endif
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/** @brief ADC3 driver identifier.*/
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#if STM32_ADC_USE_ADC3 || defined(__DOXYGEN__)
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ADCDriver ADCD3;
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#endif
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/*===========================================================================*/
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/* Driver local variables and types. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver local functions. */
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/*===========================================================================*/
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/**
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* @brief ADC DMA ISR service routine.
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*
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* @param[in] adcp pointer to the @p ADCDriver object
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* @param[in] flags pre-shifted content of the ISR register
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*/
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static void adc_lld_serve_rx_interrupt(ADCDriver *adcp, uint32_t flags) {
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/* DMA errors handling.*/
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if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) {
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/* DMA, this could help only if the DMA tries to access an unmapped
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address space or violates alignment rules.*/
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_adc_isr_error_code(adcp, ADC_ERR_DMAFAILURE);
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}
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else {
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/* It is possible that the conversion group has already be reset by the
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ADC error handler, in this case this interrupt is spurious.*/
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if (adcp->grpp != NULL) {
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if ((flags & STM32_DMA_ISR_TCIF) != 0) {
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/* Transfer complete processing.*/
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_adc_isr_full_code(adcp);
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}
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else if ((flags & STM32_DMA_ISR_HTIF) != 0) {
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/* Half transfer processing.*/
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_adc_isr_half_code(adcp);
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}
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}
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}
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}
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/*===========================================================================*/
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/* Driver interrupt handlers. */
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/*===========================================================================*/
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#if STM32_ADC_USE_ADC1 || STM32_ADC_USE_ADC2 || STM32_ADC_USE_ADC3 || \
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defined(__DOXYGEN__)
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/**
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* @brief ADC interrupt handler.
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*
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* @isr
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*/
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OSAL_IRQ_HANDLER(STM32_ADC_HANDLER) {
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uint32_t sr;
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OSAL_IRQ_PROLOGUE();
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#if STM32_ADC_USE_ADC1
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sr = ADC1->SR;
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ADC1->SR = 0;
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/* Note, an overflow may occur after the conversion ended before the driver
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is able to stop the ADC, this is why the DMA channel is checked too.*/
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if ((sr & ADC_SR_OVR) && (dmaStreamGetTransactionSize(ADCD1.dmastp) > 0)) {
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/* ADC overflow condition, this could happen only if the DMA is unable
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to read data fast enough.*/
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if (ADCD1.grpp != NULL)
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_adc_isr_error_code(&ADCD1, ADC_ERR_OVERFLOW);
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}
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/* TODO: Add here analog watchdog handling.*/
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#endif /* STM32_ADC_USE_ADC1 */
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#if STM32_ADC_USE_ADC2
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sr = ADC2->SR;
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ADC2->SR = 0;
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/* Note, an overflow may occur after the conversion ended before the driver
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is able to stop the ADC, this is why the DMA channel is checked too.*/
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if ((sr & ADC_SR_OVR) && (dmaStreamGetTransactionSize(ADCD2.dmastp) > 0)) {
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/* ADC overflow condition, this could happen only if the DMA is unable
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to read data fast enough.*/
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if (ADCD2.grpp != NULL)
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_adc_isr_error_code(&ADCD2, ADC_ERR_OVERFLOW);
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}
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/* TODO: Add here analog watchdog handling.*/
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#endif /* STM32_ADC_USE_ADC2 */
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#if STM32_ADC_USE_ADC3
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sr = ADC3->SR;
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ADC3->SR = 0;
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/* Note, an overflow may occur after the conversion ended before the driver
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is able to stop the ADC, this is why the DMA channel is checked too.*/
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if ((sr & ADC_SR_OVR) && (dmaStreamGetTransactionSize(ADCD3.dmastp) > 0)) {
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/* ADC overflow condition, this could happen only if the DMA is unable
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to read data fast enough.*/
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if (ADCD3.grpp != NULL)
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_adc_isr_error_code(&ADCD3, ADC_ERR_OVERFLOW);
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}
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/* TODO: Add here analog watchdog handling.*/
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#endif /* STM32_ADC_USE_ADC3 */
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OSAL_IRQ_EPILOGUE();
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}
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#endif
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/*===========================================================================*/
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/* Driver exported functions. */
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/*===========================================================================*/
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/**
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* @brief Low level ADC driver initialization.
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*
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* @notapi
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*/
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void adc_lld_init(void) {
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#if STM32_ADC_USE_ADC1
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/* Driver initialization.*/
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adcObjectInit(&ADCD1);
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ADCD1.adc = ADC1;
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ADCD1.dmastp = STM32_DMA_STREAM(STM32_ADC_ADC1_DMA_STREAM);
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ADCD1.dmamode = STM32_DMA_CR_CHSEL(ADC1_DMA_CHANNEL) |
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STM32_DMA_CR_PL(STM32_ADC_ADC1_DMA_PRIORITY) |
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STM32_DMA_CR_DIR_P2M |
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STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD |
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STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE |
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STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
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#endif
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#if STM32_ADC_USE_ADC2
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/* Driver initialization.*/
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adcObjectInit(&ADCD2);
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ADCD2.adc = ADC2;
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ADCD2.dmastp = STM32_DMA_STREAM(STM32_ADC_ADC2_DMA_STREAM);
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ADCD2.dmamode = STM32_DMA_CR_CHSEL(ADC2_DMA_CHANNEL) |
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STM32_DMA_CR_PL(STM32_ADC_ADC2_DMA_PRIORITY) |
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STM32_DMA_CR_DIR_P2M |
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STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD |
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STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE |
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STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
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#endif
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#if STM32_ADC_USE_ADC3
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/* Driver initialization.*/
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adcObjectInit(&ADCD3);
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ADCD3.adc = ADC3;
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ADCD3.dmastp = STM32_DMA_STREAM(STM32_ADC_ADC3_DMA_STREAM);
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ADCD3.dmamode = STM32_DMA_CR_CHSEL(ADC3_DMA_CHANNEL) |
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STM32_DMA_CR_PL(STM32_ADC_ADC3_DMA_PRIORITY) |
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STM32_DMA_CR_DIR_P2M |
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STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD |
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STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE |
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STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
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#endif
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/* The shared vector is initialized on driver initialization and never
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disabled because sharing.*/
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nvicEnableVector(STM32_ADC_NUMBER, STM32_ADC_IRQ_PRIORITY);
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}
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/**
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* @brief Configures and activates the ADC peripheral.
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*
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* @param[in] adcp pointer to the @p ADCDriver object
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*
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* @notapi
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*/
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void adc_lld_start(ADCDriver *adcp) {
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/* If in stopped state then enables the ADC and DMA clocks.*/
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if (adcp->state == ADC_STOP) {
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#if STM32_ADC_USE_ADC1
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if (&ADCD1 == adcp) {
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bool b;
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b = dmaStreamAllocate(adcp->dmastp,
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STM32_ADC_ADC1_DMA_IRQ_PRIORITY,
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(stm32_dmaisr_t)adc_lld_serve_rx_interrupt,
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(void *)adcp);
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osalDbgAssert(!b, "stream already allocated");
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dmaStreamSetPeripheral(adcp->dmastp, &ADC1->DR);
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rccEnableADC1(FALSE);
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}
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#endif /* STM32_ADC_USE_ADC1 */
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#if STM32_ADC_USE_ADC2
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if (&ADCD2 == adcp) {
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bool b;
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b = dmaStreamAllocate(adcp->dmastp,
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STM32_ADC_ADC2_DMA_IRQ_PRIORITY,
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(stm32_dmaisr_t)adc_lld_serve_rx_interrupt,
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(void *)adcp);
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osalDbgAssert(!b, "stream already allocated");
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dmaStreamSetPeripheral(adcp->dmastp, &ADC2->DR);
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rccEnableADC2(FALSE);
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}
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#endif /* STM32_ADC_USE_ADC2 */
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#if STM32_ADC_USE_ADC3
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if (&ADCD3 == adcp) {
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bool b;
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b = dmaStreamAllocate(adcp->dmastp,
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STM32_ADC_ADC3_DMA_IRQ_PRIORITY,
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(stm32_dmaisr_t)adc_lld_serve_rx_interrupt,
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(void *)adcp);
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osalDbgAssert(!b, "stream already allocated");
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dmaStreamSetPeripheral(adcp->dmastp, &ADC3->DR);
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rccEnableADC3(FALSE);
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}
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#endif /* STM32_ADC_USE_ADC3 */
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/* This is a common register but apparently it requires that at least one
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of the ADCs is clocked in order to allow writing, see bug 3575297.*/
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ADC->CCR = (ADC->CCR & (ADC_CCR_TSVREFE | ADC_CCR_VBATE)) |
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(STM32_ADC_ADCPRE << 16);
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/* ADC initial setup, starting the analog part here in order to reduce
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the latency when starting a conversion.*/
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adcp->adc->CR1 = 0;
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adcp->adc->CR2 = 0;
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adcp->adc->CR2 = ADC_CR2_ADON;
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}
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}
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/**
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* @brief Deactivates the ADC peripheral.
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*
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* @param[in] adcp pointer to the @p ADCDriver object
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*
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* @notapi
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*/
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void adc_lld_stop(ADCDriver *adcp) {
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/* If in ready state then disables the ADC clock.*/
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if (adcp->state == ADC_READY) {
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dmaStreamRelease(adcp->dmastp);
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adcp->adc->CR1 = 0;
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adcp->adc->CR2 = 0;
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#if STM32_ADC_USE_ADC1
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if (&ADCD1 == adcp)
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rccDisableADC1(FALSE);
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#endif
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#if STM32_ADC_USE_ADC2
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if (&ADCD2 == adcp)
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rccDisableADC2(FALSE);
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#endif
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#if STM32_ADC_USE_ADC3
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if (&ADCD3 == adcp)
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rccDisableADC3(FALSE);
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#endif
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}
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}
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/**
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* @brief Starts an ADC conversion.
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*
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* @param[in] adcp pointer to the @p ADCDriver object
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*
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* @notapi
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*/
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void adc_lld_start_conversion(ADCDriver *adcp) {
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uint32_t mode;
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uint32_t cr2;
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const ADCConversionGroup *grpp = adcp->grpp;
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/* DMA setup.*/
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mode = adcp->dmamode;
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if (grpp->circular) {
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mode |= STM32_DMA_CR_CIRC;
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if (adcp->depth > 1) {
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/* If circular buffer depth > 1, then the half transfer interrupt
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is enabled in order to allow streaming processing.*/
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mode |= STM32_DMA_CR_HTIE;
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}
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}
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dmaStreamSetMemory0(adcp->dmastp, adcp->samples);
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dmaStreamSetTransactionSize(adcp->dmastp, (uint32_t)grpp->num_channels *
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(uint32_t)adcp->depth);
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dmaStreamSetMode(adcp->dmastp, mode);
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dmaStreamEnable(adcp->dmastp);
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/* ADC setup.*/
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adcp->adc->SR = 0;
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adcp->adc->SMPR1 = grpp->smpr1;
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adcp->adc->SMPR2 = grpp->smpr2;
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adcp->adc->SQR1 = grpp->sqr1;
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adcp->adc->SQR2 = grpp->sqr2;
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adcp->adc->SQR3 = grpp->sqr3;
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/* ADC configuration and start.*/
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adcp->adc->CR1 = grpp->cr1 | ADC_CR1_OVRIE | ADC_CR1_SCAN;
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/* Enforcing the mandatory bits in CR2.*/
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cr2 = grpp->cr2 | ADC_CR2_DMA | ADC_CR2_DDS | ADC_CR2_ADON;
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/* The start method is different dependign if HW or SW triggered, the
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start is performed using the method specified in the CR2 configuration.*/
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if ((cr2 & ADC_CR2_SWSTART) != 0) {
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/* Initializing CR2 while keeping ADC_CR2_SWSTART at zero.*/
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adcp->adc->CR2 = (cr2 | ADC_CR2_CONT) & ~ADC_CR2_SWSTART;
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/* Finally enabling ADC_CR2_SWSTART.*/
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adcp->adc->CR2 = (cr2 | ADC_CR2_CONT);
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}
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else
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adcp->adc->CR2 = cr2;
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}
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/**
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* @brief Stops an ongoing conversion.
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*
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* @param[in] adcp pointer to the @p ADCDriver object
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*
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* @notapi
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*/
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void adc_lld_stop_conversion(ADCDriver *adcp) {
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dmaStreamDisable(adcp->dmastp);
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adcp->adc->CR1 = 0;
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adcp->adc->CR2 = 0;
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adcp->adc->CR2 = ADC_CR2_ADON;
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}
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/**
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* @brief Enables the TSVREFE bit.
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* @details The TSVREFE bit is required in order to sample the internal
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* temperature sensor and internal reference voltage.
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* @note This is an STM32-only functionality.
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*/
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void adcSTM32EnableTSVREFE(void) {
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ADC->CCR |= ADC_CCR_TSVREFE;
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}
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/**
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* @brief Disables the TSVREFE bit.
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* @details The TSVREFE bit is required in order to sample the internal
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* temperature sensor and internal reference voltage.
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* @note This is an STM32-only functionality.
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*/
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void adcSTM32DisableTSVREFE(void) {
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ADC->CCR &= ~ADC_CCR_TSVREFE;
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}
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/**
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* @brief Enables the VBATE bit.
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* @details The VBATE bit is required in order to sample the VBAT channel.
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* @note This is an STM32-only functionality.
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* @note This function is meant to be called after @p adcStart().
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*/
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void adcSTM32EnableVBATE(void) {
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ADC->CCR |= ADC_CCR_VBATE;
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}
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/**
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* @brief Disables the VBATE bit.
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* @details The VBATE bit is required in order to sample the VBAT channel.
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* @note This is an STM32-only functionality.
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* @note This function is meant to be called after @p adcStart().
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*/
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void adcSTM32DisableVBATE(void) {
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ADC->CCR &= ~ADC_CCR_VBATE;
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}
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#endif /* HAL_USE_ADC */
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/** @} */
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