595 lines
19 KiB
C
595 lines
19 KiB
C
/*
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ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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/**
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* @file STM32/USARTv2/uart_lld.c
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* @brief STM32 low level UART driver code.
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*
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* @addtogroup UART
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* @{
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*/
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#include "ch.h"
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#include "hal.h"
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#if HAL_USE_UART || defined(__DOXYGEN__)
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/*===========================================================================*/
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/* Driver local definitions. */
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/*===========================================================================*/
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#define USART1_RX_DMA_CHANNEL \
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STM32_DMA_GETCHANNEL(STM32_UART_USART1_RX_DMA_STREAM, \
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STM32_USART1_RX_DMA_CHN)
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#define USART1_TX_DMA_CHANNEL \
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STM32_DMA_GETCHANNEL(STM32_UART_USART1_TX_DMA_STREAM, \
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STM32_USART1_TX_DMA_CHN)
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#define USART2_RX_DMA_CHANNEL \
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STM32_DMA_GETCHANNEL(STM32_UART_USART2_RX_DMA_STREAM, \
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STM32_USART2_RX_DMA_CHN)
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#define USART2_TX_DMA_CHANNEL \
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STM32_DMA_GETCHANNEL(STM32_UART_USART2_TX_DMA_STREAM, \
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STM32_USART2_TX_DMA_CHN)
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#define USART3_RX_DMA_CHANNEL \
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STM32_DMA_GETCHANNEL(STM32_UART_USART3_RX_DMA_STREAM, \
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STM32_USART3_RX_DMA_CHN)
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#define USART3_TX_DMA_CHANNEL \
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STM32_DMA_GETCHANNEL(STM32_UART_USART3_TX_DMA_STREAM, \
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STM32_USART3_TX_DMA_CHN)
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/*===========================================================================*/
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/* Driver exported variables. */
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/*===========================================================================*/
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/** @brief USART1 UART driver identifier.*/
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#if STM32_UART_USE_USART1 || defined(__DOXYGEN__)
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UARTDriver UARTD1;
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#endif
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/** @brief USART2 UART driver identifier.*/
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#if STM32_UART_USE_USART2 || defined(__DOXYGEN__)
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UARTDriver UARTD2;
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#endif
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/** @brief USART3 UART driver identifier.*/
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#if STM32_UART_USE_USART3 || defined(__DOXYGEN__)
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UARTDriver UARTD3;
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#endif
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/*===========================================================================*/
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/* Driver local variables and types. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver local functions. */
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/*===========================================================================*/
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/**
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* @brief Status bits translation.
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*
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* @param[in] sr USART SR register value
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*
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* @return The error flags.
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*/
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static uartflags_t translate_errors(uint32_t isr) {
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uartflags_t sts = 0;
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if (isr & USART_ISR_ORE)
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sts |= UART_OVERRUN_ERROR;
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if (isr & USART_ISR_PE)
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sts |= UART_PARITY_ERROR;
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if (isr & USART_ISR_FE)
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sts |= UART_FRAMING_ERROR;
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if (isr & USART_ISR_NE)
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sts |= UART_NOISE_ERROR;
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if (isr & USART_ISR_LBD)
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sts |= UART_BREAK_DETECTED;
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return sts;
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}
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/**
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* @brief Puts the receiver in the UART_RX_IDLE state.
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*
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* @param[in] uartp pointer to the @p UARTDriver object
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*/
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static void set_rx_idle_loop(UARTDriver *uartp) {
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uint32_t mode;
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/* RX DMA channel preparation, if the char callback is defined then the
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TCIE interrupt is enabled too.*/
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if (uartp->config->rxchar_cb == NULL)
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mode = STM32_DMA_CR_DIR_P2M | STM32_DMA_CR_CIRC;
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else
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mode = STM32_DMA_CR_DIR_P2M | STM32_DMA_CR_CIRC | STM32_DMA_CR_TCIE;
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dmaStreamSetMemory0(uartp->dmarx, &uartp->rxbuf);
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dmaStreamSetTransactionSize(uartp->dmarx, 1);
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dmaStreamSetMode(uartp->dmarx, uartp->dmamode | mode);
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dmaStreamEnable(uartp->dmarx);
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}
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/**
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* @brief USART de-initialization.
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* @details This function must be invoked with interrupts disabled.
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*
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* @param[in] uartp pointer to the @p UARTDriver object
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*/
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static void usart_stop(UARTDriver *uartp) {
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/* Stops RX and TX DMA channels.*/
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dmaStreamDisable(uartp->dmarx);
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dmaStreamDisable(uartp->dmatx);
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/* Stops USART operations.*/
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uartp->usart->CR1 = 0;
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uartp->usart->CR2 = 0;
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uartp->usart->CR3 = 0;
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}
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/**
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* @brief USART initialization.
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* @details This function must be invoked with interrupts disabled.
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*
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* @param[in] uartp pointer to the @p UARTDriver object
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*/
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static void usart_start(UARTDriver *uartp) {
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uint32_t cr1;
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USART_TypeDef *u = uartp->usart;
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/* Defensive programming, starting from a clean state.*/
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usart_stop(uartp);
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/* Baud rate setting.*/
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#if defined(STM32F0XX)
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if (uartp->usart == USART1)
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u->BRR = STM32_USART1CLK / uartp->config->speed;
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else
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u->BRR = STM32_PCLK / uartp->config->speed;
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#else /* !defined(STM32F0XX) */
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if (uartp->usart == USART1)
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u->BRR = STM32_PCLK2 / uartp->config->speed;
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else
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u->BRR = STM32_PCLK1 / uartp->config->speed;
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#endif /* !defined(STM32F0XX) */
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/* Resetting eventual pending status flags.*/
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u->ICR = 0xFFFFFFFF;
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/* Note that some bits are enforced because required for correct driver
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operations.*/
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u->CR2 = uartp->config->cr2 | USART_CR2_LBDIE;
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u->CR3 = uartp->config->cr3 | USART_CR3_DMAT | USART_CR3_DMAR |
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USART_CR3_EIE;
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if (uartp->config->txend2_cb == NULL)
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cr1 = USART_CR1_UE | USART_CR1_PEIE | USART_CR1_TE | USART_CR1_RE;
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else
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cr1 = USART_CR1_UE | USART_CR1_PEIE | USART_CR1_TE | USART_CR1_RE |
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USART_CR1_TCIE;
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u->CR1 = uartp->config->cr1 | cr1;
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/* Starting the receiver idle loop.*/
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set_rx_idle_loop(uartp);
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}
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/**
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* @brief RX DMA common service routine.
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*
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* @param[in] uartp pointer to the @p UARTDriver object
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* @param[in] flags pre-shifted content of the ISR register
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*/
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static void uart_lld_serve_rx_end_irq(UARTDriver *uartp, uint32_t flags) {
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/* DMA errors handling.*/
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#if defined(STM32_UART_DMA_ERROR_HOOK)
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if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) {
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STM32_UART_DMA_ERROR_HOOK(uartp);
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}
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#else
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(void)flags;
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#endif
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if (uartp->rxstate == UART_RX_IDLE) {
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/* Receiver in idle state, a callback is generated, if enabled, for each
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received character and then the driver stays in the same state.*/
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if (uartp->config->rxchar_cb != NULL)
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uartp->config->rxchar_cb(uartp, uartp->rxbuf);
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}
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else {
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/* Receiver in active state, a callback is generated, if enabled, after
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a completed transfer.*/
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dmaStreamDisable(uartp->dmarx);
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uartp->rxstate = UART_RX_COMPLETE;
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if (uartp->config->rxend_cb != NULL)
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uartp->config->rxend_cb(uartp);
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/* If the callback didn't explicitly change state then the receiver
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automatically returns to the idle state.*/
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if (uartp->rxstate == UART_RX_COMPLETE) {
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uartp->rxstate = UART_RX_IDLE;
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set_rx_idle_loop(uartp);
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}
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}
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}
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/**
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* @brief TX DMA common service routine.
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*
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* @param[in] uartp pointer to the @p UARTDriver object
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* @param[in] flags pre-shifted content of the ISR register
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*/
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static void uart_lld_serve_tx_end_irq(UARTDriver *uartp, uint32_t flags) {
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/* DMA errors handling.*/
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#if defined(STM32_UART_DMA_ERROR_HOOK)
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if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) {
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STM32_UART_DMA_ERROR_HOOK(uartp);
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}
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#else
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(void)flags;
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#endif
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dmaStreamDisable(uartp->dmatx);
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/* A callback is generated, if enabled, after a completed transfer.*/
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uartp->txstate = UART_TX_COMPLETE;
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if (uartp->config->txend1_cb != NULL)
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uartp->config->txend1_cb(uartp);
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/* If the callback didn't explicitly change state then the transmitter
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automatically returns to the idle state.*/
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if (uartp->txstate == UART_TX_COMPLETE)
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uartp->txstate = UART_TX_IDLE;
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}
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/**
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* @brief USART common service routine.
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*
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* @param[in] uartp pointer to the @p UARTDriver object
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*/
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static void serve_usart_irq(UARTDriver *uartp) {
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uint32_t isr;
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USART_TypeDef *u = uartp->usart;
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/* Reading and clearing status.*/
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isr = u->ISR;
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u->ICR = isr;
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if (isr & (USART_ISR_LBD | USART_ISR_ORE | USART_ISR_NE |
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USART_ISR_FE | USART_ISR_PE)) {
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if (uartp->config->rxerr_cb != NULL)
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uartp->config->rxerr_cb(uartp, translate_errors(isr));
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}
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if (isr & USART_ISR_TC) {
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/* End of transmission, a callback is generated.*/
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if (uartp->config->txend2_cb != NULL)
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uartp->config->txend2_cb(uartp);
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}
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}
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/*===========================================================================*/
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/* Driver interrupt handlers. */
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/*===========================================================================*/
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#if STM32_UART_USE_USART1 || defined(__DOXYGEN__)
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#if !defined(STM32_USART1_HANDLER)
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#error "STM32_USART1_HANDLER not defined"
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#endif
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/**
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* @brief USART1 IRQ handler.
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*
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* @isr
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*/
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CH_IRQ_HANDLER(STM32_USART1_HANDLER) {
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CH_IRQ_PROLOGUE();
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serve_usart_irq(&UARTD1);
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CH_IRQ_EPILOGUE();
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}
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#endif /* STM32_UART_USE_USART1 */
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#if STM32_UART_USE_USART2 || defined(__DOXYGEN__)
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#if !defined(STM32_USART2_HANDLER)
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#error "STM32_USART2_HANDLER not defined"
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#endif
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/**
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* @brief USART2 IRQ handler.
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*
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* @isr
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*/
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CH_IRQ_HANDLER(STM32_USART2_HANDLER) {
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CH_IRQ_PROLOGUE();
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serve_usart_irq(&UARTD2);
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CH_IRQ_EPILOGUE();
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}
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#endif /* STM32_UART_USE_USART2 */
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#if STM32_UART_USE_USART3 || defined(__DOXYGEN__)
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#if !defined(STM32_USART3_HANDLER)
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#error "STM32_USART3_HANDLER not defined"
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#endif
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/**
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* @brief USART3 IRQ handler.
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*
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* @isr
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*/
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CH_IRQ_HANDLER(STM32_USART3_HANDLER) {
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CH_IRQ_PROLOGUE();
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serve_usart_irq(&UARTD3);
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CH_IRQ_EPILOGUE();
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}
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#endif /* STM32_UART_USE_USART3 */
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/*===========================================================================*/
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/* Driver exported functions. */
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/*===========================================================================*/
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/**
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* @brief Low level UART driver initialization.
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*
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* @notapi
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*/
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void uart_lld_init(void) {
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#if STM32_UART_USE_USART1
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uartObjectInit(&UARTD1);
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UARTD1.usart = USART1;
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UARTD1.dmamode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
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UARTD1.dmarx = STM32_DMA_STREAM(STM32_UART_USART1_RX_DMA_STREAM);
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UARTD1.dmatx = STM32_DMA_STREAM(STM32_UART_USART1_TX_DMA_STREAM);
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#endif
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#if STM32_UART_USE_USART2
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uartObjectInit(&UARTD2);
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UARTD2.usart = USART2;
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UARTD2.dmamode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
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UARTD2.dmarx = STM32_DMA_STREAM(STM32_UART_USART2_RX_DMA_STREAM);
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UARTD2.dmatx = STM32_DMA_STREAM(STM32_UART_USART2_TX_DMA_STREAM);
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#endif
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#if STM32_UART_USE_USART3
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uartObjectInit(&UARTD3);
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UARTD3.usart = USART3;
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UARTD3.dmamode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
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UARTD3.dmarx = STM32_DMA_STREAM(STM32_UART_USART3_RX_DMA_STREAM);
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UARTD3.dmatx = STM32_DMA_STREAM(STM32_UART_USART3_TX_DMA_STREAM);
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#endif
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}
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/**
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* @brief Configures and activates the UART peripheral.
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*
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* @param[in] uartp pointer to the @p UARTDriver object
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*
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* @notapi
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*/
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void uart_lld_start(UARTDriver *uartp) {
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if (uartp->state == UART_STOP) {
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#if STM32_UART_USE_USART1
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if (&UARTD1 == uartp) {
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bool_t b;
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b = dmaStreamAllocate(uartp->dmarx,
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STM32_UART_USART1_IRQ_PRIORITY,
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(stm32_dmaisr_t)uart_lld_serve_rx_end_irq,
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(void *)uartp);
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chDbgAssert(!b, "uart_lld_start(), #1", "stream already allocated");
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b = dmaStreamAllocate(uartp->dmatx,
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STM32_UART_USART1_IRQ_PRIORITY,
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(stm32_dmaisr_t)uart_lld_serve_tx_end_irq,
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(void *)uartp);
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chDbgAssert(!b, "uart_lld_start(), #2", "stream already allocated");
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rccEnableUSART1(FALSE);
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nvicEnableVector(STM32_USART1_NUMBER,
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CORTEX_PRIORITY_MASK(STM32_UART_USART1_IRQ_PRIORITY));
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uartp->dmamode |= STM32_DMA_CR_CHSEL(USART1_RX_DMA_CHANNEL) |
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STM32_DMA_CR_PL(STM32_UART_USART1_DMA_PRIORITY);
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}
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#endif
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#if STM32_UART_USE_USART2
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if (&UARTD2 == uartp) {
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bool_t b;
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b = dmaStreamAllocate(uartp->dmarx,
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STM32_UART_USART2_IRQ_PRIORITY,
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(stm32_dmaisr_t)uart_lld_serve_rx_end_irq,
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(void *)uartp);
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chDbgAssert(!b, "uart_lld_start(), #3", "stream already allocated");
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b = dmaStreamAllocate(uartp->dmatx,
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STM32_UART_USART2_IRQ_PRIORITY,
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(stm32_dmaisr_t)uart_lld_serve_tx_end_irq,
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(void *)uartp);
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chDbgAssert(!b, "uart_lld_start(), #4", "stream already allocated");
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rccEnableUSART2(FALSE);
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nvicEnableVector(STM32_USART2_NUMBER,
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CORTEX_PRIORITY_MASK(STM32_UART_USART2_IRQ_PRIORITY));
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uartp->dmamode |= STM32_DMA_CR_CHSEL(USART2_RX_DMA_CHANNEL) |
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STM32_DMA_CR_PL(STM32_UART_USART2_DMA_PRIORITY);
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}
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#endif
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#if STM32_UART_USE_USART3
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if (&UARTD3 == uartp) {
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bool_t b;
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b = dmaStreamAllocate(uartp->dmarx,
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STM32_UART_USART3_IRQ_PRIORITY,
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(stm32_dmaisr_t)uart_lld_serve_rx_end_irq,
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(void *)uartp);
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chDbgAssert(!b, "uart_lld_start(), #5", "stream already allocated");
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b = dmaStreamAllocate(uartp->dmatx,
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STM32_UART_USART3_IRQ_PRIORITY,
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(stm32_dmaisr_t)uart_lld_serve_tx_end_irq,
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(void *)uartp);
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chDbgAssert(!b, "uart_lld_start(), #6", "stream already allocated");
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rccEnableUSART3(FALSE);
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nvicEnableVector(STM32_USART3_NUMBER,
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CORTEX_PRIORITY_MASK(STM32_UART_USART3_IRQ_PRIORITY));
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uartp->dmamode |= STM32_DMA_CR_CHSEL(USART3_RX_DMA_CHANNEL) |
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STM32_DMA_CR_PL(STM32_UART_USART3_DMA_PRIORITY);
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}
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#endif
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/* Static DMA setup, the transfer size depends on the USART settings,
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it is 16 bits if M=1 and PCE=0 else it is 8 bits.*/
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if ((uartp->config->cr1 & (USART_CR1_M | USART_CR1_PCE)) == USART_CR1_M)
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uartp->dmamode |= STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD;
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dmaStreamSetPeripheral(uartp->dmarx, &uartp->usart->RDR);
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dmaStreamSetPeripheral(uartp->dmatx, &uartp->usart->TDR);
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uartp->rxbuf = 0;
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}
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uartp->rxstate = UART_RX_IDLE;
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uartp->txstate = UART_TX_IDLE;
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usart_start(uartp);
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}
|
|
|
|
/**
|
|
* @brief Deactivates the UART peripheral.
|
|
*
|
|
* @param[in] uartp pointer to the @p UARTDriver object
|
|
*
|
|
* @notapi
|
|
*/
|
|
void uart_lld_stop(UARTDriver *uartp) {
|
|
|
|
if (uartp->state == UART_READY) {
|
|
usart_stop(uartp);
|
|
dmaStreamRelease(uartp->dmarx);
|
|
dmaStreamRelease(uartp->dmatx);
|
|
|
|
#if STM32_UART_USE_USART1
|
|
if (&UARTD1 == uartp) {
|
|
nvicDisableVector(STM32_USART1_NUMBER);
|
|
rccDisableUSART1(FALSE);
|
|
return;
|
|
}
|
|
#endif
|
|
|
|
#if STM32_UART_USE_USART2
|
|
if (&UARTD2 == uartp) {
|
|
nvicDisableVector(STM32_USART2_NUMBER);
|
|
rccDisableUSART2(FALSE);
|
|
return;
|
|
}
|
|
#endif
|
|
|
|
#if STM32_UART_USE_USART3
|
|
if (&UARTD3 == uartp) {
|
|
nvicDisableVector(STM32_USART3_NUMBER);
|
|
rccDisableUSART3(FALSE);
|
|
return;
|
|
}
|
|
#endif
|
|
}
|
|
}
|
|
|
|
/**
|
|
* @brief Starts a transmission on the UART peripheral.
|
|
* @note The buffers are organized as uint8_t arrays for data sizes below
|
|
* or equal to 8 bits else it is organized as uint16_t arrays.
|
|
*
|
|
* @param[in] uartp pointer to the @p UARTDriver object
|
|
* @param[in] n number of data frames to send
|
|
* @param[in] txbuf the pointer to the transmit buffer
|
|
*
|
|
* @notapi
|
|
*/
|
|
void uart_lld_start_send(UARTDriver *uartp, size_t n, const void *txbuf) {
|
|
|
|
/* TX DMA channel preparation and start.*/
|
|
dmaStreamSetMemory0(uartp->dmatx, txbuf);
|
|
dmaStreamSetTransactionSize(uartp->dmatx, n);
|
|
dmaStreamSetMode(uartp->dmatx, uartp->dmamode | STM32_DMA_CR_DIR_M2P |
|
|
STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE);
|
|
dmaStreamEnable(uartp->dmatx);
|
|
}
|
|
|
|
/**
|
|
* @brief Stops any ongoing transmission.
|
|
* @note Stopping a transmission also suppresses the transmission callbacks.
|
|
*
|
|
* @param[in] uartp pointer to the @p UARTDriver object
|
|
*
|
|
* @return The number of data frames not transmitted by the
|
|
* stopped transmit operation.
|
|
*
|
|
* @notapi
|
|
*/
|
|
size_t uart_lld_stop_send(UARTDriver *uartp) {
|
|
|
|
dmaStreamDisable(uartp->dmatx);
|
|
return dmaStreamGetTransactionSize(uartp->dmatx);
|
|
}
|
|
|
|
/**
|
|
* @brief Starts a receive operation on the UART peripheral.
|
|
* @note The buffers are organized as uint8_t arrays for data sizes below
|
|
* or equal to 8 bits else it is organized as uint16_t arrays.
|
|
*
|
|
* @param[in] uartp pointer to the @p UARTDriver object
|
|
* @param[in] n number of data frames to send
|
|
* @param[out] rxbuf the pointer to the receive buffer
|
|
*
|
|
* @notapi
|
|
*/
|
|
void uart_lld_start_receive(UARTDriver *uartp, size_t n, void *rxbuf) {
|
|
|
|
/* Stopping previous activity (idle state).*/
|
|
dmaStreamDisable(uartp->dmarx);
|
|
|
|
/* RX DMA channel preparation and start.*/
|
|
dmaStreamSetMemory0(uartp->dmarx, rxbuf);
|
|
dmaStreamSetTransactionSize(uartp->dmarx, n);
|
|
dmaStreamSetMode(uartp->dmarx, uartp->dmamode | STM32_DMA_CR_DIR_P2M |
|
|
STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE);
|
|
dmaStreamEnable(uartp->dmarx);
|
|
}
|
|
|
|
/**
|
|
* @brief Stops any ongoing receive operation.
|
|
* @note Stopping a receive operation also suppresses the receive callbacks.
|
|
*
|
|
* @param[in] uartp pointer to the @p UARTDriver object
|
|
*
|
|
* @return The number of data frames not received by the
|
|
* stopped receive operation.
|
|
*
|
|
* @notapi
|
|
*/
|
|
size_t uart_lld_stop_receive(UARTDriver *uartp) {
|
|
size_t n;
|
|
|
|
dmaStreamDisable(uartp->dmarx);
|
|
n = dmaStreamGetTransactionSize(uartp->dmarx);
|
|
set_rx_idle_loop(uartp);
|
|
return n;
|
|
}
|
|
|
|
#endif /* HAL_USE_UART */
|
|
|
|
/** @} */
|