335 lines
10 KiB
C
335 lines
10 KiB
C
/*
|
|
ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
|
|
|
|
Licensed under the Apache License, Version 2.0 (the "License");
|
|
you may not use this file except in compliance with the License.
|
|
You may obtain a copy of the License at
|
|
|
|
http://www.apache.org/licenses/LICENSE-2.0
|
|
|
|
Unless required by applicable law or agreed to in writing, software
|
|
distributed under the License is distributed on an "AS IS" BASIS,
|
|
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
See the License for the specific language governing permissions and
|
|
limitations under the License.
|
|
*/
|
|
/*
|
|
Concepts and parts of this file have been contributed by Uladzimir Pylinsky
|
|
aka barthess.
|
|
*/
|
|
|
|
/**
|
|
* @file STM32/I2Cv2/i2c_lld.h
|
|
* @brief STM32 I2C subsystem low level driver header.
|
|
*
|
|
* @addtogroup I2C
|
|
* @{
|
|
*/
|
|
|
|
#ifndef _I2C_LLD_H_
|
|
#define _I2C_LLD_H_
|
|
|
|
#if HAL_USE_I2C || defined(__DOXYGEN__)
|
|
|
|
/*===========================================================================*/
|
|
/* Driver constants. */
|
|
/*===========================================================================*/
|
|
|
|
/**
|
|
* @name TIMINGR register definitions
|
|
* @{
|
|
*/
|
|
#define STM32_TIMINGR_PRESC_MASK (15U << 28)
|
|
#define STM32_TIMINGR_PRESC(n) ((n) << 28)
|
|
#define STM32_TIMINGR_SCLDEL_MASK (15U << 20)
|
|
#define STM32_TIMINGR_SCLDEL(n) ((n) << 20)
|
|
#define STM32_TIMINGR_SDADEL_MASK (15U << 16)
|
|
#define STM32_TIMINGR_SDADEL(n) ((n) << 16)
|
|
#define STM32_TIMINGR_SCLH_MASK (255U << 8)
|
|
#define STM32_TIMINGR_SCLH(n) ((n) << 8)
|
|
#define STM32_TIMINGR_SCLL_MASK (255U << 0)
|
|
#define STM32_TIMINGR_SCLL(n) ((n) << 0)
|
|
/** @} */
|
|
|
|
/*===========================================================================*/
|
|
/* Driver pre-compile time settings. */
|
|
/*===========================================================================*/
|
|
|
|
/**
|
|
* @name Configuration options
|
|
* @{
|
|
*/
|
|
/**
|
|
* @brief I2C1 driver enable switch.
|
|
* @details If set to @p TRUE the support for I2C1 is included.
|
|
* @note The default is @p FALSE.
|
|
*/
|
|
#if !defined(STM32_I2C_USE_I2C1) || defined(__DOXYGEN__)
|
|
#define STM32_I2C_USE_I2C1 FALSE
|
|
#endif
|
|
|
|
/**
|
|
* @brief I2C2 driver enable switch.
|
|
* @details If set to @p TRUE the support for I2C2 is included.
|
|
* @note The default is @p FALSE.
|
|
*/
|
|
#if !defined(STM32_I2C_USE_I2C2) || defined(__DOXYGEN__)
|
|
#define STM32_I2C_USE_I2C2 FALSE
|
|
#endif
|
|
|
|
/**
|
|
* @brief I2C1 interrupt priority level setting.
|
|
*/
|
|
#if !defined(STM32_I2C_I2C1_IRQ_PRIORITY) || defined(__DOXYGEN__)
|
|
#define STM32_I2C_I2C1_IRQ_PRIORITY 10
|
|
#endif
|
|
|
|
/**
|
|
* @brief I2C2 interrupt priority level setting.
|
|
*/
|
|
#if !defined(STM32_I2C_I2C2_IRQ_PRIORITY) || defined(__DOXYGEN__)
|
|
#define STM32_I2C_I2C2_IRQ_PRIORITY 10
|
|
#endif
|
|
|
|
/**
|
|
* @brief I2C1 DMA priority (0..3|lowest..highest).
|
|
* @note The priority level is used for both the TX and RX DMA streams but
|
|
* because of the streams ordering the RX stream has always priority
|
|
* over the TX stream.
|
|
*/
|
|
#if !defined(STM32_I2C_I2C1_DMA_PRIORITY) || defined(__DOXYGEN__)
|
|
#define STM32_I2C_I2C1_DMA_PRIORITY 1
|
|
#endif
|
|
|
|
/**
|
|
* @brief I2C2 DMA priority (0..3|lowest..highest).
|
|
* @note The priority level is used for both the TX and RX DMA streams but
|
|
* because of the streams ordering the RX stream has always priority
|
|
* over the TX stream.
|
|
*/
|
|
#if !defined(STM32_I2C_I2C2_DMA_PRIORITY) || defined(__DOXYGEN__)
|
|
#define STM32_I2C_I2C2_DMA_PRIORITY 1
|
|
#endif
|
|
|
|
/**
|
|
* @brief I2C DMA error hook.
|
|
* @note The default action for DMA errors is a system halt because DMA
|
|
* error can only happen because programming errors.
|
|
*/
|
|
#if !defined(STM32_I2C_DMA_ERROR_HOOK) || defined(__DOXYGEN__)
|
|
#define STM32_I2C_DMA_ERROR_HOOK(i2cp) chSysHalt()
|
|
#endif
|
|
/** @} */
|
|
|
|
/*===========================================================================*/
|
|
/* Derived constants and error checks. */
|
|
/*===========================================================================*/
|
|
|
|
/* Streams for the DMA peripheral.*/
|
|
#if defined(STM32F0XX)
|
|
#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
|
|
#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
|
|
#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
|
|
#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
|
|
|
|
#elif defined(STM32F30X) || defined(STM32F37X)
|
|
#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
|
|
#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
|
|
#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
|
|
#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
|
|
|
|
#else
|
|
#error "device unsupported by I2Cv2 driver"
|
|
#endif
|
|
|
|
/** @brief error checks */
|
|
#if STM32_I2C_USE_I2C1 && !STM32_HAS_I2C1
|
|
#error "I2C1 not present in the selected device"
|
|
#endif
|
|
|
|
#if STM32_I2C_USE_I2C2 && !STM32_HAS_I2C2
|
|
#error "I2C2 not present in the selected device"
|
|
#endif
|
|
|
|
#if !STM32_I2C_USE_I2C1 && !STM32_I2C_USE_I2C2
|
|
#error "I2C driver activated but no I2C peripheral assigned"
|
|
#endif
|
|
|
|
#if STM32_I2C_USE_I2C1 && \
|
|
!STM32_DMA_IS_VALID_ID(STM32_I2C_I2C1_RX_DMA_STREAM, \
|
|
STM32_I2C1_RX_DMA_MSK)
|
|
#error "invalid DMA stream associated to I2C1 RX"
|
|
#endif
|
|
|
|
#if STM32_I2C_USE_I2C1 && \
|
|
!STM32_DMA_IS_VALID_ID(STM32_I2C_I2C1_TX_DMA_STREAM, \
|
|
STM32_I2C1_TX_DMA_MSK)
|
|
#error "invalid DMA stream associated to I2C1 TX"
|
|
#endif
|
|
|
|
#if STM32_I2C_USE_I2C2 && \
|
|
!STM32_DMA_IS_VALID_ID(STM32_I2C_I2C2_RX_DMA_STREAM, \
|
|
STM32_I2C2_RX_DMA_MSK)
|
|
#error "invalid DMA stream associated to I2C2 RX"
|
|
#endif
|
|
|
|
#if STM32_I2C_USE_I2C2 && \
|
|
!STM32_DMA_IS_VALID_ID(STM32_I2C_I2C2_TX_DMA_STREAM, \
|
|
STM32_I2C2_TX_DMA_MSK)
|
|
#error "invalid DMA stream associated to I2C2 TX"
|
|
#endif
|
|
|
|
#if !defined(STM32_DMA_REQUIRED)
|
|
#define STM32_DMA_REQUIRED
|
|
#endif
|
|
|
|
/* Check clock range. */
|
|
|
|
/*===========================================================================*/
|
|
/* Driver data structures and types. */
|
|
/*===========================================================================*/
|
|
|
|
/**
|
|
* @brief Type representing I2C address.
|
|
*/
|
|
typedef uint16_t i2caddr_t;
|
|
|
|
/**
|
|
* @brief I2C Driver condition flags type.
|
|
*/
|
|
typedef uint32_t i2cflags_t;
|
|
|
|
/**
|
|
* @brief Driver configuration structure.
|
|
*/
|
|
typedef struct {
|
|
/**
|
|
* @brief TIMINGR register initialization.
|
|
* @note Refer to the STM32 reference manual, the values are affected
|
|
* by the system clock settings in mcuconf.h.
|
|
*/
|
|
uint32_t timingr;
|
|
/**
|
|
* @brief CR1 register initialization.
|
|
* @note Leave to zero unless you know what you are doing.
|
|
*/
|
|
uint32_t cr1;
|
|
/**
|
|
* @brief CR2 register initialization.
|
|
* @note Only the ADD10 bit can eventually be specified here.
|
|
*/
|
|
uint32_t cr2;
|
|
} I2CConfig;
|
|
|
|
/**
|
|
* @brief Type of a structure representing an I2C driver.
|
|
*/
|
|
typedef struct I2CDriver I2CDriver;
|
|
|
|
/**
|
|
* @brief Structure representing an I2C driver.
|
|
*/
|
|
struct I2CDriver{
|
|
/**
|
|
* @brief Driver state.
|
|
*/
|
|
i2cstate_t state;
|
|
/**
|
|
* @brief Current configuration data.
|
|
*/
|
|
const I2CConfig *config;
|
|
/**
|
|
* @brief Error flags.
|
|
*/
|
|
i2cflags_t errors;
|
|
#if I2C_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__)
|
|
#if CH_USE_MUTEXES || defined(__DOXYGEN__)
|
|
/**
|
|
* @brief Mutex protecting the bus.
|
|
*/
|
|
Mutex mutex;
|
|
#elif CH_USE_SEMAPHORES
|
|
Semaphore semaphore;
|
|
#endif
|
|
#endif /* I2C_USE_MUTUAL_EXCLUSION */
|
|
#if defined(I2C_DRIVER_EXT_FIELDS)
|
|
I2C_DRIVER_EXT_FIELDS
|
|
#endif
|
|
/* End of the mandatory fields.*/
|
|
/**
|
|
* @brief Thread waiting for I/O completion.
|
|
*/
|
|
Thread *thread;
|
|
/**
|
|
* @brief Current slave address without R/W bit.
|
|
*/
|
|
i2caddr_t addr;
|
|
/**
|
|
* @brief DMA mode bit mask.
|
|
*/
|
|
uint32_t dmamode;
|
|
/**
|
|
* @brief Receive DMA channel.
|
|
*/
|
|
const stm32_dma_stream_t *dmarx;
|
|
/**
|
|
* @brief Transmit DMA channel.
|
|
*/
|
|
const stm32_dma_stream_t *dmatx;
|
|
/**
|
|
* @brief Pointer to the I2Cx registers block.
|
|
*/
|
|
I2C_TypeDef *i2c;
|
|
};
|
|
|
|
/*===========================================================================*/
|
|
/* Driver macros. */
|
|
/*===========================================================================*/
|
|
|
|
/**
|
|
* @brief Get errors from I2C driver.
|
|
*
|
|
* @param[in] i2cp pointer to the @p I2CDriver object
|
|
*
|
|
* @notapi
|
|
*/
|
|
#define i2c_lld_get_errors(i2cp) ((i2cp)->errors)
|
|
|
|
/*===========================================================================*/
|
|
/* External declarations. */
|
|
/*===========================================================================*/
|
|
|
|
#if !defined(__DOXYGEN__)
|
|
#if STM32_I2C_USE_I2C1
|
|
extern I2CDriver I2CD1;
|
|
#endif
|
|
|
|
#if STM32_I2C_USE_I2C2
|
|
extern I2CDriver I2CD2;
|
|
#endif
|
|
|
|
#endif /* !defined(__DOXYGEN__) */
|
|
|
|
#ifdef __cplusplus
|
|
extern "C" {
|
|
#endif
|
|
void i2c_lld_init(void);
|
|
void i2c_lld_start(I2CDriver *i2cp);
|
|
void i2c_lld_stop(I2CDriver *i2cp);
|
|
msg_t i2c_lld_master_transmit_timeout(I2CDriver *i2cp, i2caddr_t addr,
|
|
const uint8_t *txbuf, size_t txbytes,
|
|
uint8_t *rxbuf, size_t rxbytes,
|
|
systime_t timeout);
|
|
msg_t i2c_lld_master_receive_timeout(I2CDriver *i2cp, i2caddr_t addr,
|
|
uint8_t *rxbuf, size_t rxbytes,
|
|
systime_t timeout);
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|
|
|
|
#endif /* HAL_USE_I2C */
|
|
|
|
#endif /* _I2C_LLD_H_ */
|
|
|
|
/** @} */
|